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2797 Commits

Author SHA1 Message Date
Nadav Rotem 1af0c538e0 update checked pattern 
llvm-svn: 139631
 2011-09-13 19:59:18 +00:00
Nadav Rotem 52202fbf2d Add vselect target support for targets that do not support blend but do support 
xor/and/or (For example SSE2).

llvm-svn: 139623
 2011-09-13 19:17:42 +00:00
Bruno Cardoso Lopes bf6e1e2717 Change testcase commandline to be more strict and silence buildbots 
llvm-svn: 139554
 2011-09-12 22:59:26 +00:00
Bruno Cardoso Lopes ff8d8a830e Fix PR10845. SUBREG_TO_REG shouldn't be used when the input and 
destination types are equal!

llvm-svn: 139553
 2011-09-12 22:59:23 +00:00
Bruno Cardoso Lopes 973d2921e8 Revert the wrong part of r139528, and fix testcases. 
llvm-svn: 139541
 2011-09-12 21:24:07 +00:00
Bruno Cardoso Lopes be7a086f58 Not sure how CMPPS and CMPPD had already ever worked, I guess it didn't. 
However with this fix it does now.

Basically the operand order for the x86 target specific node
is not the same as the instruction, but since the intrinsic need that
specific order at the instruction definition, just change the order
during legalization. Also, there were some wrong invertions of condition
codes, such as GE => LE, GT => LT, fix that too. Fix PR10907.

llvm-svn: 139528
 2011-09-12 19:30:40 +00:00
Eli Friedman 501f541b45 Really un-XFAIL the testcase, like I said I would in r139458. 
llvm-svn: 139459
 2011-09-10 02:02:27 +00:00
Richard Trieu d9917bef6c Fixed an assert from: 
assert("not implemented for target shuffle node");

to:

  assert(0 && "not implemented for target shuffle node");

This causes a test failure in CodeGen/X86/palignr.ll which has
been marked as XFAIL for the time being.
Test failure filed at PR10901.

llvm-svn: 139454
 2011-09-10 01:26:21 +00:00
Nadav Rotem de838daefd Implement vector-select support for avx256. Refactor the vblend implementation to have tablegen match the instruction by the node type 
llvm-svn: 139400
 2011-09-09 20:29:17 +00:00
Bruno Cardoso Lopes 46b9cde019 Add a AVX version of a simple i64 -> f64 bitcast. This could be 
triggered using llc with -O0, which wouldn't let it be folded and
expose the lack of this pattern.

llvm-svn: 139320
 2011-09-08 21:52:33 +00:00
Bruno Cardoso Lopes 51920a6191 Reapply testcase from r139309! 
llvm-svn: 139318
 2011-09-08 21:05:43 +00:00
Bruno Cardoso Lopes f483c081b6 Remove this crashing test, until I figure out what's going wrong here 
llvm-svn: 139309
 2011-09-08 18:32:36 +00:00
Bruno Cardoso Lopes fb113a0051 Add AVX versions of blend vector operations and fix some issues noticed 
in Nadav's r139285 and r139287 commits.

1) Rename vsel.ll to a more descriptive name
2) Change the order of BLEND operands to "Op1, Op2, Cond", this is
necessary because PBLENDVB is already used in different places with
this order, and it was being emitted in the wrong way for vselect
3) Add AVX patterns and tests for the same SSE41 instructions

llvm-svn: 139305
 2011-09-08 18:05:08 +00:00
Bruno Cardoso Lopes ea8d803bb0 Fix PR10844: Add patterns to cover non foldable versions of X86vzmovl. 
Triggered using llc -O0. Also fix some SET0PS patterns to their AVX
forms and test it on the testcase.

llvm-svn: 139304
 2011-09-08 18:05:02 +00:00
Nadav Rotem 354b7585de add a testcase for the previous patch 
llvm-svn: 139287
 2011-09-08 08:31:31 +00:00
Eli Friedman 02f2f89a98 Fix atomic load and store on x86 to pass -verify-machineinstrs (and possibly fix some subtle bugs involving passes which check mayStore()). 
This isn't exactly ideal, but it is good enough for the moment.

llvm-svn: 139245
 2011-09-07 18:48:32 +00:00
Duncan Sands 1257042b70 Another forgotten trampoline testcase. 
llvm-svn: 139230
 2011-09-07 10:05:14 +00:00
Devang Patel 9de7a7db26 While sinking machine instructions, sink matching DBG_VALUEs also otherwise live debug variable pass will drop DBG_VALUEs on the floor. 
llvm-svn: 139208
 2011-09-07 00:07:58 +00:00
Jakob Stoklund Olesen 1f72dd40c7 Pseudo CMOV instructions don't clobber EFLAGS. 
The explanation about a 0 argument being materialized as xor is no
longer valid.  Rematerialization will check if EFLAGS is live before
clobbering it.

The code produced by X86TargetLowering::EmitLoweredSelect does not
clobber EFLAGS.

This causes one less testb instruction to be generated in the cmov.ll
test case.

llvm-svn: 139057
 2011-09-02 23:52:55 +00:00
Eli Friedman f3dd6da7a8 Don't fast-isel for atomic load/store; some cases require extra handling missing from fast-isel. 
llvm-svn: 139044
 2011-09-02 22:33:24 +00:00
Duncan Sands 5c04c62765 Darwin wants ctors/dtors to be ordered the other way round to linux. 
llvm-svn: 139015
 2011-09-02 18:07:19 +00:00
Benjamin Kramer 0f6ff8cb2b This test depends on cmov being available. 
llvm-svn: 138954
 2011-09-01 18:40:01 +00:00
Bruno Cardoso Lopes f61d1c072e Fix vbroadcast matching logic to early unmatch if the node doesn't have 
only one use. Fix PR10825.

llvm-svn: 138951
 2011-09-01 18:15:06 +00:00
Andrew Trick 832a6a1909 PreRA scheduler should avoid cloning compares. 
Added canClobberReachingPhysRegUse() to handle a particular pattern in
which a two-address instruction could be forced to interfere with
EFLAGS, causing a compare to be unnecessarilly cloned.
Fixes rdar://problem/5875261

llvm-svn: 138924
 2011-09-01 00:54:31 +00:00
Bill Wendling 55fb73a6e0 Remove old declare statements. 
llvm-svn: 138905
 2011-08-31 21:41:20 +00:00
Bill Wendling 22055c713f Update more tests to the new EH scheme. 
llvm-svn: 138904
 2011-08-31 21:40:15 +00:00
Bill Wendling d4e871404d Update more tests to the new EH scheme. 
llvm-svn: 138903
 2011-08-31 21:39:05 +00:00
David Greene cdef71f4f3 Compress Repeated Byte Output 
Emit a repeated sequence of bytes using .zero.  This saves an enormous
amount of asm file space for certain programs.

llvm-svn: 138864
 2011-08-31 17:30:56 +00:00
Benjamin Kramer 5247ca0ae5 This test requires sse, otherwise x87 ops will block tailcall optimization 
llvm-svn: 138859
 2011-08-31 16:49:05 +00:00
Bruno Cardoso Lopes 9fc6b8be03 - Move all MOVSS and MOVSD patterns close to their definitions 
- Duplicate some store patterns to their AVX forms!
- Catched a bug while restricting the patterns subtarget, fix it
  and update a testcase to check it properly

llvm-svn: 138851
 2011-08-31 03:04:20 +00:00
Evan Cheng cb1e5bae4c Fix (movhps load) lowering / pattern to match more cases. rdar://10050549 
llvm-svn: 138848
 2011-08-31 02:05:24 +00:00
Benjamin Kramer 50cabb5de4 Fix test typo. 
llvm-svn: 138843
 2011-08-31 00:02:59 +00:00
Rafael Espindola 1450f61e8f Add a triple. 
llvm-svn: 138831
 2011-08-30 21:19:37 +00:00
Rafael Espindola 9f2edc8d2c Some test code to check if correct code is being generated. 
Patch by Sanjoy Das.

llvm-svn: 138820
 2011-08-30 19:51:29 +00:00
Eli Friedman 850b9a9a84 Explicitly zero out parts of a vector which are required to be zero by the algorithm in LowerUINT_TO_FP_i32. This only has a substantial effect on the generated code when the input is extracted from a vector register; other ways of loading an i32 do the appropriate zeroing implicitly. Fixes PR10802. 
llvm-svn: 138768
 2011-08-29 21:15:46 +00:00
Duncan Sands 4d63542b82 Fix PR5329: pay attention to constructor/destructor priority 
when outputting them.  With this, the entire LLVM testsuite
passes when built with dragonegg.

llvm-svn: 138724
 2011-08-28 13:17:22 +00:00
Bill Wendling 2f92d2cdae Update to new EH scheme. 
llvm-svn: 138699
 2011-08-27 04:53:41 +00:00
Bill Wendling 46c720994a Cannot have an llvm.eh.exception call in a non-landing pad block. 
llvm-svn: 138698
 2011-08-27 04:53:28 +00:00
Eli Friedman 5e5704277f Add support for generating CMPXCHG16B on x86-64 for the cmpxchg IR instruction. 
llvm-svn: 138660
 2011-08-26 21:21:21 +00:00
Bruno Cardoso Lopes 8347b86293 Add support for AVX 256-bit version of MOVDDUP! 
llvm-svn: 138588
 2011-08-25 21:40:37 +00:00
Bruno Cardoso Lopes 296256fb32 Add support for 256-bit versions of VSHUFPD and VSHUFPS. 
llvm-svn: 138546
 2011-08-25 02:58:26 +00:00
Eli Friedman 9c73a57b20 Hook up 64-bit atomic load/store on x86-32. I plan to write more efficient implementations eventually. 
llvm-svn: 138505
 2011-08-24 22:33:28 +00:00
Eli Friedman 5aabaaa367 Basic tests for atomic load and store on x86. 
llvm-svn: 138486
 2011-08-24 21:16:59 +00:00
Craig Topper de92622aa5 Break 256-bit vector int add/sub/mul into two 128-bit operations to avoid costly scalarization. Fixes PR10711. 
llvm-svn: 138427
 2011-08-24 06:14:18 +00:00
Bruno Cardoso Lopes 9e9f2ce32d Fix a nasty bug where a v4i64 was being wrong emitted with 32-bit 
permutations. Also tidy up some patterns and make them close to their
instruction definition!

llvm-svn: 138392
 2011-08-23 22:06:37 +00:00
Nick Lewycky 4c8ff77f1b PerformSubCombine to work on integers larger than i128. Fixes a crasher. 
llvm-svn: 138354
 2011-08-23 19:01:24 +00:00
Craig Topper 6612e35b0d Add support for breaking 256-bit v16i16 and v32i8 VSETCC into two 128-bit ones, avoiding sclarization. Add vex form of pcmpeqq and pcmpgtq. Fixes more cases for PR10712. 
llvm-svn: 138321
 2011-08-23 04:36:33 +00:00
Bruno Cardoso Lopes 2a3ffb5d97 Introduce a pass to insert vzeroupper instructions to avoid AVX to 
SSE transition penalty. The pass is enabled through the "x86-use-vzeroupper"
llc command line option. This is only the first step (very naive and
conservative one) to sketch out the idea, but proper DFA is coming next
to allow smarter decisions. Comments and ideas now and in further commits
will be very appreciated.

llvm-svn: 138317
 2011-08-23 01:14:17 +00:00
Bruno Cardoso Lopes 74f090d44c Add support for breaking 256-bit int VETCC into two 128-bit ones, 
avoding scalarization of the compare. Reduces code from 59 to 6
instructions. Fix PR10712.

llvm-svn: 138271
 2011-08-22 20:31:04 +00:00
Jakob Stoklund Olesen 90b6018c8f Add test case for r138018. 
llvm-svn: 138033
 2011-08-19 04:30:24 +00:00