7f0e98fd7f
Correct disassembly printing of Thumb2 post-incremented LDRD and STRD.
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llvm-svn: 139639
2011-09-13 20:46:26 +00:00
fba4bd62b1
Add pattern used to match MipsLo, which is needed when the instruction selector
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tries to match a dead MipsLo node (explanation in the link below).
http://article.gmane.org/gmane.comp.compilers.llvm.devel/42757/match=dagcombiner+dead
llvm-svn: 139634
2011-09-13 20:13:58 +00:00
f58d6812a9
Disable tests which generate code for allegrex or psp.
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llvm-svn: 139632
2011-09-13 20:00:35 +00:00
1af0c538e0
update checked pattern
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llvm-svn: 139631
2011-09-13 19:59:18 +00:00
52202fbf2d
Add vselect target support for targets that do not support blend but do support
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xor/and/or (For example SSE2).
llvm-svn: 139623
2011-09-13 19:17:42 +00:00
44ae2da4ec
Teach the Thumb ASM parser that BKPT is allowed in IT blocks, even though it is always executed unconditionally.
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llvm-svn: 139610
2011-09-13 17:59:19 +00:00
c3c60a0882
Fix encoding of Thumb2 shifted register operands with RRX shifts.
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llvm-svn: 139606
2011-09-13 17:34:32 +00:00
e98d8a5c84
Remove filter that was preventing MOVDQU/MOVDQA and their VEX forms from being disassembled. Also added encodings for the other register/register form of these instructions. Fixes PR10848.
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llvm-svn: 139588
2011-09-13 06:54:58 +00:00
f9f68b816b
[indvars] Revert r139579 until 401.bzip -arch i386 miscompilation is fixed. PR10920.
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llvm-svn: 139583
2011-09-13 05:23:49 +00:00
061d811c51
Disable IV rewriting by default. See PR10916.
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llvm-svn: 139579
2011-09-13 03:23:21 +00:00
5b28cc84f0
Generalize test case to handle multiple indvars modes.
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llvm-svn: 139578
2011-09-13 03:17:25 +00:00
1191773a62
Generalize this test's CHECK statements to handle different indvars modes.
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llvm-svn: 139577
2011-09-13 02:46:27 +00:00
57d8afde93
This test only makes sense with -enable-iv-rewrite.
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llvm-svn: 139576
2011-09-13 02:45:26 +00:00
3de5b8e4c1
[indvars] Fix bugs in floating point IV range checks noticed by inspection.
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llvm-svn: 139574
2011-09-13 01:59:32 +00:00
54a109845d
Conditionalize indvars test that relies on SCEV expansion of geps,
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which is only relevant with canonical IVs
llvm-svn: 139556
2011-09-12 23:13:57 +00:00
bf6e1e2717
Change testcase commandline to be more strict and silence buildbots
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llvm-svn: 139554
2011-09-12 22:59:26 +00:00
ff8d8a830e
Fix PR10845. SUBREG_TO_REG shouldn't be used when the input and
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destination types are equal!
llvm-svn: 139553
2011-09-12 22:59:23 +00:00
a8315c3f2b
indvars test only relevant for -enable-iv-rewrite.
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Otherwise this case is now covered by no-iv-rewrite.ll.
llvm-svn: 139552
2011-09-12 22:59:00 +00:00
1b7090c9b3
Fix a failing ELF Thumb test. I _think_ this is right, but it's not totally clear to me what this test is doing. Could someone on an ELF platform check?
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llvm-svn: 139549
2011-09-12 22:40:31 +00:00
2a206c44b7
Thumb2 POP's don't allow the PC as an operand, and PUSH's don't allow the SP either.
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llvm-svn: 139542
2011-09-12 21:28:46 +00:00
973d2921e8
Revert the wrong part of r139528, and fix testcases.
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llvm-svn: 139541
2011-09-12 21:24:07 +00:00
4a9eb5f8dc
Fix encoding of PC-relative LDRSHW with an immediate offset.
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llvm-svn: 139537
2011-09-12 20:36:51 +00:00
d2e61e1f70
Conditionalize indvars tests that rely on SCEV expansion of geps,
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which is relevant with canonical IVs. Anything else being checked by
these tests is already covered by early CSE.
llvm-svn: 139535
2011-09-12 20:26:34 +00:00
be7a086f58
Not sure how CMPPS and CMPPD had already ever worked, I guess it didn't.
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However with this fix it does now.
Basically the operand order for the x86 target specific node
is not the same as the instruction, but since the intrinsic need that
specific order at the instruction definition, just change the order
during legalization. Also, there were some wrong invertions of condition
codes, such as GE => LE, GT => LT, fix that too. Fix PR10907.
llvm-svn: 139528
2011-09-12 19:30:40 +00:00
a9ebf6fb64
Port more encoding tests to decoding tests, and correct an improper Thumb2 pre-indexed load decoding this uncovered.
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llvm-svn: 139522
2011-09-12 18:56:30 +00:00
30e8db98b8
Removing indvars tests that directly test canonical IVs and nothing else.
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llvm-svn: 139518
2011-09-12 18:33:08 +00:00
183013d8d4
Rename -disable-iv-rewrite to -enable-iv-rewrite=false in preparation for default change.
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llvm-svn: 139517
2011-09-12 18:28:44 +00:00
57ca95961b
Fix mistake in test runline.
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llvm-svn: 139505
2011-09-12 17:32:58 +00:00
8c6fb3af6e
Test case for r139453, WidenIV::GetExtendedOperandRecurrence.
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llvm-svn: 139504
2011-09-12 17:20:57 +00:00
97a2a5c4dc
Associate a MemOperand with LDWCP nodes introduced during ISel.
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This information is required if we want LDWCP to be hoisted out of loops.
llvm-svn: 139495
2011-09-12 14:43:23 +00:00
48f2b36911
Fix disassembling of one of the register/register forms of MOVUPS/MOVUPD/MOVAPS/MOVAPD/MOVSS/MOVSD and their VEX equivalents. Fixes PR10877.
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llvm-svn: 139486
2011-09-11 23:19:54 +00:00
a88e356017
Fix disassembling of reverse register/register forms of ADD/SUB/XOR/OR/AND/SBB/ADC/CMP/MOV.
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llvm-svn: 139485
2011-09-11 21:41:45 +00:00
a948cb9058
Fix disassembling of PAUSE instruction. Fixes PR10900. Also fixed NOP disassembling to ignore OpSize and REX.W.
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llvm-svn: 139484
2011-09-11 20:23:20 +00:00
501f541b45
Really un-XFAIL the testcase, like I said I would in r139458.
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llvm-svn: 139459
2011-09-10 02:02:27 +00:00
d9917bef6c
Fixed an assert from:
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assert("not implemented for target shuffle node");
to:
assert(0 && "not implemented for target shuffle node");
This causes a test failure in CodeGen/X86/palignr.ll which has
been marked as XFAIL for the time being.
Test failure filed at PR10901.
llvm-svn: 139454
2011-09-10 01:26:21 +00:00
b908b7af31
Thumb2 parsing and encoding for MOV(immediate).
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Some aliases for MOV(register) also to keep existing T1 tests happy when
run in thumbv7 mode.
llvm-svn: 139440
2011-09-10 00:15:36 +00:00
5624707684
Fix test cases.
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Generate code for Mips32r1 unless a Mips32r2 feature is tested.
llvm-svn: 139433
2011-09-09 23:14:58 +00:00
53db43b560
LDM writeback is not allowed if Rn is in the target register list.
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llvm-svn: 139432
2011-09-09 23:13:33 +00:00
5bfb0e0a85
Fix assembly/disassembly of Thumb2 ADR instructions with immediate operands.
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llvm-svn: 139422
2011-09-09 22:24:36 +00:00
29cfe6c368
Thumb unconditional branches are allowed in IT blocks, and therefore should have a predicate operand, unlike conditional branches.
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llvm-svn: 139415
2011-09-09 21:48:23 +00:00
b7910b79f5
Make the SelectionDAG verify that all the operands of BUILD_VECTOR have the same type. Teach DAGCombiner::visitINSERT_VECTOR_ELT not to make invalid BUILD_VECTORs. Fixes PR10897.
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llvm-svn: 139407
2011-09-09 21:04:06 +00:00
4444daeec5
Drop support for Mips1 and Mips2.
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llvm-svn: 139405
2011-09-09 20:45:50 +00:00
de838daefd
Implement vector-select support for avx256. Refactor the vblend implementation to have tablegen match the instruction by the node type
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llvm-svn: 139400
2011-09-09 20:29:17 +00:00
62c33955e2
Thumb2 assembly parsing and encoding for MLA and MLS.
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llvm-svn: 139399
2011-09-09 20:24:45 +00:00
b4c32d92ea
Thumb2 assembly parsing and encoding for MCR, MCR2, MCRR, MCRR2.
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llvm-svn: 139397
2011-09-09 20:19:28 +00:00
54175d519e
Tidy up formatting a bit.
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llvm-svn: 139396
2011-09-09 20:17:49 +00:00
89b1775256
Thumb2 assembly parsing and encoding for LSL.
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llvm-svn: 139395
2011-09-09 20:05:38 +00:00
2119a62aae
Thumb2 assembly parsing and encoding for LDRT.
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llvm-svn: 139393
2011-09-09 20:02:15 +00:00
9b11580719
Thumb2 assembly parsing and encoding for LDRSHT.
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llvm-svn: 139392
2011-09-09 20:01:18 +00:00
d2165b829f
Thumb2 assembly parsing and encoding for LDRSH.
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llvm-svn: 139391
2011-09-09 19:54:30 +00:00
Owen Anderson