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35 Commits

Author SHA1 Message Date
Matheus Almeida 4b27eb588c [mips][msa] Add DLSA instruction. 
llvm-svn: 201081
 2014-02-10 12:05:17 +00:00
Matheus Almeida 1ace1f1236 [mips][msa] Add insert.d instruction. 
This instruction is only available on Mips64 cores that implement the MSA ASE.

llvm-svn: 200543
 2014-01-31 13:31:20 +00:00
Matheus Almeida ec079d9e1d [mips][msa] Add fill.d instruction. 
This instruction is only available on Mips64 cores
that implement the MSA ASE.

llvm-svn: 200400
 2014-01-29 15:12:02 +00:00
Matheus Almeida 74070327b2 [mips][msa] Add copy_{u,s}.d. 
These instructions are only available on Mips64 cores
that implement the MSA ASE.

llvm-svn: 200398
 2014-01-29 14:05:28 +00:00
Matheus Almeida 180d97dcdf [mips][msa] Update format of RUN lines for every MSA MC test. 
1. The arch directive now appears before the cpu directive
2. Long run lines were split across multiple lines
    
No functional changes.

llvm-svn: 197588
 2013-12-18 17:31:21 +00:00
Matheus Almeida a3aeed8c44 [mips][msa] Remove unneeded triple directive in MSA MC tests. 
No functional changes.

llvm-svn: 197559
 2013-12-18 11:06:13 +00:00
Matheus Almeida 6b59c449d9 [mips][msa] Fix issue with immediate fields of LD/ST instructions 
not being correctly encoded/decoded.
In more detail, immediate fields of LD/ST instructions should be
divided/multiplied by the size of the data format before encoding and
after decoding, respectively.

llvm-svn: 196494
 2013-12-05 11:06:22 +00:00
Matheus Almeida 50c6e82222 [mips][msa] Update encoding of bnz.v (typo). 
Note that there's no hardware yet that relies on that encoding.

llvm-svn: 195006
 2013-11-18 13:09:54 +00:00
Matheus Almeida 779c593708 [mips][msa] Fix immediate value of LSA instruction as it was being wrongly encoded. 
The immediate field should be encoded as "imm - 1" as the CPU always adds one to that field.

llvm-svn: 195004
 2013-11-18 12:32:49 +00:00
Matheus Almeida a3bac16950 [mips][msa] Update encoding of LDI instruction. 
The encoding was updated in MSA r1.07.

llvm-svn: 194255
 2013-11-08 10:43:11 +00:00
Matheus Almeida be8681b461 [mips][msa] Direct Object Emission support for the LSA instruction. 
llvm-svn: 193240
 2013-10-23 13:20:07 +00:00
Matheus Almeida eb68d9d985 [mips][msa] Direct Object Emission support for conditional branches. 
These branches have a 16-bit offset (R_MIPS_PC16).

List of conditional branch instructions:
bnz.{b,h,w,d}
bnz.v
bz.{b,h,w,d}
bz.v

llvm-svn: 193157
 2013-10-22 09:43:32 +00:00
Matheus Almeida fe0bf9f618 [mips][msa] Direct Object Emission support for LD/ST instructions. 
llvm-svn: 193082
 2013-10-21 13:07:13 +00:00
Matheus Almeida 8ddad15177 [mips][msa] Direct Object Emission support for LDI instructions. 
llvm-svn: 193081
 2013-10-21 12:56:20 +00:00
Matheus Almeida 83d797de4a [mips][msa] Direct Object Emission support for MOVE.v. 
llvm-svn: 193080
 2013-10-21 12:43:54 +00:00
Matheus Almeida a591fdc63c [mips][msa] Direct Object Emission support for CTCMSA and CFCMSA. 
These instructions are logically related as they allow read/write of MSA control registers.
Currently MSA control registers are emitted by number but hopefully that will change as soon 
as GAS starts accepting them by name as that would make the assembly easier to read.

llvm-svn: 193078
 2013-10-21 12:26:50 +00:00
Matheus Almeida 5798c6f3bb [mips][msa] Direct Object Emission of SPLAT instruction. 
llvm-svn: 193077
 2013-10-21 12:07:26 +00:00
Matheus Almeida 70fbf77546 [mips][msa] Fix definition of SLD instruction. 
The second parameter of the SLD intrinsic is the number of columns (GPR) to 
slide left the source array.

llvm-svn: 193076
 2013-10-21 11:47:56 +00:00
Matheus Almeida 2102188cfc [mips][msa] Direct Object Emission support for BIT instructions. 
List of instructions:
bclri.{b,h,w,d}
binsli.{b,h,w,d}
binsri.{b,h,w,d}
bnegi.{b,h,w,d}
bseti.{b,h,w,d}
sat_s.{b,h,w,d}
sat_u.{b,h,w,d}
slli.{b,h,w,d}
srai.{b,h,w,d}
srari.{b,h,w,d}
srli.{b,h,w,d}
srlri.{b,h,w,d}

llvm-svn: 192589
 2013-10-14 13:07:39 +00:00
Matheus Almeida 5be0cd8720 [mips][msa] Direct Object Emission support for VEC instructions. 
List of instructions:
and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.v.

llvm-svn: 192588
 2013-10-14 12:57:18 +00:00
Matheus Almeida 7d65ea76ea [mips][msa] Direct Object Emission of INSVE.{b,h,w,d}. 
llvm-svn: 192587
 2013-10-14 12:38:17 +00:00
Matheus Almeida bc189eb318 [mips][msa] Direct Object Emission for the majority of the ELM instructions. 
List of instructions:
copy_s.{b,h,w}
copy_u.{b,h,w}
sldi.{b,h,w,d}
splati.{b,h,w,d}

llvm-svn: 192586
 2013-10-14 12:22:43 +00:00
Matheus Almeida b74293dc55 [mips][msa] Direct Object Emission of INSERT.{B,H,W} instruction. 
INSERT is the first type of MSA instruction that requires a change to the way
MSA registers are parsed. This happens because MSA registers may be suffixed by
an index in the form of an immediate or a general purpose register. The changes
to parseMSARegs reflect that requirement.

llvm-svn: 192582
 2013-10-14 11:49:30 +00:00
Matheus Almeida 3372c6adb1 This reverts 192447 because of compiler warning generated on darwin build. 
llvm-svn: 192451
 2013-10-11 13:58:32 +00:00
Matheus Almeida 599446af66 This reverts r192449 because of compiler warning generated on darwin build. 
llvm-svn: 192450
 2013-10-11 13:56:12 +00:00
Matheus Almeida aa5138b538 [mips][msa] Direct Object Emission for the majority of the ELM instructions. 
llvm-svn: 192449
 2013-10-11 13:39:49 +00:00
Matheus Almeida 3d0933c425 [mips][msa] Direct Object Emission of INSERT.{B,H,W} instruction. 
INSERT is the first type of MSA instruction that requires a change to the way MSA registers are parsed. 
This happens because MSA registers may be suffixed by an index in the form of an immediate or a
 general purpose register. The changes to parseMSARegs reflect that requirement.

llvm-svn: 192447
 2013-10-11 13:29:36 +00:00
Jack Carter 8ff70e3e26 [mips][msa] Direct Object Emission for I8 instructions. 
This patch adds Direct Object Emission support for I8 instructions: andi.b, bmnzi.b, bmzi.b, bseli.b, nori.b, ori.b, shf.{b,h,w} and xori.b.


Patch by Matheus Almeida

llvm-svn: 191688
 2013-09-30 18:05:18 +00:00
Jack Carter c3b25686b9 [mips][msa] Direct Object Emission for I5 instructions. 
This patch adds Direct Object Emission support for I5 instructions: addvi.{b,h,w,d}, ceqi.{b,h,w,d}, clei_s.{b,h,w,d}, clei_u.{b,h,w,d}, clti_s.{b,h,w,d}, clti_u.{b,h,w,d}, maxi_s.{b,h,w,d}, maxi_u.{b,h,w,d}, mini_s.{b,h,w,d}, mini_u.{b,h,w,d}, subvi.{b,h,w,d}.


Patch by Matheus Almeida

llvm-svn: 191687
 2013-09-30 17:58:07 +00:00
Jack Carter 92e6e0f171 [mips][msa] Direct Object Emission for 2R instructions. 
This patch adds Direct Object Emission support for 2R instructions: nloc.{b,h,w}, nlzc.{b,h,w}, pcnt.{b,w,d}.  


Patch by Matheus Almeida

llvm-svn: 191685
 2013-09-30 17:52:33 +00:00
Jack Carter 6eed9cc6a8 [PATCH 1/4] [mips][msa] Source register of FILL instructions is GPR 
and not an MSA register

Patch by Matheus Almeida

llvm-svn: 191684
 2013-09-30 17:43:04 +00:00
Jack Carter cb8b40b08d [mips][msa] Direct Object Emission for 3RF instructions. 
Patch by Matheus Almeida

llvm-svn: 191461
 2013-09-26 21:31:43 +00:00
Jack Carter 3eb663b037 [mips][msa] Direct Object Emission for 3R instructions. 
This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class.
 
Patch by Matheus Almeida

llvm-svn: 191415
 2013-09-26 00:09:46 +00:00
Jack Carter 3381298227 [mips][msa] Direct Object Emission for 2RF instructions. 
Patch by Matheus Almeida

llvm-svn: 191413
 2013-09-25 23:56:25 +00:00
Jack Carter 5dc8ac92b9 [mips][msa] Direct Object Emission support for the MSA instruction set. 
In more detail, this patch adds the ability to parse, encode and decode MSA registers ($w0-$w31). The format of 2RF instructions (MipsMSAInstrFormat.td) was updated so that we could attach a test case to this patch i.e., the test case parses, encodes and decodes 2 MSA instructions. Following patches will add the remainder of the instructions.

Note that DecodeMSA128BRegisterClass is missing from MipsDisassembler.td because it's not yet required at this stage and having it would cause a compiler warning (unused function).

Patch by Matheus Almeida

llvm-svn: 191412
 2013-09-25 23:50:44 +00:00