Commit Graph

292543 Commits

Author SHA1 Message Date
Simon Pilgrim 5b6b500687 Fix -Wparentheses gcc warning. NFCI.
llvm-svn: 335451
2018-06-25 11:19:05 +00:00
Clement Courbet e2fc89fdd6 [llvm-exegesis][NFC] Fix `Operand` class comments.
llvm-svn: 335450
2018-06-25 11:12:30 +00:00
Krasimir Georgiev 0895f5e8b9 [clang-format] Fix end-of-file comments text proto formatting
Summary:
The case of end-of-file comments was formatted badly:
```
key: value
    # end-of-file comment
```
This patch fixes that formatting:
```
key: value
# end-of-file comment
```

Subscribers: cfe-commits

Differential Revision: https://reviews.llvm.org/D48539

llvm-svn: 335449
2018-06-25 11:08:24 +00:00
Jonas Devlieghere c1cc3173d3 Revert "[FileSpec] Always normalize"
This reverts r335432 because remove_dots() is expensive and measuring
its impact showed an observable performance regression
(https://reviews.llvm.org/D45977#1078510).

llvm-svn: 335448
2018-06-25 10:11:53 +00:00
George Rimar 2051bd02a7 [ELF] - Replace llvm::find_if with the loop. NFC.
Requested during post commit review.

llvm-svn: 335447
2018-06-25 09:30:39 +00:00
Craig Topper facea6b4a6 [X86] Block commuting operand 1 of FMA*_Int instructions in findThreeSrcCommutedOpIndices. Remove uncommutable returns from getThreeSrcCommuteCase/getFMA3OpcodeToCommuteOperands.
We should be blocking the operand while we are in the routine that tries to find commutable operand indices. Doing it later means we might have missed out on another valid set of operands we could have commuted.

The intrinsic case was the only case that could really prevent commuting in getFMA3OpcodeToCommuteOperands. All the other cases in getThreeSrcCommuteCase were not reachable conditions as they were protected by findThreeSrcCommutedOpIndices.

With that abort case pushed earlier, we can remove all the abort checks and replace with asserts.

llvm-svn: 335446
2018-06-25 06:05:37 +00:00
Igor Kudrin eff8f9d178 [CodeGen] Provide source locations for UBSan type checks when emitting constructor calls.
Differential Revision: https://reviews.llvm.org/D48531

llvm-svn: 335445
2018-06-25 05:48:04 +00:00
George Burgess IV 97ec62455d [MSSA] Add domination number verifier; NFC
It's easy for domination numbers to get out-of-date, and this is no more
costly than any of the other verifiers we already have, so it seems nice
to have.

A stage3 build with this Works On My Machine, so this hasn't caught any
bugs... yet. :)

llvm-svn: 335444
2018-06-25 05:30:36 +00:00
Zachary Turner eee66518af One more build fix for non MSVC compilers.
llvm-svn: 335443
2018-06-25 04:38:03 +00:00
Zachary Turner ad45f93e89 Try to fix build error on non MSVC compilers.
llvm-svn: 335442
2018-06-25 04:35:35 +00:00
Zachary Turner 72b3f5fb0f Fix CRLF line endings.
llvm-svn: 335441
2018-06-25 03:13:27 +00:00
Zachary Turner 35169f6698 Add a TaskQueue that can serialize work on a ThreadPool.
We have ThreadPool, which can execute work asynchronously on N
background threads, but sometimes you need to make sure the work
is executed asynchronously but also serially.  That is, if task
B is enqueued after task A, then task B should not begin until
task A has completed.  This patch adds such a class.

Differential Revision: https://reviews.llvm.org/D48240

llvm-svn: 335440
2018-06-25 03:13:09 +00:00
Heejin Ahn 04c4894911 [WebAssembly] Add WebAssemblyException information analysis
Summary:
A WebAssemblyException object contains BBs that belong to a 'catch' part
of the try-catch-end structure. Because CFGSort requires all the BBs
within a catch part to be sorted together as it does for loops, this
pass calculates the nesting structure of catch part of exceptions in a
function. Now this assumes the use of Windows EH instructions.

Reviewers: dschuff, majnemer

Subscribers: jfb, mgorny, sbc100, jgravelle-google, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D44134

llvm-svn: 335439
2018-06-25 01:20:21 +00:00
Heejin Ahn 4934f76b58 [WebAssembly] Add WebAssemblyLateEHPrepare pass
Summary:
Add WebAssemblyLateEHPrepare pass that does several small jobs for
exception handling. This runs before CFGSort, and is different from
WasmEHPrepare pass that runs before ISel, even though the names are
similar.

Reviewers: dschuff, majnemer

Subscribers: sbc100, jgravelle-google, sunfish, mgorny, llvm-commits

Differential Revision: https://reviews.llvm.org/D46803

llvm-svn: 335438
2018-06-25 01:07:11 +00:00
Craig Topper 3b18bdc46d [X86] Simplify some code by using isOneConstant. NFC
llvm-svn: 335437
2018-06-25 01:01:47 +00:00
Craig Topper 4331d6218d [X86] Remove the changes to combineScalarToVector made in r335037.
They appear to be untested other than the test case for p37879.ll and I believe we should be using SimplifyDemandedElts here to handle these cases.

llvm-svn: 335436
2018-06-25 00:21:53 +00:00
Craig Topper ecf7c5b75f [X86] Reduce the number of patterns needed for masked scalar ceil/floor isel.
The scalar to vector on the mask register should not be part of the patterns.

llvm-svn: 335435
2018-06-25 00:05:09 +00:00
Brad Smith df1f50579f [mips][ias] Enable IAS by default for OpenBSD / FreeBSD mips64/mips64el.
Reviewers: atanasyan

Differential Review: https://reviews.llvm.org/D31557

llvm-svn: 335434
2018-06-24 15:44:47 +00:00
Sanjay Patel 962ee178fa [DAGCombiner] eliminate setcc bool math when input is low-bit of some value
This patch has the same motivating example as D48466:
define void @foo(i64 %x, i32 %c.0282.in, i32 %d.0280, i32* %ptr0, i32* %ptr1) {
    %c.0282 = and i32 %c.0282.in, 268435455
    %a16 = lshr i64 32508, %x
    %a17 = and i64 %a16, 1
    %tobool = icmp eq i64 %a17, 0
    %. = select i1 %tobool, i32 1, i32 2
    %.286 = select i1 %tobool, i32 27, i32 26
    %shr97 = lshr i32 %c.0282, %.
    %shl98 = shl i32 %c.0282.in, %.286
    %or99 = or i32 %shr97, %shl98
    %shr100 = lshr i32 %d.0280, %.
    %shl101 = shl i32 %d.0280, %.286
    %or102 = or i32 %shr100, %shl101
    store i32 %or99, i32* %ptr0
    store i32 %or102, i32* %ptr1
    ret void
}

...but I'm trying to kill the setcc bool math sooner rather than later.

By matching a larger pattern that includes both the low-bit mask and the trailing add/sub, 
we can create a universally good fold because we always eliminate the condition code 
intermediate value.

Here are Alive proofs for these (currently instcombine folds the 'add' variants, but 
misses the 'sub' patterns):
https://rise4fun.com/Alive/Gsyp

Name: sub of zext cmp mask
  %a = and i8 %x, 1
  %c = icmp eq i8 %a, 0
  %z = zext i1 %c to i32
  %r = sub i32 C1, %z
  =>
  %optional_cast = zext i8 %a to i32
  %r = add i32 %optional_cast, C1-1

Name: add of zext cmp mask
  %a = and i32 %x, 1
  %c = icmp eq i32 %a, 0
  %z = zext i1 %c to i8
  %r = add i8 %z, C1
  =>
  %optional_cast = trunc i32 %a to i8
  %r = sub i8 C1+1, %optional_cast

All of the tests look like improvements or neutral to me. But it is possible that x86 
test+set+bitop is better than what we now show here. I suspect we could do better by 
adding another fold for the 'sub' variants.

We start with select-of-constant in IR in the larger motivating test, so that's why I 
included tests with selects. Proofs for those variants:
https://rise4fun.com/Alive/Bx1

Name: true const is bigger
Pre: C2 == (C1 + 1)
  %a = and i8 %x, 1
  %c = icmp eq i8 %a, 0
  %r = select i1 %c, i64 C2, i64 C1
  =>
  %z = zext i8 %a to i64
  %r = sub i64 C2, %z

Name: false const is bigger
Pre: C2 == (C1 + 1)
  %a = and i8 %x, 1
  %c = icmp eq i8 %a, 0
  %r = select i1 %c, i64 C1, i64 C2
  =>
  %z = zext i8 %a to i64
  %r = add i64 C1, %z

Differential Revision: https://reviews.llvm.org/D48466

llvm-svn: 335433
2018-06-24 14:37:30 +00:00
Jonas Devlieghere 4c92584eb2 [FileSpec] Always normalize
Removing redundant components from the path seems pretty harmless.
Rather than checking whether this is necessary and then actually doing
so, always invoke remove_dots to start with a normalized path.

llvm-svn: 335432
2018-06-24 13:31:44 +00:00
Jan Kratochvil 8fbb1fc229 Make testcase classnames unique
Filenames with test results contain only the class name which makes it more
difficult to find it if the same class name is present in multiple *.py files.

packages/Python/lldbsuite/test/functionalities/step-avoids-no-debug/TestStepNoDebug.py
-class ReturnValueTestCase(TestBase):
+class StepAvoidsNoDebugTestCase(TestBase):
as ReturnValueTestCase is already present in:
packages/Python/lldbsuite/test/functionalities/return-value/TestReturnValue.py

packages/Python/lldbsuite/test/functionalities/thread/crash_during_step/TestCrashDuringStep.py
-class CreateDuringStepTestCase(TestBase):
+class CrashDuringStepTestCase(TestBase):
as CreateDuringStepTestCase is already present in:
packages/Python/lldbsuite/test/functionalities/thread/create_during_step/TestCreateDuringStep.py

packages/Python/lldbsuite/test/functionalities/thread/step_until/TestStepUntil.py
-class TestCStepping(TestBase):
+class StepUntilTestCase(TestBase):
as TestCStepping is already present in:
packages/Python/lldbsuite/test/lang/c/stepping/TestStepAndBreakpoints.py

llvm-svn: 335431
2018-06-24 10:36:44 +00:00
Jonas Devlieghere 24bd63c462 [FileSpec] Refactor append and prepend implemenetations. NFC
Replaces custom implementations of append and prepend with calls to
llvm's path library. This is part of a series of patches (started in
D48084) to delegate common operations to llvm::sys::path.

llvm-svn: 335430
2018-06-24 10:18:01 +00:00
Craig Topper 03523f6741 [X86] Regroup some isel patterns. NFC
For some reason the 64-bit patterns were separated from their 8/16/32-bit friends, but only for add/sub/mul. For and/or/xor they were together.

llvm-svn: 335429
2018-06-24 06:56:49 +00:00
Craig Topper 19772c89c7 [X86] Rename VFPCLASSSS and VFPCLASSSD internal instruction names to include a Z to match other EVEX instructions.
llvm-svn: 335428
2018-06-24 06:29:50 +00:00
Zachary Turner aa202f03f7 Also forward declare BitScanReverse.
With the removal of intrin.h in an earlier patch, the intrinsics
that we were actually using were manually re-declared, however
several of them were missed leading to compilation failures with
MSVC.  Fix those.

llvm-svn: 335427
2018-06-24 01:48:25 +00:00
Brad Smith 8c17d5921d Add OpenBSD support to the Threading code
llvm-svn: 335426
2018-06-23 22:02:59 +00:00
Brad Smith 3baae56a03 [CMake] Do not use --gc-sections on OpenBSD
llvm-svn: 335425
2018-06-23 21:43:27 +00:00
Brad Smith ee0e66026b [CMake] Support building shared library for OpenBSD
llvm-svn: 335424
2018-06-23 21:26:44 +00:00
Jonas Devlieghere 77fa07264a [llc] Fix sanitizer failure.
Store the string on the stack rather than just the StringRef.

Fix sanitizer bots:

  http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-fast/builds/19948
  http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-bootstrap-msan/builds/5500

llvm-svn: 335423
2018-06-23 19:04:10 +00:00
Brian Gesiak 12728474b3 [Coroutines] Less IR for noexcept await_resume
Summary:
In his review of https://reviews.llvm.org/D45860, @GorNishanov suggested
avoiding generating additional exception-handling IR in the case that
the resume function was marked as 'noexcept', and exceptions could not
occur. This implements that suggestion.

Test Plan: `check-clang`

Reviewers: GorNishanov, EricWF

Reviewed By: GorNishanov

Subscribers: cfe-commits, GorNishanov

Differential Revision: https://reviews.llvm.org/D47673

llvm-svn: 335422
2018-06-23 18:57:26 +00:00
Duncan P. N. Exon Smith f4c82cffc6 ADT: Use EBO to shrink SmallVector size 1
SmallVectorStorage is empty when its size is 1; use inheritance so that
the empty base class optimization kicks in.

llvm-svn: 335421
2018-06-23 18:39:44 +00:00
Brian Gesiak c1b173a636 [Sema] isValidCoroutineContext FIXME and citations
Summary:
Add citations to the Coroutines TS to the `isValidCoroutineContext`
function, as well as a FIXME and test for [expr.await]p2, which states
a co_await expression cannot be used in a default argument.

Test Plan: check-clang

Reviewers: GorNishanov, EricWF

Reviewed By: GorNishanov

Subscribers: rsmith, cfe-commits

Differential Revision: https://reviews.llvm.org/D48519

llvm-svn: 335420
2018-06-23 18:01:02 +00:00
Reid Kleckner e7a7a5057b Attempt to fix latent tablegen dependency issue
llvm-svn: 335419
2018-06-23 17:32:51 +00:00
Jonas Devlieghere 7762484459 [llc] Use WithColor for printing errors/warnings
Use the WithColor helper from support to print errors and warnings.

llvm-svn: 335418
2018-06-23 16:51:10 +00:00
Jonas Devlieghere 7513a1bf5a [llvm-config] Use WithColor for printing errors.
Use the WithColor helper from support to print errors.

llvm-svn: 335417
2018-06-23 16:50:09 +00:00
Jonas Devlieghere fb54074112 [llvm-mt] Use WithColor for printing errors.
Use the WithColor helper from support to print errors.

llvm-svn: 335416
2018-06-23 16:49:07 +00:00
Jonas Devlieghere c02bf01f64 [TableGen] Use WithColor for printing errors/warnings
Use the WithColor helper from support to print errors and warnings.

llvm-svn: 335415
2018-06-23 16:48:03 +00:00
Craig Topper d8d64a56b5 [X86] Make %eiz usage in 64-bit mode, force a 0x67 address size prefix. Fix some test CHECK lines.
llvm-svn: 335414
2018-06-23 06:15:04 +00:00
Craig Topper 2545529034 [X86] Teach disassembler to use %eip instead of %rip when 0x67 prefix is used on a rip-relative address.
llvm-svn: 335413
2018-06-23 06:03:48 +00:00
Craig Topper 68d64e3859 [X86][AsmParser] Improve base/index register checks.
-Ensure EIP isn't used with an index reigster.
-Ensure EIP isn't used as index register.
-Ensure base register isn't a vector register.
-Ensure eiz/riz usage matches the size of their base register.

llvm-svn: 335412
2018-06-23 05:53:00 +00:00
Stanislav Mekhanoshin d8c9374797 Fix invariant fdiv hoisting in LICM
FDiv is replaced with multiplication by reciprocal and invariant
reciprocal is hoisted out of the loop, while multiplication remains
even if invariant.

Switch checks for all invariant operands and only invariant
denominator to fix the issue.

Differential Revision: https://reviews.llvm.org/D48447

llvm-svn: 335411
2018-06-23 04:01:28 +00:00
Petr Hosek 96917d7912 [Fuchsia] Enable static libc++, libc++abi, libunwind
This is needed for building Fuchsia drivers.

Differential Revision: https://reviews.llvm.org/D48208

llvm-svn: 335410
2018-06-23 03:15:07 +00:00
Reid Kleckner fd7c9ab971 [AMDGPU] Update includes for intrinsic changes :(
llvm-svn: 335409
2018-06-23 03:05:39 +00:00
Lang Hames d716a26e8b [ORC] Fix formatting and list pending queries in VSO::dump.
llvm-svn: 335408
2018-06-23 02:22:10 +00:00
Reid Kleckner f5890e4e43 [IR] Split Intrinsics.inc into enums and implementations
Implements PR34259

Intrinsics.h is a very popular header. Most LLVM TUs care about things
like dbg_value, but they don't care how they are implemented. After I
split these out, IntrinsicImpl.inc is 1.7 MB, so this saves each LLVM TU
from scanning 1.7 MB of source that gets pre-processed away.

It also means we can modify intrinsic properties without triggering a
full rebuild, but that's probably less of a win.

I think the next best thing to do would be to split out the target
intrinsics into their own header. Very, very few TUs care about
target-specific intrinsics. It's very hard to split up the target
independent intrinsics like llvm.expect, assume, and dbg.value, though.

llvm-svn: 335407
2018-06-23 02:02:38 +00:00
Reid Kleckner 5c25346912 Avoid including intrin.h from MathExtras.h
This is repeatably worth 0.3s compile time on MathExtras.cpp. This is a
very popular header, and it basically pulls all Intel intrinsics into
every LLVM TU. Let's not do that.

llvm-svn: 335406
2018-06-23 01:19:49 +00:00
Fangrui Song 4ef42a83f9 [ELF] Change isSectionData to exclude SHF_EXECINSTR
Summary:
This affects what sections are displayed as "DATA" in llvm-objdump.
The other user llvm-size is unaffected.

Before, a "TEXT" section is also "DATA", which seems weird.
The sh_flags condition matches that of bfd's SEC_DATA but the sh_type
condition uses (== SHF_PROGBITS) instead of bfd's (!= SHT_NOBITS).
bfd's SEC_DATA is not appealing as so many sections will be shown as DATA.

Reviewers: jyknight, Bigcheese

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D48472

llvm-svn: 335405
2018-06-23 00:15:33 +00:00
Fangrui Song e737e75491 [ELF] Change llvm-objdump output for D48472: TEXT DATA -> TEXT
Reviewers: jyknight, Bigcheese, espindola

Subscribers: emaste, arichardson, llvm-commits

Differential Revision: https://reviews.llvm.org/D48473

llvm-svn: 335404
2018-06-23 00:15:23 +00:00
Craig Topper abdbb2c67a [X86][AsmParser] Rework that allows (%dx) to be used in place of %dx with in/out instructions.
Previously, to support (%dx) we left a wide open hole in our 16-bit memory address checking. This let this address value be used with any instruction without error in the parser. It would later fail in the encoder with an assertion failure on debug builds and who knows what on release builds.

This patch passes the mnemonic down to the memory operand parsing function so we can allow the (%dx) form only on specific instructions.

llvm-svn: 335403
2018-06-23 00:03:20 +00:00
Reid Kleckner 330f65b3e8 [RuntimeDyld] Implement the ELF PIC large code model relocations
Prerequisite for https://reviews.llvm.org/D47211 which improves our ELF
large PIC codegen.

llvm-svn: 335402
2018-06-22 23:53:22 +00:00