0d928a142b
Add support for the X86 secure guard extensions instructions in assembler (SGX).
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This allows assembling the two new instructions, encls and enclu for the
SKX processor model.
Note the diffs are a bigger than what might think, but to fit the new
MRM_CF and MRM_D7 in things in the right places things had to be
renumbered and shuffled down causing a bit more diffs.
rdar://16228228
llvm-svn: 214460
2014-07-31 23:57:38 +00:00
595683da00
[SKX] Enabling mask logic instructions: encoding, lowering
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Instructions: KAND{BWDQ}, KANDN{BWDQ}, KOR{BWDQ}, KXOR{BWDQ}, KXNOR{BWDQ}
Reviewed by Elena Demikhovsky <elena.demikhovsky@intel.com>
llvm-svn: 214081
2014-07-28 13:46:45 +00:00
74acbb7767
[SKX] Enabling mask instructions: encoding, lowering
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KMOVB, KMOVW, KMOVD, KMOVQ, KNOTB, KNOTW, KNOTD, KNOTQ
Reviewed by Elena Demikhovsky <elena.demikhovsky@intel.com>
llvm-svn: 213757
2014-07-23 14:49:42 +00:00
bfa0131365
[SKX] Enabling SKX target and AVX512BW, AVX512DQ, AVX512VL features.
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Enabling HasAVX512{DQ,BW,VL} predicates.
Adding VK2, VK4, VK32, VK64 masked register classes.
Adding new types (v64i8, v32i16) to VR512.
Extending calling conventions for new types (v64i8, v32i16)
Patch by Zinovy Nis <zinovy.y.nis@intel.com>
Reviewed by Elena Demikhovsky <elena.demikhovsky@intel.com>
llvm-svn: 213545
2014-07-21 14:54:21 +00:00
5933c2f824
[X86] AVX512: Add disassembler support for compressed displacement
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There are two parts here. First is to modify tablegen to adjust the encoding
type ENCODING_RM with the scaling factor.
The second is to use the new encoding types to compute the correct
displacement in the decoder.
Fixes <rdar://problem/17608489>
llvm-svn: 213281
2014-07-17 17:04:56 +00:00
2406477179
[C++11] More 'nullptr' conversion. In some cases just using a boolean check instead of comparing to nullptr.
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llvm-svn: 206254
2014-04-15 07:20:03 +00:00
e413b628f8
[x86] Simplify disassembler code slightly.
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llvm-svn: 202233
2014-02-26 06:01:21 +00:00
e2347df24d
[x86] Switch PAUSE instruction to use XS prefix instead of HasREPPrefix. Remove HasREPPrefix support from disassembler table generator since its now only used by CodeGenOnly instructions.
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llvm-svn: 201767
2014-02-20 07:59:43 +00:00
56f0ed815e
Remove special FP opcode maps and instead add enough MRM_XX formats to handle all the FP operations. This increases format by 1 bit, but decreases opcode map by 1 bit so the TSFlags size doesn't change.
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llvm-svn: 201649
2014-02-19 08:25:02 +00:00
2fb696b214
Put some of the X86 formats in a more logical order.
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llvm-svn: 201645
2014-02-19 06:59:13 +00:00
0d1fd55c13
Remove A6/A7 opcode maps. They can all be handled with a TB map, opcode of 0xa6/0xa7, and adding MRM_C0/MRM_E0 forms. Removes 376K from the disassembler tables.
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llvm-svn: 201641
2014-02-19 05:34:21 +00:00
5ccb61781f
Add an x86 prefix encoding for instructions that would decode to a different instruction with 0xf2/f3/66 were in front of them, but don't themselves have a prefix. For now this doesn't change any bbehavior, but plan to use it to fix some bugs in the disassembler.
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llvm-svn: 201538
2014-02-18 00:21:49 +00:00
69e245c01d
Remove filtering concept from X86 disassembler table generation. It's no longer necessary.
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llvm-svn: 201299
2014-02-13 07:07:16 +00:00
5b3a6bd370
Remove special case filtering for instructions with lock prefix as they are all marked with isCodeGenOnly already.
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llvm-svn: 201216
2014-02-12 08:09:20 +00:00
ea91f02762
Mark XACQUIRE_PREFIX/XRELEASE_PREFIX as isAsmParserOnly so they'll disappear from the disassembler table build without custom filtering code.
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llvm-svn: 201215
2014-02-12 08:02:29 +00:00
a0869dceea
Recommit r201059 and r201060 with hopefully a fix for its original failure.
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Original commits messages:
Add MRMXr/MRMXm form to X86 for use by instructions which treat the 'reg' field of modrm byte as a don't care value. Will allow for simplification of disassembler code.
Simplify a bunch of code by removing the need for the x86 disassembler table builder to know about extended opcodes. The modrm forms are sufficient to convey the information.
llvm-svn: 201065
2014-02-10 06:55:41 +00:00
ebdae7c2ff
Revert r201059 and r201060.
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r201059 appears to cause a crash in a bootstrapped build of clang. Craig
isn't available to look at it right now, so I'm reverting it while he
investigates.
llvm-svn: 201064
2014-02-10 05:28:30 +00:00
0a43c2c393
Simplify a bunch of code by removing the need for the x86 disassembler table builder to know about extended opcodes. The modrm forms are sufficient to convey the information.
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llvm-svn: 201060
2014-02-10 01:58:12 +00:00
0d88de8c56
Add MRMXr/MRMXm form to X86 for use by instructions which treat the 'reg' field of modrm byte as a don't care value. Will allow for simplification of disassembler code.
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llvm-svn: 201059
2014-02-10 00:50:34 +00:00
fa6298a162
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64.
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llvm-svn: 200626
2014-02-02 09:25:09 +00:00
8e92e85ac7
Simplify some code since VEX and EVEX instructions never have HasOpSizePrefix.
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llvm-svn: 200625
2014-02-02 07:46:05 +00:00
d402df3ce8
Merge HasVEXPrefix/HasEVEXPrefix/HasXOPPrefix into a 2-bit 'encoding' field in TSFlags.
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llvm-svn: 200624
2014-02-02 07:08:01 +00:00
10243c8907
Separate x86 opcode maps and 0x66/0xf2/0xf3 prefixes from each other in the TSFlags. This greatly simplifies the switch statements in the disassembler tables and the code emitters.
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llvm-svn: 200522
2014-01-31 08:47:06 +00:00
ec68866f55
Move REP out of the Prefix field of the X86 format. Give it its own bit. It had special handling anyway and this enables a future patch.
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llvm-svn: 200520
2014-01-31 07:00:55 +00:00
9bbf7ca13d
]x86] Allow segment and address-size overrides for CMPS[BWLQ] (PR9385)
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llvm-svn: 199806
2014-01-22 15:08:36 +00:00
b33c2ef215
[x86] Allow address-size overrides for STOS[BWLQ] (PR9385)
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llvm-svn: 199804
2014-01-22 15:08:21 +00:00
2ef8d9c05c
[x86] Allow segment and address-size overrides for LODS[BWLQ] (PR9385)
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llvm-svn: 199803
2014-01-22 15:08:08 +00:00
caaa2850c0
[x86] Fix disassembly of MOV16ao16 et al.
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The addition of IC_OPSIZE_ADSIZE in r198759 wasn't quite complete. It
also turns out to have been unnecessary. The disassembler handles the
AdSize prefix for itself, and doesn't care about the difference between
(e.g.) MOV8ao8 and MOB8ao8_16 definitions. So just let them coexist and
don't worry about it.
llvm-svn: 199654
2014-01-20 12:02:53 +00:00
35da3d190a
Allow x86 mov instructions to/from memory with absolute address to be encoded and disassembled with a segment override prefix. Fixes PR16962.
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llvm-svn: 199364
2014-01-16 07:36:58 +00:00
b7c7f38918
Simplify x86 disassembler table handling of when to use TYPE_Rv/TYPE_R16/TYPE_R32 now that HasOpSizePrefix only means 16-bit instructions.
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llvm-svn: 199295
2014-01-15 05:02:02 +00:00
ad60708a72
Remove stray comma in enum to satisfy -Wpedantic.
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llvm-svn: 199194
2014-01-14 08:07:10 +00:00
ae11aed9d7
Separate the concept of 16-bit/32-bit operand size controlled by 0x66 prefix and the current mode from the concept of SSE instructions using 0x66 prefix as part of their encoding without being affected by the mode.
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This should allow SSE instructions to be encoded correctly in 16-bit mode which r198586 probably broke.
llvm-svn: 199193
2014-01-14 07:41:20 +00:00
32da3c8f3b
[x86] Fix MOV8ao8 et al for 16-bit mode, fix up disassembler to understand
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It seems there is no separate instruction class for having AdSize *and*
OpSize bits set, which is required in order to disambiguate between all
these instructions. So add that to the disassembler.
Hm, perhaps we do need an AdSize16 bit after all?
llvm-svn: 198759
2014-01-08 12:58:24 +00:00
2ea87dad77
The rest of r198588. Remove SegOvrBits from X86 TSFlags since they weren't being used.
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llvm-svn: 198589
2014-01-06 06:57:27 +00:00
d9e1669d1c
Use patterns to remove some duplicate instructions.
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llvm-svn: 198550
2014-01-05 06:55:48 +00:00
34db6523f3
Fix encoding for PUSH64i16. Add In64BitMode Predicate. Remove disassembler hack.
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llvm-svn: 198547
2014-01-05 05:46:38 +00:00
c0107977d9
Remove no longer needed x86 disassembler hack.
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llvm-svn: 198546
2014-01-05 05:10:07 +00:00
0550ce7ac1
Mark x86 _alt instructions as AsmParserOnly so they will be omitted from disassembler without string matches.
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llvm-svn: 198545
2014-01-05 04:55:55 +00:00
5165cf78b0
Use new ForceDisassemble flag on the 2-byte forms of INC/DEC for 32-bit mode and remove disassmbler table emitter hack.
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llvm-svn: 198544
2014-01-05 04:32:42 +00:00
3484fc2161
Add a new x86 specific instruction flag to force some isCodeGenOnly instructions to go through to the disassembler tables without resorting to string matches. Apply flag to all _REV instructions.
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llvm-svn: 198543
2014-01-05 04:17:28 +00:00
5999d47538
Mark the 64-bit x86 push/pop instructions as In64BitMode. Mark the corresponding 32-bit versions with the same encodings Not64BitMode. Remove hack from tablegen disassembler table emitter. Fix bad test.
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llvm-svn: 198530
2014-01-05 01:35:51 +00:00
bc281ad8c1
Tag x86 move to/from debug/control registers with Not64BitMode/In64BitMode. Remove disassembler hack.
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llvm-svn: 198515
2014-01-04 22:29:41 +00:00
1da8582322
Remove JMP64pcrel32 (jmpq ). There are no tests for it. I'm pretty sure it won't be emitted correctly since it was set to NoImm. And I can't prove that gas accepts 'jmpq' with an immediate either. Remove the special case for it from the disassembler table generator.
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llvm-svn: 198475
2014-01-04 05:09:27 +00:00
66c20f344e
Mark REX64_PREFIX as In64BitMode, remove hack from X86RecognizableInstr.
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llvm-svn: 198336
2014-01-02 19:12:10 +00:00
fae226c67e
Remove unused HasFROperands field from disassembler.
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llvm-svn: 198332
2014-01-02 18:44:21 +00:00
eabdbcb8a9
Mark PUSHFS64/PUSHGS64/POPFS64/POPGS64 as In64BitMode and remove the hack from the disassembler table builder.
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llvm-svn: 198327
2014-01-02 18:20:48 +00:00
a941d2b08e
Remove unnecessary stirng comparison from disassembler.
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llvm-svn: 198325
2014-01-02 17:41:40 +00:00
9dd48c8ed4
Mark all x86 Int_ and _Int patterns as isCodeGenOnly so the disassembler table builder doesn't need to string match them to exclude them.
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llvm-svn: 198323
2014-01-02 17:28:14 +00:00
83b7e24b76
Remove unused function argument.
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llvm-svn: 198291
2014-01-02 03:58:45 +00:00
3321c99a06
Remove modifierType/Base from X86 disassembler tables as they are no longer used. Removes ~11.5K from static tables.
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llvm-svn: 198284
2014-01-01 21:52:57 +00:00
Kevin Enderby