04c342ea20
replace stuff like:
...
let AsmString = !strconcat(
!strconcat(!strconcat(opc, "${p}"), !strconcat(".", dt)),
!strconcat("\t", asm));
with:
let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm);
:)
llvm-svn: 115720
2010-10-06 00:05:18 +00:00
b9f2d50d5f
Comment out fastisel debugging message.
...
llvm-svn: 115717
2010-10-05 23:50:58 +00:00
8cfc459274
Random cleanup and make the intermediate register in fptosi a
...
32-bit fp reg, not 64-bit.
Fixes SingleSource.
llvm-svn: 115711
2010-10-05 23:13:24 +00:00
e929899a3f
Increase the number of bits used internally by the ARM target to represent the
...
addressing mode from four to five.
llvm-svn: 115645
2010-10-05 18:14:55 +00:00
70ac5fa42c
fix MSVC 2010 build.
...
llvm-svn: 115594
2010-10-05 06:00:43 +00:00
e7f00cbb7c
Cleanup Whitespace.
...
llvm-svn: 115593
2010-10-05 06:00:33 +00:00
66e08d43d2
Jim Asked us to move DataLayout on ARM back to the most specialized classes. Do
...
so and also change X86 for consistency.
Investigating if this can be improved a bit.
llvm-svn: 115469
2010-10-03 18:59:45 +00:00
73eac2aadf
Major changes to Cortex-A9 itinerary.
...
1. Model dual issues as two FUs.
2. Model the pipelines correctly: two symmetric ALUs, the multiplier is a
dependent pipeline on ALU0.
The changes do not have much impact on codegen right now. But I plan to make
pre-RA scheduler multi-issue aware which should take good advantage of the
changes.
llvm-svn: 115457
2010-10-03 02:03:59 +00:00
7787f79f21
Start on lowering global addresses.
...
llvm-svn: 115390
2010-10-02 00:32:44 +00:00
ff1751c0a6
PrintSpecial() can go away now.
...
llvm-svn: 115376
2010-10-01 23:27:48 +00:00
83a5ec8fe0
Stub out constant GV handling, fixes C++ eh tests.
...
llvm-svn: 115375
2010-10-01 23:24:42 +00:00
fae8305e2b
Nuke the rest of the :comment references
...
llvm-svn: 115373
2010-10-01 23:21:38 +00:00
c13194254b
Nuke a bunch of no-longer-needed comment-only asm strings.
...
llvm-svn: 115370
2010-10-01 23:09:33 +00:00
a317815463
Fix r115332: correctly model AGU / NEON mux.
...
llvm-svn: 115365
2010-10-01 22:52:29 +00:00
f31f33ea89
Thread the determination of branch prediction hit rates back through the if-conversion heuristic APIs. For now,
...
stick with a constant estimate of 90% (branch predictors are good!), but we might find that we want to provide
more nuanced estimates in the future.
llvm-svn: 115364
2010-10-01 22:45:50 +00:00
0e854f3d43
Rename the AsmPrinter directory to InstPrinter for those targets that have
...
been MC-ized for assembly printing. MSP430 is mostly so, but still has the
asm printer and lowering code in the printer subdir for the moment.
llvm-svn: 115360
2010-10-01 22:39:28 +00:00
1969887fc6
Fix scheduling infor for vmovn and vshrn which I broke accidentially.
...
llvm-svn: 115354
2010-10-01 21:48:06 +00:00
f3179567de
Add operand cycles for vldr / vstr.
...
llvm-svn: 115353
2010-10-01 21:40:30 +00:00
9d0136274b
Direct calls only for arm fast isel for now.
...
llvm-svn: 115350
2010-10-01 21:33:12 +00:00
2a5d764858
NEON scheduling info fix. vmov reg, reg are single cycle instructions.
...
llvm-svn: 115344
2010-10-01 20:50:58 +00:00
6080da7a79
Fix thinko on store instructions. Fixes test_indvars failure.
...
llvm-svn: 115342
2010-10-01 20:46:04 +00:00
2ecba4a07e
Make the spelling of the flags for old-style if-conversion heuristics consistent between ARM and Thumb2.
...
llvm-svn: 115341
2010-10-01 20:33:47 +00:00
671d57865e
Provide an option to restore old-style if-conversion heuristics for Thumb2.
...
llvm-svn: 115339
2010-10-01 20:28:06 +00:00
89e6f6759f
Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly.
...
llvm-svn: 115332
2010-10-01 19:41:46 +00:00
05ed521a88
grammar
...
llvm-svn: 115314
2010-10-01 14:57:48 +00:00
c1e209d40e
Implement double return values in calls. Fixes
...
SingleSource/Regression/C/casts.c.
llvm-svn: 115246
2010-10-01 00:00:11 +00:00
b9b63ee031
Temporarily add a flag to make it easier to compare the new-style ARM if
...
conversion heuristics to the old-style ones.
llvm-svn: 115239
2010-09-30 23:48:38 +00:00
56094ff402
Movement and cleanup.
...
llvm-svn: 115225
2010-09-30 22:34:19 +00:00
78f8d4eaf0
Start of generalized call support for ARM fast isel.
...
llvm-svn: 115203
2010-09-30 20:49:44 +00:00
c8e2e9d830
Nuke a few more unused asm strings
...
llvm-svn: 115193
2010-09-30 19:53:58 +00:00
7e872969ce
Move getPointerSize() to the base class since it's not dependent on MachO
...
vs. ELF
llvm-svn: 115180
2010-09-30 17:45:51 +00:00
5a5ddc402e
Remove extraneous ';'
...
llvm-svn: 115176
2010-09-30 17:19:17 +00:00
b9429179f9
The asm strings are never used at all, so just nuke 'em entirely.
...
llvm-svn: 115160
2010-09-30 16:56:53 +00:00
bad267fa05
Adds getPointerSize() to the AsmBackend which will be needed by the final patch
...
for the dwarf .loc support to emit dwarf line number tables.
llvm-svn: 115153
2010-09-30 16:38:07 +00:00
136ed51b08
80 column fix
...
llvm-svn: 115149
2010-09-30 15:25:22 +00:00
6c233c141e
Fix two tiny issues (ARM does not need COFF) and comment sanity.
...
llvm-svn: 115147
2010-09-30 14:58:19 +00:00
689651c767
trailing whitespace
...
llvm-svn: 115136
2010-09-30 03:21:00 +00:00
58bce99385
Remove misplaced ';'. Make buildbots happy, hopefully.
...
llvm-svn: 115135
2010-09-30 03:20:34 +00:00
645f6c2bef
Tiny patch for proof-of-concept cleanup of ARMAsmPrinter::EmitStartOfAsmFile()
...
Small test for sanity check of resulting ARM .s file.
Tested against -r115129.
llvm-svn: 115133
2010-09-30 02:45:56 +00:00
4a9cb8f10e
Go ahead and jump!
...
Now that the MC lowering handles the expansion of the pseudos, kill the horrible
blobs of text.
llvm-svn: 115130
2010-09-30 02:18:06 +00:00
b32124545b
I added a new file ARMAsmBackend which stubs out in similar ways to
...
the eqv X86 class.
For now, I split the ELFARMAsmBackend from the DarwinARMAsmBackend
(also mimicking X86)
Tested against -r115126
llvm-svn: 115129
2010-09-30 02:17:26 +00:00
2ff7de0264
Now that the pseudos that needed this are all custom lowered, we can go back
...
to an empty PrintSpecial()
llvm-svn: 115128
2010-09-30 02:02:22 +00:00
080fdf4609
Nuke it from orbit. It's the only way to be sure.
...
(Kill the dead non-MC asm printer for the ARM target.)
llvm-svn: 115127
2010-09-30 01:57:53 +00:00
2fb20b1d37
ARM instruction itinerary fixes:
...
1. Cortex-a9 8-bit and 16-bit loads / stores AGU cycles are 1 cycle longer than 32-bit ones.
2. Cortex-a9 is out-of-order so model all read cycles as cycle 1.
3. Lots of other random fixes for A8 and A9.
llvm-svn: 115121
2010-09-30 01:08:25 +00:00
7939806ecc
Refactor arm fast isel libcall handling so that pieces can be used
...
for generic call handling.
llvm-svn: 115105
2010-09-29 23:11:09 +00:00
4a010fd1ea
Model Cortex-a9 load to SUB, RSB, ADD, ADC, SBC, RSC, CMN, MVN, or CMP
...
pipeline forwarding path.
llvm-svn: 115098
2010-09-29 22:42:35 +00:00
b024be3162
Add a convenience variable so I'm not chasing all over looking for
...
a context.
llvm-svn: 115094
2010-09-29 22:24:45 +00:00
0860520527
Add specializations of addrmode2 that allow differentiating those forms
...
which require the use of the shifter-operand. This will be used to split
the ldr/str instructions such that those versions needing the shifter operand
can get a different scheduling itenerary, as in some cases, the use of the
shifter can cause different scheduling than the simpler forms.
llvm-svn: 115066
2010-09-29 19:03:54 +00:00
97bf273870
Increase ARM APCS preferred alignment for i64 and f64 from 32 bits to 64 bits.
...
LDM/STM instructions can run one cycle faster on some ARM processors if the
memory address is 64-bit aligned. Radar 8489376.
llvm-svn: 115047
2010-09-29 17:54:10 +00:00
c7b10f3745
Add braces for legibility.
...
llvm-svn: 115043
2010-09-29 17:32:29 +00:00
05eccf0e44
One Printer to rule them all, One Printer to find them,
...
One Printer to lower them all and in the back end bind them.
(Remove option to use the old non-MC asm printer.)
llvm-svn: 115038
2010-09-29 15:23:40 +00:00
d36e3e8850
improve heuristics to find the 'and' corresponding to 'tst' to also catch opportunities on thumb2
...
added some doxygen on the way
llvm-svn: 115033
2010-09-29 10:12:08 +00:00
a63292a3ca
implement rdar://8456378 and PR7557 - support for the fstsw,
...
an instruction that requires a WHOLE NEW wonderful kind of alias.
llvm-svn: 115015
2010-09-29 01:50:45 +00:00
b44fd24fc1
change the protocol TargetAsmPArser::MatchInstruction method to take an
...
MCStreamer to emit into instead of an MCInst to fill in. This allows the
matcher extra flexibility and is more convenient.
llvm-svn: 115014
2010-09-29 01:42:58 +00:00
3a7e8cd6bd
Rework comparison handling to set a register on true/false. This avoids
...
problems with phi-nodes in blocks that have hard and not virtual registers.
Accordingly update branch handling to compensate.
llvm-svn: 115013
2010-09-29 01:14:47 +00:00
edd4b600f3
Remove unnecessary set ahead of time.
...
llvm-svn: 115011
2010-09-29 00:50:57 +00:00
2259d67a33
Separate itinerary classes for mvn from mov; for tst / teq from cmp / cmn.
...
llvm-svn: 115010
2010-09-29 00:49:25 +00:00
2c8e7f421c
Remove assert, add comment.
...
llvm-svn: 115009
2010-09-29 00:49:09 +00:00
c35d7bbe43
Assign bitwise binary instructions different itinerary classes from ALU instructions such as add / sub.
...
llvm-svn: 115008
2010-09-29 00:27:46 +00:00
0097dd0d5a
Add support to model pipeline bypass / forwarding.
...
llvm-svn: 115005
2010-09-28 23:50:49 +00:00
a86a6d2fed
32-bit constant ints only for now.
...
llvm-svn: 115001
2010-09-28 22:47:54 +00:00
b4b12535e8
Removed a bunch of unnecessary target_link_libraries.
...
llvm-svn: 114999
2010-09-28 22:39:14 +00:00
a3181e2d79
Add a subtarget hook for reporting the misprediction penalty. Use this to provide more precise
...
cost modeling for if-conversion. Now if only we had a way to estimate the misprediction probability.
Adjsut CodeGen/ARM/ifcvt10.ll. The pipeline on Cortex-A8 is long enough that it is still profitable
to predicate an ldm, but the shorter pipeline on Cortex-A9 makes it unprofitable.
llvm-svn: 114995
2010-09-28 21:57:50 +00:00
953b1afd5f
Integer materialization needed the same thinko change.
...
llvm-svn: 114994
2010-09-28 21:55:34 +00:00
7d483d352b
Resolve this GCC warning:
...
ARMTargetMachine.cpp:53: error: control reaches end of non-void function
llvm-svn: 114992
2010-09-28 21:40:26 +00:00
81bdc93bbb
User proper libcall names & condcodes while compiling for ARM EABI.
...
Patch by Evzen Muller!
llvm-svn: 114991
2010-09-28 21:39:26 +00:00
88af7d00fc
Part one of switching to using a more sane heuristic for determining if-conversion profitability.
...
Rather than having arbitrary cutoffs, actually try to cost model the conversion.
For now, the constants are tuned to more or less match our existing behavior, but these will be
changed to reflect realistic values as this work proceeds.
llvm-svn: 114973
2010-09-28 18:32:13 +00:00
45c83d496f
Factor out dbg_value comment printing and teach MC asm printing to use it.
...
This should make the arm-linux self-host buildbot happy again.
llvm-svn: 114964
2010-09-28 17:05:56 +00:00
3da4255d07
Add ARM Disassembler to the CMake build.
...
llvm-svn: 114949
2010-09-28 11:48:19 +00:00
bf86fd3c47
80-col fixups.
...
llvm-svn: 114943
2010-09-28 04:18:29 +00:00
3dc97324c1
Add a command line option "-arm-strict-align" to disallow unaligned memory
...
accesses for ARM targets that would otherwise allow it. Radar 8465431.
llvm-svn: 114941
2010-09-28 04:09:35 +00:00
7990df1ae2
Rework builtin handling and call setup. The builtin handling
...
now takes a libcall operand, sets up the arguments correctly and
handles stack adjustments.
llvm-svn: 114934
2010-09-28 01:21:42 +00:00
e68635acdb
Fix typo.
...
llvm-svn: 114931
2010-09-28 00:35:33 +00:00
6f98bfd870
Fix fp constant loads to have a destination register.
...
llvm-svn: 114930
2010-09-28 00:35:09 +00:00
175d6411c8
Enable the MC-ized ARM asm printer. Passing all local tests, so it's time to
...
enable it for real. Leaving the CL option in place to it's easy to disable it
again if (when) testers find something I've missed.
llvm-svn: 114915
2010-09-27 22:28:11 +00:00
9e9ed98305
ARM-mode eh.sjlj.longjmp MC lowering
...
llvm-svn: 114896
2010-09-27 21:47:04 +00:00
11fed543c9
Enable the MC-ized ARM asm printer. Passing all local tests, so it's time to
...
enable it for real. Leaving the CL option in place to it's easy to disable it
again if (when) testers find something I've missed.
llvm-svn: 114892
2010-09-27 21:28:44 +00:00
6b2aaf1a36
Hard to imagine there are still people using inferior compilers.
...
llvm-svn: 114862
2010-09-27 20:12:58 +00:00
69aa15155f
Odd additional stub framework for the ARM MC ELF emission.
...
llc now recognizes the "intent" to support MC/obj emission for ARM, but
given that they are all stubs, it asserts on --filetype=obj --march=arm
Patch by Jason Kim.
llvm-svn: 114856
2010-09-27 18:31:37 +00:00
0720611e3a
Insert missing coherency in comment. Add a quick check for hardware
...
divide support also.
llvm-svn: 114813
2010-09-27 06:08:12 +00:00
29ab6d1f82
Mass rename for Jim.
...
llvm-svn: 114812
2010-09-27 06:02:23 +00:00
48cc21620f
Fix IIC_iEXTAr itinerary class of Cortex-A9.
...
llvm-svn: 114784
2010-09-25 01:09:28 +00:00
8f9a2244fc
Remove a unused instruction itinerary class.
...
llvm-svn: 114782
2010-09-25 01:06:02 +00:00
62d626ce86
Fix zero and sign extension instructions scheduling itineraries.
...
llvm-svn: 114780
2010-09-25 00:49:35 +00:00
e37da03e60
More pseudo instruction scheduling itinerary fixes.
...
llvm-svn: 114768
2010-09-24 22:41:41 +00:00
1d35ad62cc
Fix scheduling itinerary for pseudo mov immediate instructions which expand into two real instructions.
...
llvm-svn: 114766
2010-09-24 22:03:46 +00:00
4a6ab13fb9
Add ARM explicit MCInst lowering for the Thumb eh.sjlj.setjmp sequence.
...
llvm-svn: 114758
2010-09-24 20:47:58 +00:00
dbcc4b4d4d
Enable code placement optimization pass for ARM.
...
llvm-svn: 114746
2010-09-24 19:07:23 +00:00
40a4222996
Fix a potential null dereference bug.
...
llvm-svn: 114723
2010-09-24 05:18:35 +00:00
2c5df619c4
Revert r114703 and r114702, removing the isConditionalMove flag from instructions. After further
...
reflection, this isn't going to achieve the purpose I intended it for. Back to the drawing board!
llvm-svn: 114710
2010-09-23 23:45:25 +00:00
7fbbe9a43a
Set alignment operand for NEON VST instructions.
...
llvm-svn: 114709
2010-09-23 23:42:37 +00:00
c0aed7179a
ARM-mode eh.sjlj.setjmp pseudo MC-inst lowering expansion
...
llvm-svn: 114707
2010-09-23 23:33:56 +00:00
2f3728f576
#+4 --> #4 for consistency with other asm output
...
llvm-svn: 114706
2010-09-23 23:32:38 +00:00
07f07290d8
Fix formatting of output .s code
...
llvm-svn: 114705
2010-09-23 23:03:26 +00:00
bd57e0ce3d
Add isConditionalMove bits to X86 and ARM instructions.
...
llvm-svn: 114703
2010-09-23 22:57:01 +00:00
9eeb890172
Set alignment operand for NEON VLD instructions.
...
llvm-svn: 114696
2010-09-23 21:43:54 +00:00
7d34837676
never mind. I can't read, apparently
...
llvm-svn: 114689
2010-09-23 19:42:17 +00:00
1596f7f6f3
Fix r114632. Return if the only terminator is an unconditional branch after the redundant ones are deleted.
...
llvm-svn: 114688
2010-09-23 19:42:03 +00:00
836341a17a
Fix opcode value for the 'trap' instruction, keeping the type suffix on the
...
constant. Hopefully the non-Darwin bots will like it...
llvm-svn: 114687
2010-09-23 19:32:40 +00:00
3d50a3e237
explicit 'unsigned long' on constant value. Hopefully make bots happier.
...
llvm-svn: 114686
2010-09-23 19:08:04 +00:00
e38495dbc0
Unbreak build. Jim, please review.
...
llvm-svn: 114684
2010-09-23 18:57:26 +00:00
8503054410
Clean up the 'trap' instruction printing a bit. Non-Darwin assemblers don't
...
(yet) recognize the 'trap' mnemonic, so we use .short/.long to emit the
opcode directly. On Darwin, however, we do want the mnemonic for more
readable assembly code and better disassembly.
Adjust the .td file to use the 'trap' mnemonic and handle using the binutils
workaround in the assembly printer. Also tweak the formatting of the opcode
values to make them consistent between the MC printer and the old printer.
llvm-svn: 114679
2010-09-23 18:05:37 +00:00
ea20e257b2
nuke unused var
...
llvm-svn: 114676
2010-09-23 17:58:00 +00:00
66c8cd2b32
If there are multiple unconditional branches terminating a block, eliminate all
...
but the first one. Those will never be executed. There was logic to do this
but it was faulty.
llvm-svn: 114632
2010-09-23 06:54:40 +00:00
85dcd3d0f4
Add support for ELF PLT references for ARM MC asm printing. Adding a
...
new VariantKind to the MCSymbolExpr seems like overkill, but I'm not sure
there's a more straightforward way to get the printing difference captured.
(i.e., x86 uses @PLT, ARM uses (PLT)).
llvm-svn: 114613
2010-09-22 23:27:36 +00:00
a9424d4f2f
Enable a few additional asserts in MC instruction lowering.
...
llvm-svn: 114601
2010-09-22 23:01:28 +00:00
463a05342a
Change VDUPLANE DAG combiner to just return the result instead of calling
...
CombineTo to avoid putting the result on the worklist. I don't think it makes
much difference for now, but it might help someday as we add more DAG
combine optimizations.
llvm-svn: 114595
2010-09-22 22:27:30 +00:00
2280674fa9
Combine both VMOVDRR(VMOVRRD) and VMOVRRD(VMOVDRR), instead of just doing one
...
of those. Refactor to share code for handling BUILD_VECTOR(VMOVRRD).
I don't have a testcase that exercises this, but it seems like an obvious
good thing to do.
llvm-svn: 114589
2010-09-22 22:09:21 +00:00
1f57cc4a59
add FIXME
...
llvm-svn: 114578
2010-09-22 20:55:15 +00:00
003fd5b65e
Remove a few commented out bits
...
llvm-svn: 114576
2010-09-22 20:32:34 +00:00
e12c8ba05b
Add PrintSpecial() handling for in ARM MC instruction printer.
...
llvm-svn: 114563
2010-09-22 18:37:14 +00:00
284eebc1ae
Add MC instruction printer support for ARM and Thumb1 jump tables.
...
llvm-svn: 114555
2010-09-22 17:39:48 +00:00
1573b29ea7
Add MC instruction printer support for TB[BH] style thumb2 jump tables.
...
llvm-svn: 114553
2010-09-22 17:15:35 +00:00
754e1efffc
Clean up comment.
...
llvm-svn: 114550
2010-09-22 16:45:13 +00:00
d757c88bba
OptimizeCompareInstr should avoid iterating pass the beginning of the MBB when the 'and' instruction is after the comparison.
...
llvm-svn: 114506
2010-09-21 23:49:07 +00:00
d64f9b8381
Add start of support for MC instruction printer of ARM jump tables. Filling in
...
the rest of it is next up.
llvm-svn: 114500
2010-09-21 23:28:16 +00:00
61158f98ab
Enable target-specific mul-lowering on ARM, even at -Os. Remove a test that this makes
...
irrelevant, but add a new test for the new, improved functionality.
llvm-svn: 114494
2010-09-21 22:51:46 +00:00
0e023ea02a
fix a long standing wart: all the ComplexPattern's were being
...
passed the root of the match, even though only a few patterns
actually needed this (one in X86, several in ARM [which should
be refactored anyway], and some in CellSPU that I don't feel
like detangling). Instead of requiring all ComplexPatterns to
take the dead root, have targets opt into getting the root by
putting SDNPWantRoot on the ComplexPattern.
llvm-svn: 114471
2010-09-21 20:31:19 +00:00
886250c8f0
convert a couple more places to use the new getStore()
...
llvm-svn: 114463
2010-09-21 18:51:21 +00:00
5549d496dd
Define the TargetLowering::getTgtMemIntrinsic hook for ARM so that NEON load
...
and store intrinsics are represented with MemIntrinsicSDNodes.
llvm-svn: 114454
2010-09-21 17:56:22 +00:00
cbac342e1a
Fix errant printing of [v]ldm instructions that aren't a pop
...
llvm-svn: 114445
2010-09-21 16:45:31 +00:00
1a25ae88ff
Fix buglet when the TST instruction directly uses the AND result.
...
I am unable to write a test for this case, help is solicited, though...
What I did is to tickle the code in the debugger and verify that we do the right thing.
llvm-svn: 114430
2010-09-21 13:30:57 +00:00
adbbb93d3d
Move the search for the appropriate AND instruction
...
into OptimizeCompareInstr.
This necessitates the passing of CmpValue around,
so widen the virtual functions to accomodate.
No functionality changes.
llvm-svn: 114428
2010-09-21 12:01:15 +00:00
7727d05dbb
convert the targets off the non-MachinePointerInfo of getLoad.
...
llvm-svn: 114410
2010-09-21 06:44:06 +00:00
2510de2bea
reimplement memcpy/memmove/memset lowering to use MachinePointerInfo
...
instead of srcvalue/offset pairs. This corrects SV info for mem
operations whose size is > 32-bits.
llvm-svn: 114401
2010-09-21 05:40:29 +00:00
e3d864b857
convert targets to the new MF.getMachineMemOperand interface.
...
llvm-svn: 114391
2010-09-21 04:39:43 +00:00
94dfd6fc4f
Simplify ARM callee-saved register handling by removing the distinction
...
between the high and low registers for prologue/epilogue code. This was
a Darwin-only thing that wasn't providing a realistic benefit anymore.
Combining the save areas simplifies the compiler code and results in better
ARM/Thumb2 codegen.
For example, previously we would generate code like:
push {r4, r5, r6, r7, lr}
add r7, sp, #12
stmdb sp!, {r8, r10, r11}
With this change, we combine the register saves and generate:
push {r4, r5, r6, r7, r8, r10, r11, lr}
add r7, sp, #12
rdar://8445635
llvm-svn: 114340
2010-09-20 19:32:20 +00:00
abf60e3421
Fix build.
...
llvm-svn: 114292
2010-09-18 17:54:37 +00:00
a6ba082cb6
Thumb opcodes for thumb calls.
...
llvm-svn: 114263
2010-09-18 02:32:38 +00:00
aef6499bf1
Add addrmode5 fp load support. Swap float/thumb operand adding to handle
...
thumb with floating point.
llvm-svn: 114256
2010-09-18 01:59:37 +00:00
30f2300ed2
Floating point stores have a 3rd addressing mode type.
...
llvm-svn: 114254
2010-09-18 01:23:38 +00:00
af5d63583e
factor out a simple helper function to create a label for PC-relative
...
instructions (PICADD, PICLDR, et.al.)
llvm-svn: 114243
2010-09-18 00:05:05 +00:00
8a5a6a6c1e
PC-relative pseudo instructions are lowered and printed directly. Any encounter
...
with one in the generic printing code is an error.
llvm-svn: 114242
2010-09-18 00:04:53 +00:00
de636ca9a8
Fix vmov.f64 disassembly on targets where sizeof(long) != 8.
...
llvm-svn: 114240
2010-09-17 23:48:07 +00:00
3d97920829
Add MC-inst handling for tPICADD
...
llvm-svn: 114237
2010-09-17 23:41:53 +00:00
cb6db98897
Add target-specific DAG combiner for BUILD_VECTOR and VMOVRRD. An i64
...
value should be in GPRs when it's going to be used as a scalar, and we use
VMOVRRD to make that happen, but if the value is converted back to a vector
we need to fold to a simple bit_convert. Radar 8407927.
llvm-svn: 114233
2010-09-17 22:59:05 +00:00
7a6c37d3e7
Teach the (non-MC) instruction printer to use the cannonical names for push/pop,
...
and shift instructions on ARM. Update the tests to match.
llvm-svn: 114230
2010-09-17 22:36:38 +00:00
2ccc1aa696
Rework arm fast isel branch and compare code.
...
llvm-svn: 114226
2010-09-17 22:28:18 +00:00
132a0ce787
Hook up verbose asm comment printing for SOImm operands in MC printer
...
llvm-svn: 114215
2010-09-17 21:33:25 +00:00
4e51d0bebb
trailing whitespace
...
llvm-svn: 114212
2010-09-17 21:25:10 +00:00
1287f4f3b8
Add skeleton infrastructure for the ARMMCCodeEmitter class. Patch by Jason Kim!
...
llvm-svn: 114195
2010-09-17 18:46:17 +00:00
0d35df1cfe
handle the upper16/lower16 target operand flags on symbol references for MC
...
instruction lowering.
llvm-svn: 114191
2010-09-17 18:25:25 +00:00
a7d430b51c
expand PICLDR MC lowering to handle other PICLDR and PICSTR versions.
...
llvm-svn: 114183
2010-09-17 16:25:52 +00:00
218e22da8b
MC-ization of the PICLDR pseudo. Next up, adding the other variants
...
(PICLDRB, et. al.) and PICSTR*
llvm-svn: 114098
2010-09-16 17:43:25 +00:00
ee1934a2da
Make sure to promote single precision floats to double before extracting them
...
from the APFloat.
llvm-svn: 114096
2010-09-16 17:37:30 +00:00
a625b0110b
Remove support for "dregpair" operand modifier, now that it is no longer being
...
used for anything.
llvm-svn: 114067
2010-09-16 04:55:00 +00:00
450c6cfaff
When expanding ARM pseudo registers, copy the existing predicate operands
...
instead of using default predicates on the expanded instructions.
llvm-svn: 114066
2010-09-16 04:25:37 +00:00
298d0fd1c8
store MC FP immediates as a double instead of as an APFloat, thus avoiding an
...
unnecessary dtor for MCOperand.
llvm-svn: 114064
2010-09-16 03:45:21 +00:00
62c454847d
Add missing break.
...
llvm-svn: 114048
2010-09-16 00:31:32 +00:00
6b853c3ce3
Change VLDMQ and VSTMQ to be pseudo instructions. They are expanded after
...
register allocation to VLDMD and VSTMD respectively. This avoids using the
dregpair operand modifier.
llvm-svn: 114047
2010-09-16 00:31:02 +00:00
cb54b960b8
Add support for the 'lane' modifier on vdup operands
...
llvm-svn: 114030
2010-09-15 22:13:23 +00:00
44857a38fa
Remember VLDMQ.
...
llvm-svn: 114026
2010-09-15 21:40:11 +00:00
b929c7173d
Add missing break.
...
llvm-svn: 114025
2010-09-15 21:40:09 +00:00
27ab5fbd2b
Teach the MC disassembler to handle vmov.f32 and vmov.f64 immediate to register
...
moves. Previously, the immediate was printed as the encoded integer value,
which is incorrect.
llvm-svn: 114021
2010-09-15 21:04:54 +00:00
40e85fbf17
move getRegisterNumbering() to out of ARMBaseRegisterInfo into the helper
...
functions in ARMBaseInfo.h so it can be used in the MC library as well.
For anything bigger than this, we may want a means to have a small support
library for shared helper functions like this. Cross that bridge when we
come to it.
llvm-svn: 114016
2010-09-15 20:26:25 +00:00
9569567255
simplify getRegisterNumbering(). Remove the unused isSPVFP argument and
...
merge the common cases.
llvm-svn: 114013
2010-09-15 19:52:17 +00:00
789ca9a1e9
Refactor uses of getRegisterNumbering() to not need the isSPVFP argument. Check
...
if the register is a member of the SPR register class directly instead.
llvm-svn: 114012
2010-09-15 19:44:57 +00:00
29fe94e75e
Reduce dependencies in the ARM MC instruction printer.
...
llvm-svn: 114009
2010-09-15 19:27:50 +00:00
2b48b5557a
Fix spelling typo.
...
llvm-svn: 114008
2010-09-15 19:26:50 +00:00
91fbd8f86e
Factor out basic enums and hleper functions from ARM.h for cleaner sharing
...
between the compiler back end and the MC libraries.
llvm-svn: 114007
2010-09-15 19:26:06 +00:00
7bbf3fd0d6
Add support for floating point immediates to MC instruction printing. ARM
...
VFP instructions use it for loading some constants, so implement that
handling.
Not thrilled with adding a member to MCOperand, but not sure there's much of
a better option that's not pretty fragile (like putting a double in the
union instead and just assuming that's good enough). Suggestions welcome...
llvm-svn: 113996
2010-09-15 18:47:08 +00:00
33005d1327
Recognize VST1q64Pseudo and VSTMQ as stack slot stores.
...
Recognize VLD1q64Pseudo as a stack slot load.
Reject these if they are loading or storing a subregister. The API (and
VirtRegRewriter) doesn't know how to deal with that.
llvm-svn: 113985
2010-09-15 17:27:09 +00:00
660d7ecf32
Reapply Gabor's 113839, 113840, and 113876 with a fix for a problem
...
encountered while building llvm-gcc for arm. This is probably the same issue
that the ppc buildbot hit. llvm::prior works on a MachineBasicBlock::iterator,
not a plain MachineInstr.
llvm-svn: 113983
2010-09-15 17:12:08 +00:00
9ae4b271f2
the darwin9-powerpc buildbot keeps consistently crashing,
...
backing out following to get it back to green,
so I can investigate in peace:
svn merge -c -113840 llvm/test/CodeGen/ARM/arm-and-tst-peephole.ll
svn merge -c -113876 -c -113839 llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
llvm-svn: 113980
2010-09-15 16:53:07 +00:00
11f5be3b86
Move ARM is{LoadFrom,StoreTo}StackSlot closer to their siblings so they won't be
...
forgotten in the future.
Coalesce identical cases in switch.
No functional changes intended.
llvm-svn: 113979
2010-09-15 16:36:26 +00:00
2c00b5098a
Spelling fix.
...
llvm-svn: 113978
2010-09-15 16:28:21 +00:00
b1e9d4bff1
Use VLD1/VST1 pseudo instructions for loadRegFromStackSlot and
...
storeRegToStackSlot.
llvm-svn: 113918
2010-09-15 01:48:05 +00:00
c7cf42d80b
Reapply r113875 with additional cleanups.
...
"The register specified for a dregpair is the corresponding Q register, so to
get the pair, we need to look up the sub-regs based on the qreg. Create a
lookup function since we don't have access to TargetRegisterInfo here to
be able to use getSubReg(ARM::dsub_[01])."
Additionaly, fix the NEON VLD1* and VST1* instruction patterns not to use
the dregpair modifier for the 2xdreg versions. Explicitly specifying the two
registers as operands is more correct and more consistent with the other
instruction patterns. This enables further cleanup of special case code in the
disassembler as a nice side-effect.
llvm-svn: 113903
2010-09-14 23:54:06 +00:00
8b9126694d
Emit libcalls for SDIV, this requires some call infrastructure
...
that needs to be shared a bit more widely around.
llvm-svn: 113886
2010-09-14 23:03:37 +00:00
c07b2afe5e
revert 113875 momentarilly. Need to fix the MC disassembler to handle the
...
change.
llvm-svn: 113878
2010-09-14 22:38:39 +00:00
29cad6c2fc
trailing whitespace cleanup
...
llvm-svn: 113877
2010-09-14 22:27:15 +00:00
b54e9387ab
an attempt to salvage the darwin9-powerpc buildbot, which could be miscompiling this line
...
llvm-svn: 113876
2010-09-14 22:25:16 +00:00
b523be2bb3
The register specified for a dregpair is the corresponding Q register, so to
...
get the pair, we need to look up the sub-regs based on the qreg. Create a
lookup function since we don't have access to TargetRegisterInfo here to
be able to use getSubReg(ARM::dsub_[01]).
llvm-svn: 113875
2010-09-14 22:20:33 +00:00
22f6922505
set isCompare for another three Thumb1 instructions
...
llvm-svn: 113867
2010-09-14 22:00:50 +00:00
a244f70113
Add predicate and 's' bit operands to PICADD instruction lowering.
...
llvm-svn: 113860
2010-09-14 21:28:17 +00:00
62e9a052b9
Avoid warnings.
...
llvm-svn: 113857
2010-09-14 21:12:05 +00:00
7ae94222cd
fix comment typo
...
llvm-svn: 113856
2010-09-14 21:05:34 +00:00
dd29db5635
Make NEON ld/st pseudo instruction classes take the instruction itinerary as
...
an argument, so that we can distinguish instructions with the same register
classes but different numbers of registers (e.g., vld3 and vld4). Fix some
of the non-pseudo NEON ld/st instruction itineraries to reflect the number
of registers loaded or stored, not just the opcode name.
llvm-svn: 113854
2010-09-14 20:59:49 +00:00
2afac8e9bd
set comparable for a bunch of Thumb instructions
...
llvm-svn: 113849
2010-09-14 20:47:43 +00:00
cf98cbaef1
Don't ignore the CPSR implicit def when lowering a MachineInstruction to an MCInst.
...
llvm-svn: 113847
2010-09-14 20:41:27 +00:00
bc7eeaf233
Clarify comment
...
llvm-svn: 113846
2010-09-14 20:35:46 +00:00
d0cef1e2ef
Eliminate a 'tst' that immediately follows an 'and'
...
by morphing the 'and' to its recording form 'andS'.
This is basically a test commit into this area, to
see whether the bots like me. Several generalizations
can be applied and various avenues of code simplification
are open. I'll introduce those as I go.
I am aware of stylistic input from Bill Wendling, about
where put the analysis complexity, but I am positive
that we can move things around easily and will find a
satisfactory solution.
llvm-svn: 113839
2010-09-14 09:23:22 +00:00
726838a3e5
Fix QOpcode assignment to Opc.
...
llvm-svn: 113837
2010-09-14 08:31:25 +00:00
93c9b2ea93
Revert "CMake: Get rid of LLVMLibDeps.cmake and export the libraries normally."
...
This reverts commit r113632
Conflicts:
cmake/modules/AddLLVM.cmake
llvm-svn: 113819
2010-09-13 23:59:48 +00:00
c597fd3b4a
Convert some VTBL and VTBX instructions to use pseudo instructions prior to
...
register allocation. Remove the NEONPreAllocPass, which is no longer needed.
Yeah!!
llvm-svn: 113818
2010-09-13 23:55:10 +00:00
d5c57a5ed4
Switch all the NEON vld-lane and vst-lane instructions over to the new
...
pseudo-instruction approach. Change ARMExpandPseudoInsts to use a table
to record all the NEON load/store information.
llvm-svn: 113812
2010-09-13 23:01:35 +00:00
7aeff13cae
trailing whitespace
...
llvm-svn: 113768
2010-09-13 18:25:42 +00:00
a2a9d16b78
fix the asmparser so that the target is responsible for skipping to
...
the end of the line on a parser error, allowing skipping to happen
for syntactic errors but not for semantic errors. Before we would
miss emitting a diagnostic about the second line, because we skipped
it due to the semantic error on the first line:
foo %eax
bar %al
This fixes rdar://8414033 - llvm-mc ignores lines after an invalid instruction mnemonic errors
llvm-svn: 113688
2010-09-11 16:18:25 +00:00
27dddd1fd1
Rename ConvertToSetZeroFlag to something more general.
...
llvm-svn: 113670
2010-09-11 00:13:50 +00:00
d0a5f4e238
No need to recompute the SrcReg and CmpValue.
...
llvm-svn: 113666
2010-09-10 23:46:12 +00:00
041230014c
Move some of the decision logic for converting an instruction into one that sets
...
the 'zero' bit down into the back-end. There are other cases where this logic
isn't sufficient, so they should be handled separately.
llvm-svn: 113665
2010-09-10 23:34:19 +00:00
72497e5d90
Start sketching out ARM fast-isel calls.
...
llvm-svn: 113662
2010-09-10 23:18:12 +00:00
cc766a20d3
For consistency.
...
llvm-svn: 113659
2010-09-10 23:10:30 +00:00
cc1367851b
Newline at end of file.
...
llvm-svn: 113654
2010-09-10 22:46:03 +00:00
1c06917f15
Split out some of the calling convention bits so that they can be
...
used for fast-isel.
llvm-svn: 113652
2010-09-10 22:42:06 +00:00
aee679bf35
Modify the comparison optimizations in the peephole optimizer to update the
...
iterator when an optimization took place. This allows us to do more insane
things with the code than just remove an instruction or two.
llvm-svn: 113640
2010-09-10 21:55:43 +00:00
1f77ee5691
Add a missing case to duplicateCPV() for LSDA constants. Add a FIXME. rdar://8302157
...
llvm-svn: 113637
2010-09-10 21:38:22 +00:00
dc38d36ccb
CMake: Get rid of LLVMLibDeps.cmake and export the libraries normally.
...
llvm-svn: 113632
2010-09-10 21:14:25 +00:00
ed19768cec
Calculate the number of VLDM/VSTM registers by subtracting the number of
...
fixed operands from the total number of operands (including the variadic ones).
llvm-svn: 113597
2010-09-10 18:25:35 +00:00
ac0ad0f634
Reword since this may not be a bug but intended behavior.
...
llvm-svn: 113584
2010-09-10 10:31:11 +00:00
8617234658
Fix merging base-updates for VLDM/VSTM: Before I switched these instructions
...
to use AddrMode4, there was a count of the registers stored in one of the
operands. I changed that to just count the operands but forgot to adjust for
the size of D registers. This was noticed by Evan as a performance problem
but it is a potential correctness bug as well, since it is possible that this
could merge a base update with a non-matching immediate.
llvm-svn: 113576
2010-09-10 05:15:04 +00:00
bf4070756f
Teach if-converter to be more careful with predicating instructions that would
...
take multiple cycles to decode.
For the current if-converter clients (actually only ARM), the instructions that
are predicated on false are not nops. They would still take machine cycles to
decode. Micro-coded instructions such as LDM / STM can potentially take multiple
cycles to decode. If-converter should take treat them as non-micro-coded
simple instructions.
llvm-svn: 113570
2010-09-10 01:29:16 +00:00
712bd0a604
Fix build error.
...
llvm-svn: 113566
2010-09-10 00:35:09 +00:00
860fc9370f
Update comments, reorganize some code, rename variables to be
...
more clear. No functional change.
llvm-svn: 113565
2010-09-10 00:34:35 +00:00
22fd29a94a
64-bit fp loads can come straight out of the constant pool, not as
...
bad as I'd thought.
llvm-svn: 113561
2010-09-09 23:50:00 +00:00
4bd7047324
SIToFP and FPToSI conversions work only on fp-reg to fp-reg. Move
...
some data around and implement a couple of move routines to do this.
llvm-svn: 113546
2010-09-09 21:44:45 +00:00
2cbe0fd956
New "move to fp reg" routine. Use it.
...
llvm-svn: 113537
2010-09-09 20:49:25 +00:00
82b05d7206
"Strike that, reverse it." -- Mr. Wonka.
...
Truncate when truncating, extend when extending.
llvm-svn: 113536
2010-09-09 20:36:19 +00:00
5903c0be2a
Add FPTrunc, fix some bugs where I forgot to update the value map.
...
llvm-svn: 113533
2010-09-09 20:26:31 +00:00
6e3eeba4d9
Basic FP->Int, Int->FP conversions.
...
llvm-svn: 113523
2010-09-09 18:54:59 +00:00
367a5df8cf
For each instruction itinerary class, specify the number of micro-ops each
...
instruction in the class would be decoded to. Or zero if the number of
uOPs must be determined dynamically.
This will be used to determine the cost-effectiveness of predicating a
micro-coded instruction.
llvm-svn: 113513
2010-09-09 18:18:55 +00:00
4adbaf1843
Fix NEON VLD pseudo instruction itineraries that were incorrectly copied from
...
the VST pseudos. The VLD/VST scheduling still needs work (see pr6722), but
at least we shouldn't confuse the loads with the stores.
llvm-svn: 113473
2010-09-09 05:40:26 +00:00
2ff757d422
Nuke whitespace and fix some indenting.
...
llvm-svn: 113463
2010-09-09 01:06:51 +00:00
bd3d121641
Handle 64-bit floating point binops as well.
...
llvm-svn: 113461
2010-09-09 01:02:03 +00:00
24dc27f73a
Basic 32-bit FP operations.
...
llvm-svn: 113459
2010-09-09 00:53:57 +00:00
84971c850a
For double-spaced VLD3/VLD4 instructions, copy the explicit super-register use
...
operand from the pseudo instruction to the new instruction as an implicit use.
This will preserve any other flags (e.g., kill) on the operand.
llvm-svn: 113456
2010-09-09 00:38:32 +00:00
f14b9bf98d
Handle float->double extension.
...
llvm-svn: 113455
2010-09-09 00:26:48 +00:00
3cf63f1edd
Rewrite TargetMaterializeConstant splitting it out into two functions
...
for integer and fp constants. Implement todo to use vfp3 instructions
to materialize easy constants if we can.
llvm-svn: 113453
2010-09-09 00:19:41 +00:00
4ccd5ce6ea
Simplify copying over operands from pseudo NEON load/store instructions.
...
For VLD3/VLD4 with double-spaced registers, add the implicit use of the
super register for both the instruction loading the even registers and the
instruction loading the odd registers.
llvm-svn: 113452
2010-09-09 00:15:32 +00:00
359f8ba337
Clean up a comment.
...
llvm-svn: 113442
2010-09-08 23:39:54 +00:00
c3e9c404aa
Very basic compare support.
...
llvm-svn: 113440
2010-09-08 23:13:45 +00:00
5838af54bf
Delete dead code.
...
llvm-svn: 113436
2010-09-08 22:58:35 +00:00
722cd122dc
Fix LDM_RET schedule itinery.
...
llvm-svn: 113435
2010-09-08 22:57:08 +00:00
6489df7c8c
Make the loads/stores match the type we really want to store.
...
llvm-svn: 113417
2010-09-08 21:49:50 +00:00
504d23bd05
Re-enable usage of the ARM base pointer. r113394 fixed the known failures.
...
Re-running some nightly testers w/ it enabled to verify.
llvm-svn: 113399
2010-09-08 20:12:02 +00:00
21c9471706
Fix errant fall-throughs causing the base pointer to be used when the frame
...
pointer was intended. rdar://8401980
llvm-svn: 113394
2010-09-08 19:55:28 +00:00
f5dd1929a2
Rewrite TargetMaterializeConstant.
...
llvm-svn: 113387
2010-09-08 18:56:34 +00:00
7dfca6fb51
Be more careful about when to do dynamic stack realignment. Since we have an
...
option to disable base pointer usage, pay attention to it when deciding
if we can realign (if no base pointer and VLAs, we can't).
llvm-svn: 113366
2010-09-08 17:22:12 +00:00
53aa5e31e1
Add missing assert
...
llvm-svn: 113365
2010-09-08 17:05:45 +00:00
91689c1d0f
change the MC "ParseInstruction" interface to make it the
...
implementation's job to check for and lex the EndOfStatement
marker.
llvm-svn: 113347
2010-09-08 05:10:46 +00:00
7a23aa081a
ARM/Disassembler: Fix definitions incompatible(unsigned and uint32_t) to Cygwin-1.5, following up to r113255.
...
llvm-svn: 113345
2010-09-08 04:48:17 +00:00
535d3b4e09
remove trailing whitespace
...
llvm-svn: 113338
2010-09-08 03:54:02 +00:00
19cb2f4c67
remove obsolete comment
...
llvm-svn: 113337
2010-09-08 03:51:44 +00:00
261df12f64
disable for the moment while tracking down a few Thumb2-O0 failure that look
...
related. (attempt deux, complete w/ test update this time)
llvm-svn: 113333
2010-09-08 02:00:34 +00:00
b2c950187e
woops. need to update a test along with this.
...
llvm-svn: 113332
2010-09-08 01:49:09 +00:00
7cda56ea6a
disable temporarily while sorting out a few test failures in Thumb2-O0 tests.
...
llvm-svn: 113331
2010-09-08 01:47:49 +00:00
136d035e45
correct spill code to properly determine if dynamic stack realignment is
...
present in the function and thus whether aligned load/store instructions can
be used.
llvm-svn: 113323
2010-09-08 00:26:59 +00:00
abcbe2474d
VFP/NEON load/store multiple instructions are addrmode4, not 5.
...
llvm-svn: 113322
2010-09-08 00:25:50 +00:00
88628e9738
To shrink a t2LDM instruction to the 16-bit wide tLDM instruction, the base
...
register must be one of the destination registers for the load. Otherwise,
the tLDM instruction will write-back to the base register, which isn't what's
desired (otherwise, we'd have a t2LDM_UPD instead).
rdar://8394087
llvm-svn: 113297
2010-09-07 22:30:53 +00:00
9877af3b46
grammar tweak
...
llvm-svn: 113289
2010-09-07 21:30:25 +00:00
091012d5d5
hopefully fix a problem building on cygwin-1.5
...
llvm-svn: 113255
2010-09-07 19:50:53 +00:00
339cc7bfef
in the case where an instruction only has one implementation
...
of a mneumonic, report operand errors with better location
info. For example, we now report:
t.s:6:14: error: invalid operand for instruction
cwtl $1
^
but we fail for common cases like:
t.s:11:4: error: invalid operand for instruction
addl $1, $1
^
because we don't know if this is supposed to be the reg/imm or imm/reg
form.
llvm-svn: 113178
2010-09-06 22:11:18 +00:00
a22a368e7c
change MatchInstructionImpl to return an enum instead of bool.
...
llvm-svn: 113165
2010-09-06 19:22:17 +00:00
3e4582ada5
have AsmMatcherEmitter.cpp produce the hunk of code that gets included
...
into the middle of the class, and rework how the different sections of
the generated file are conditionally included for simplicity.
llvm-svn: 113163
2010-09-06 19:11:01 +00:00
f43cb302ca
remove some dead code. t2addrmode_imm8s4 is never used in a
...
pattern, so there is no need to define a matching function.
llvm-svn: 113122
2010-09-05 22:51:11 +00:00
e40007a71b
cleanups.
...
llvm-svn: 113119
2010-09-05 21:18:45 +00:00
65b48b5dfc
zap dead code.
...
llvm-svn: 113073
2010-09-04 18:12:00 +00:00
03f4be86ba
Re-apply r112883:
...
"For ARM stack frames that utilize variable sized objects and have either
large local stack areas or require dynamic stack realignment, allocate a
base register via which to access the local frame. This allows efficient
access to frame indices not accessible via the FP (either due to being out
of range or due to dynamic realignment) or the SP (due to variable sized
object allocation). In particular, this greatly improves efficiency of access
to spill slots in Thumb functions which contain VLAs."
r112986 fixed a latent bug exposed by the above.
llvm-svn: 112989
2010-09-03 18:37:12 +00:00
21a2a2579f
Check the local frame alignment for determining whether dynamic stack
...
alignment should be performed. Otherwise dynamic realignment may trigger
when the register allocator has already used the frame pointer as a general
purpose register. That is, we need to make sure that the list of reserved
registers doesn't change after register allocation.
llvm-svn: 112986
2010-09-03 18:28:19 +00:00
35fafca587
Finish converting the rest of the NEON VLD instructions to use pseudo-
...
instructions prior to regalloc. Since it's getting a little close to
the 2.8 branch deadline, I'll have to leave the rest of the instructions
handled by the NEONPreAllocPass for now, but I didn't want to leave half
of the VLD instructions converted and the other half not.
llvm-svn: 112983
2010-09-03 18:16:02 +00:00
Chris Lattner