27cce1c0b6
Remove obsolete comments. VLDM is implemented in ARMInstrVFP.td.
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llvm-svn: 98395
2010-03-12 22:00:08 +00:00
b8a7427636
fix a bunch of partially ambiguous patterns on ARM. As an
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example, this:
(set DPR:$dst, (fsub (fneg (fmul DPR:$a, DPR:$b)), DPR:$dstin))
is ambiguous because DPR contains both f64 and v2f32. tblgen
currently accidentally picks f64 because it's first in the
regclass.
llvm-svn: 97955
2010-03-08 18:51:21 +00:00
86ba44a4c7
Added Vector Swap (VSWPd and VSWPq) instructions for disassembly only.
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A8.6.405
llvm-svn: 97052
2010-02-24 20:06:07 +00:00
03ac201ad9
Fixed typo of opcodestr, should be "vst1", not "vld1".
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llvm-svn: 97044
2010-02-24 18:00:40 +00:00
d5c472d811
Added for disassembly VST1 (multiple single elements) which stores elements to
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memory from three or four registers and VST2 (multiple two-element structures)
which stores to memory from two double-spaced registers.
A8.6.391 & A8.6.393
llvm-svn: 97018
2010-02-24 02:57:20 +00:00
b14a5c52bc
Added for disassembly VLD1 (multiple single elements) which loads memory into
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three or four registers and VLD2 (multiple two-element structures) which loads
memory into two double-spaced registers.
A8.6.307 & A8.6.310
llvm-svn: 96980
2010-02-23 20:51:23 +00:00
21dbd6f449
Added versions of VCGE, VCGT, VCLE, and VCLT NEON instructions which compare to
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(immediate #0 ) for disassembly only.
A8.6.283, A8.6.285, A8.6.287, A8.6.290
llvm-svn: 96856
2010-02-23 01:42:58 +00:00
886915e3bb
Added VCEQ (immediate #0 ) NEON instruction for disassembly only.
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A8.6.281
llvm-svn: 96838
2010-02-23 00:33:12 +00:00
c6c13a3515
Use NEON vmin/vmax instructions for floating-point selects.
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Radar 7461718.
llvm-svn: 96572
2010-02-18 06:05:53 +00:00
cb2deb2aaf
Remove the NEON N2VSInt instruction class: it's only used in one place and
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since it has no pattern, there's not much point in distinguishing an "N2VS"
class for intrinsics anyway.
llvm-svn: 96525
2010-02-17 22:42:54 +00:00
004d280d5e
More cleanup for NEON:
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* Use "S" abbreviation for scalar single FP registers in class and pattern
names, instead of keeping the "D" (for "double") abbreviation and tacking on
an "s" elsewhere in the name.
* Move the scalar single FP register classes and patterns to be more
consistent with other definitions in the file.
* Rename "VNEGf32d" definition to "VNEGfd" for consistency.
* Deleted the N2VDIntsPat pattern; N2VSPat is good enough.
llvm-svn: 96521
2010-02-17 22:23:11 +00:00
9e89907ed5
Wrap lines to 80 columns and generally try to clean up whitespace and
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indentation. No functional changes.
llvm-svn: 96418
2010-02-17 00:31:29 +00:00
1215c774f2
Add VBIF/VBIT for disassembly only.
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A8.6.279
llvm-svn: 95713
2010-02-09 23:05:23 +00:00
7430a98619
Emit spaces after commas in Neon register lists. This is more consistent
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with the rest of the assembly output, is easier to read, and matches the
expected output for gcc's Neon tests.
llvm-svn: 93703
2010-01-18 01:24:43 +00:00
9349437c65
The Neon "vtst" instruction takes a suffix that is the element size alone --
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adding an "i" to the suffix, indicating that the elements are integers, is
accepted but not part of the standard syntax. This helps us pass a few more
of the Neon tests from gcc.
llvm-svn: 93677
2010-01-17 06:35:17 +00:00
86fc920742
For VLDM/VSTM (Advanced SIMD), set encoding bits Inst{11-8} to 0b1011.
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llvm-svn: 90243
2009-12-01 17:37:06 +00:00
ee536b0ea4
For VMOV (immediate), make some of the encoding bits (cmode and op) unspecified.
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For VMOVv*i[16,32], op bit is don't care, and some cmode bits vary depending on
the immediate values.
Ref: Table A7-15 Modified immediate values for Advanced SIMD instructions.
llvm-svn: 90173
2009-12-01 00:02:02 +00:00
738a97a1db
Massive refactoring of NEON instructions. Separate opcode from data size specifier suffix, move \t up stream to instruction format, and fix more 80 column violations.
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This fixes the NEON asm printing so the "predicate" field is printed between the opcode and the data type suffix.
llvm-svn: 89706
2009-11-23 21:57:23 +00:00
b6528d3244
Partially revert r84730 by removing N2VDup from ARMInstrFormats.td and modifying
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VDUPLND and VDUPLNQ to derive from N2V instead of N2VDup. VDUPLND and VDUPLNQ
now expect op19_18 and op17_16 as the first two args.
llvm-svn: 89699
2009-11-23 21:00:43 +00:00
5ad7416260
Revert r84572 by removing N3VImm from ARMInstrFormats.td now that we can specify
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{?,?,?,?} as op11_8 for VEXTd and VEXTq.
llvm-svn: 89693
2009-11-23 20:09:13 +00:00
e97457afbc
Partially revert r89377 by removing NLdStLN class definition from
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ARMInstrFormats.td and fixing VLD[234]LN* and VST[234]LN* to derive from NLdSt
instead of NLdStLN.
llvm-svn: 89684
2009-11-23 18:16:16 +00:00
ebc60ef80c
Make it clear that the index bit(s) of Vector Get Lane and Vector Set Lane
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should be left unspecified now that Bob Wilson has fixed pr5470.
llvm-svn: 89676
2009-11-23 17:48:17 +00:00
a33fc86be3
Add predicate operand to NEON instructions. Fix lots (but not all) 80 col violations in ARMInstrNEON.td.
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llvm-svn: 89542
2009-11-21 06:21:52 +00:00
b3b8209d77
Added NLdStLN which is similar to NLdSt with the exception that op7_4 is not
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fully specified at this level. Subclasses of NLdStLN can specify selective
bit(s) for Inst{7-4}, as is done for VLD[234]LN* and VST[234]LN* inside
ARMInstrNEON.td.
llvm-svn: 89377
2009-11-19 19:20:17 +00:00
e129dd311e
Use table to separate opcode from operands.
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llvm-svn: 86965
2009-11-12 07:16:34 +00:00
d7cf55cd0e
Use Unified Assembly Syntax for the ARM backend.
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llvm-svn: 86494
2009-11-09 00:11:35 +00:00
d95ccd6c4d
Print VMOV (immediate) operands as hexadecimal values. Apple's assembler
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will not accept negative values for these. LLVM's default operand printing
sign extends values, so that valid unsigned values appear as negative
immediates. Print all VMOV immediate operands as hex values to resolve this.
Radar 7372576.
llvm-svn: 86301
2009-11-06 23:33:28 +00:00
0f38d989bd
Do not infer the target type for COPY_TO_REGCLASS from dest regclass, this won't work if it can contain several types. Require explicit result type for the node for now. This fixes PR5364.
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PS: It seems that blackfin usage of copy_to_regclass is completely bogus!
llvm-svn: 85766
2009-11-02 00:11:39 +00:00
5cba8de2c8
vml[as].f32 cause stalls in following advanced SIMD instructions. Avoid using
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them for scalar floating point operations for now.
llvm-svn: 85697
2009-10-31 22:57:36 +00:00
0db964a3a0
Fix NEON VST2LN instruction encoding.
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Patch by Johnny Chen.
llvm-svn: 84767
2009-10-21 17:54:01 +00:00
87671da29a
Revert 84732. It was the wrong fix.
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llvm-svn: 84766
2009-10-21 17:52:34 +00:00
5b5cb92816
Fix some more NEON instruction encoding problems.
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Thanks to Johnny Chen for discovering the problem.
llvm-svn: 84732
2009-10-21 02:27:20 +00:00
bd3650cc84
Leave some NEON instruction encoding bits unspecified instead of setting
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a default value of zero. This is important for decoding the instructions.
Patch by Johnny Chen, with some changes from me, too.
llvm-svn: 84730
2009-10-21 02:15:46 +00:00
772b2f84eb
Refs: A8-598.
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Leave Inst{11-8}, which represents the starting byte index of the extracted
result in the concatenation of the operands and is left unspecified.
Patch by Johnny Chen.
llvm-svn: 84572
2009-10-20 00:38:19 +00:00
01404ecec7
Fix more NEON instruction encodings.
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Patch by Johnny Chen.
llvm-svn: 84243
2009-10-16 03:58:44 +00:00
4138b11c93
Fix encoding bits for N3VLInt3_QHS multiclass with 8-bit elements.
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Patch by Johnny Chen.
llvm-svn: 84206
2009-10-15 21:57:47 +00:00
cfcf6bc70d
Fix instruction encoding bits for NEON VPADAL.
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Patch by Johnny Chen.
llvm-svn: 84146
2009-10-14 21:43:17 +00:00
94068707e1
Inst{11-8} for vshl should be 0b0101, not 0b1111.
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Refs: A7-17 & A8-750.
Patch by Johnny Chen.
llvm-svn: 84131
2009-10-14 20:31:01 +00:00
84e7967fae
Add codegen support for NEON vst4lane intrinsics with 128-bit vectors.
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llvm-svn: 83600
2009-10-09 00:01:36 +00:00
c409030838
Add codegen support for NEON vst3lane intrinsics with 128-bit vectors.
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llvm-svn: 83598
2009-10-08 23:51:31 +00:00
b851eb356a
Add codegen support for NEON vst2lane intrinsics with 128-bit vectors.
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llvm-svn: 83596
2009-10-08 23:38:24 +00:00
38ba47225a
Add codegen support for NEON vld4lane intrinsics with 128-bit vectors.
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Also fix some copy-and-paste errors in previous changes.
llvm-svn: 83590
2009-10-08 22:53:57 +00:00
cf54e934f8
Add codegen support for NEON vld3lane intrinsics with 128-bit vectors.
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llvm-svn: 83585
2009-10-08 22:27:33 +00:00
c2728f44a9
Add codegen support for NEON vld2lane intrinsics with 128-bit vectors.
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llvm-svn: 83568
2009-10-08 18:56:10 +00:00
b6b0ab6117
Add codegen support for NEON vst4 intrinsics with <1 x i64> vectors.
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llvm-svn: 83526
2009-10-08 05:18:18 +00:00
71387b4b2f
Add codegen support for NEON vst3 intrinsics with <1 x i64> vectors.
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llvm-svn: 83518
2009-10-08 00:28:28 +00:00
d4f5670096
Add codegen support for NEON vst2 intrinsics with <1 x i64> vectors.
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llvm-svn: 83513
2009-10-08 00:21:01 +00:00
32cc4ec304
Add codegen support for NEON vld4 intrinsics with <1 x i64> vectors.
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llvm-svn: 83508
2009-10-07 23:54:04 +00:00
5ef3c6d9f4
Add codegen support for NEON vld3 intrinsics with <1 x i64> vectors.
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llvm-svn: 83506
2009-10-07 23:39:57 +00:00
763be1a248
Add codegen support for NEON vld2 intrinsics with <1 x i64> vectors.
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llvm-svn: 83502
2009-10-07 22:57:01 +00:00
Bob Wilson