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Author SHA1 Message Date
Dan Gohman 56e1cef705 Constant pointers to objects don't need reference counting. 
llvm-svn: 138242
 2011-08-22 17:29:11 +00:00
Dan Gohman bce94fded8 Make a few tests slightly more strict. 
llvm-svn: 138241
 2011-08-22 17:27:02 +00:00
Duncan Sands b40654e21d Testcase for PR10663. 
llvm-svn: 138231
 2011-08-22 10:32:09 +00:00
Jim Grosbach bd16424f91 Fix AsmParser binary precedence for shift operators. 
rdar://9976729

llvm-svn: 138208
 2011-08-20 16:24:13 +00:00
Jim Grosbach 3322f02a03 Tidy up. Whitespace. 
llvm-svn: 138207
 2011-08-20 16:10:09 +00:00
Nadav Rotem ad4a70ad3e Add constant folding support for bitcasts of splat vectors to integers. 
llvm-svn: 138206
 2011-08-20 14:02:29 +00:00
Eric Christopher 6582dfa7c5 Remove remainder of migrated or obsolete tests from FrontendC and remove 
the empty directory.

llvm-svn: 138181
 2011-08-20 01:04:56 +00:00
Eric Christopher c19fd6eadc Remove migrated or obsolete tests. 
llvm-svn: 138176
 2011-08-20 00:49:30 +00:00
Eric Christopher 1efe3d9663 Remove obsolete or migrated tests. 
llvm-svn: 138173
 2011-08-20 00:38:20 +00:00
Chad Rosier d6641af80c With the fix in r138164: "Add <imp-def> operands to QQ and QQQQ stack loads." 
-verify-machineinstrs can be enabled for this test case.

llvm-svn: 138171
 2011-08-20 00:34:45 +00:00
Eric Christopher c2528a529a Remove obsoleted test. 
llvm-svn: 138170
 2011-08-20 00:26:30 +00:00
Eric Christopher a1124b45d2 Remove tests that were either migrated to clang or are obsolete. 
llvm-svn: 138168
 2011-08-20 00:25:42 +00:00
Eric Christopher 2f53dc2e05 Remove the rest of the files in FrontendC++ and the directory itself. 
All tests have been updated and migrated into clang or were obsolete.

llvm-svn: 138165
 2011-08-20 00:17:58 +00:00
Chad Rosier be7625161e VMOVQQQQs pseudo instructions are only created by ARMBaseInstrInfo::copyPhysReg. 
Therefore, rather then generate a pseudo instruction, which is later expanded,
generate the necessary instructions in place.

llvm-svn: 138163
 2011-08-20 00:17:25 +00:00
Eric Christopher 74cfab0fbe Remove migrated or obsolete tests. 
llvm-svn: 138156
 2011-08-20 00:08:36 +00:00
Eric Christopher a0b6bc5739 Remove migrated or obsolete tests. 
llvm-svn: 138149
 2011-08-19 23:41:50 +00:00
Devang Patel 59e27c5f12 Do not use named md nodes to track variables that are completely optimized. This does not scale while doing LTO with debug info. New approach is to include list of variables in the subprogram info directly. 
llvm-svn: 138145
 2011-08-19 23:28:12 +00:00
Jim Grosbach 2597722e07 Thumb parsing and encoding support for NOP. 
The irony is not lost that this is not a completely trivial patchset.

llvm-svn: 138143
 2011-08-19 23:24:36 +00:00
Eric Christopher 67edb5ef36 Remove obsolete test. 
llvm-svn: 138141
 2011-08-19 23:18:12 +00:00
Eric Christopher 2c16fef036 Remove migrated test. 
llvm-svn: 138140
 2011-08-19 23:18:10 +00:00
Jim Grosbach 8d77bb5f06 Use regex to remove false dependencies on register allocation. 
llvm-svn: 138137
 2011-08-19 23:10:31 +00:00
Eric Christopher 48f1599b03 Remove obsolete or migrated tests. 
llvm-svn: 138135
 2011-08-19 23:08:41 +00:00
Jim Grosbach 37aa348195 Thumb assembly parsing and encoding for NEG. 
llvm-svn: 138131
 2011-08-19 22:51:03 +00:00
Jim Grosbach 459422d750 Be more lenient on tied operand matching for MUL. 
llvm-svn: 138124
 2011-08-19 22:30:46 +00:00
Bruno Cardoso Lopes d126347f32 Re-write part of VEX encoding logic, to be more easy to read! Also fix 
a bug and add a testcase!

llvm-svn: 138123
 2011-08-19 22:27:29 +00:00
Eric Christopher 43d15b98d2 Remove tests migrated to clang. 
llvm-svn: 138121
 2011-08-19 22:26:09 +00:00
Eric Christopher 1e1cbc5f65 Remove previously migrated test. 
llvm-svn: 138120
 2011-08-19 22:26:06 +00:00
Jim Grosbach 066e9ec1e4 Update tests. 
llvm-svn: 138116
 2011-08-19 22:19:48 +00:00
Eric Christopher 58ce352d32 Remove tests migrated to clang or are unnecessary. 
llvm-svn: 138115
 2011-08-19 22:17:09 +00:00
Jim Grosbach fd4de3aeff Thumb assembly parsing and encoding for MVN. 
llvm-svn: 138109
 2011-08-19 22:09:23 +00:00
Jim Grosbach 8e048495c8 Thumb assembly parsing and encoding for MUL. 
llvm-svn: 138108
 2011-08-19 22:07:46 +00:00
Eric Christopher 029529369b Remove this test. The feature and test have already been migrated to clang. 
llvm-svn: 138101
 2011-08-19 21:51:41 +00:00
Eric Christopher 772aa6c82e Remove tests migrated to clang. 
llvm-svn: 138100
 2011-08-19 21:51:39 +00:00
Eric Christopher 981c15ef76 Remove 2009-09-04-modify-crash.cpp as clang doesn't support 32-bit kext. 
llvm-svn: 138087
 2011-08-19 21:21:28 +00:00
Eric Christopher 05927b0c90 Remove migrated tests. 
llvm-svn: 138086
 2011-08-19 21:21:26 +00:00
Eric Christopher e8ad105202 Remove migrated test. 
llvm-svn: 138085
 2011-08-19 21:21:24 +00:00
Eric Christopher 526162d18e Remove this test. There are other, duplicates, in the clang test suite. 
llvm-svn: 138084
 2011-08-19 21:21:21 +00:00
Eric Christopher 8af4e41734 Add file. 
llvm-svn: 138083
 2011-08-19 21:21:20 +00:00
Eric Christopher 810ed3a7c3 Move 2010-03-22-empty-baseclass.cpp from a frontend+opt test to just 
an opt test.

llvm-svn: 138082
 2011-08-19 21:21:14 +00:00
Jim Grosbach d07e104844 Add FIXME. 
llvm-svn: 138077
 2011-08-19 20:48:54 +00:00
Jim Grosbach f86cd37bef Thumb assembly parsing and encoding for MOV. 
llvm-svn: 138076
 2011-08-19 20:46:54 +00:00
Jim Grosbach 1eb6eb0955 Thumb assembly parsing and encoding for LSR. 
llvm-svn: 138065
 2011-08-19 19:34:22 +00:00
Jim Grosbach 3245520ade Thumb assembly parsing and encoding for LSL(register). 
llvm-svn: 138064
 2011-08-19 19:30:58 +00:00
Jim Grosbach 5503c3a4e8 Thumb assembly parsing and encoding for LSL(immediate). 
llvm-svn: 138063
 2011-08-19 19:29:25 +00:00
Jim Grosbach 7c4739da3c Thumb assembly parsing and encoding for LDRSB and LDRSH. 
llvm-svn: 138061
 2011-08-19 19:17:58 +00:00
Jim Grosbach 26d3587bd8 Thumb assembly parsing and encoding for LDRH. 
llvm-svn: 138060
 2011-08-19 18:55:51 +00:00
Jim Grosbach a32c753ebf Thumb assembly parsing and encoding for LDRB. 
llvm-svn: 138059
 2011-08-19 18:49:59 +00:00
Jim Grosbach 106281f329 Thumb assembly parsing and encoding for LDR(register). 
llvm-svn: 138056
 2011-08-19 18:35:06 +00:00
Jim Grosbach 181d2f92b5 Thumb assembly parsing and encoding for LDR(literal). 
llvm-svn: 138052
 2011-08-19 18:20:48 +00:00
Jim Grosbach 23983d6bd9 Thumb assembly parsing and encoding for LDR(immediate) form T2. 
llvm-svn: 138050
 2011-08-19 18:13:48 +00:00
Jim Grosbach 3fe94e3ef8 Thumb assembly parsing and encoding for LDR(immediate) form T1. 
llvm-svn: 138047
 2011-08-19 17:55:24 +00:00
Craig Topper ba6c2a52c7 Add TB encoding to VEX versions of SSE fp logical operations to fix disassembler 
llvm-svn: 138034
 2011-08-19 05:28:50 +00:00
Jakob Stoklund Olesen 90b6018c8f Add test case for r138018. 
llvm-svn: 138033
 2011-08-19 04:30:24 +00:00
Bruno Cardoso Lopes 22241acc29 Fix PR10677. Initial patch and idea by Peter Cooper but I've changed the 
implementation!

llvm-svn: 138029
 2011-08-19 02:23:56 +00:00
Dan Gohman b38940135b Track a retain+release nesting level independently of the 
known-incremented level, because the two concepts can be used
to prove the saftey of a retain+release removal in different
ways.

llvm-svn: 138016
 2011-08-19 00:26:36 +00:00
Akira Hatanaka fb4161ae88 Use subword loads instead of a 4-byte load when the size of a structure (or a 
piece of it) that is being passed by value is smaller than a word.

llvm-svn: 138007
 2011-08-18 23:39:37 +00:00
Owen Anderson 96b7ad2e17 STC2L_POST and STC2L_POST should be handled the same as STCL_POST/LDC_POST for the purposes of decoding all operands except the predicate. 
Found by randomized testing.

llvm-svn: 138003
 2011-08-18 22:47:44 +00:00
Owen Anderson 192a760b54 Fix the decoding of RFE instruction. RFEs have the load bit set, while SRSs have it unset. 
llvm-svn: 138000
 2011-08-18 22:31:17 +00:00
Owen Anderson 67d6f11974 Improve handling of failure and unpredictable cases for CPS, STR, and SMLA instructions. 
Fixes a large class of disassembler crashes found by randomized testing.

llvm-svn: 137995
 2011-08-18 22:11:02 +00:00
Ivan Krasin d7cbd4c518 FastISel: avoid function calls between the materialization of the constant and its use. 
llvm-svn: 137993
 2011-08-18 22:06:10 +00:00
Jim Grosbach 90103ccc05 Thumb assembly parsing and encoding for LDM instruction. 
Fix base register type and canonicallize to the "ldm" spelling rather than
"ldmia." Add diagnostics for incorrect writeback token and out-of-range
registers.

llvm-svn: 137986
 2011-08-18 21:50:53 +00:00
Owen Anderson 627021d7c0 More Thumb1 decoding tests. 
llvm-svn: 137974
 2011-08-18 20:05:06 +00:00
Devang Patel 0071f8a48e Add another test. 
llvm-svn: 137969
 2011-08-18 18:50:25 +00:00
Devang Patel f907e78b78 Add test to check type uniquing. 
llvm-svn: 137968
 2011-08-18 18:40:49 +00:00
Jim Grosbach 6cb336cb09 Thumb assembly parsing and encoding for EOR. 
llvm-svn: 137964
 2011-08-18 18:10:38 +00:00
Jim Grosbach 4f240a1fd5 Thumb assembly parsing and encoding for CMP. 
llvm-svn: 137963
 2011-08-18 18:08:29 +00:00
James Molloy 9f9371ccb3 Test commit; adding test for invalid LDRD which was part of the patch for r137647 but seemingly didn't get svn add'ed. 
llvm-svn: 137960
 2011-08-18 18:03:02 +00:00
Jim Grosbach 47bf39d921 Thumb assembly parsing and encoding test for CMN. 
llvm-svn: 137957
 2011-08-18 17:55:03 +00:00
Owen Anderson ec3884c50a Port over BL/BLX to disassembly tests. 
llvm-svn: 137954
 2011-08-18 17:43:52 +00:00
Jim Grosbach 0081879ee7 ARM assembly parsing and encoding test for BX/BLX (register). 
llvm-svn: 137949
 2011-08-18 17:02:28 +00:00
Jim Grosbach 8b7158e557 ARM assembly parsing and encoding test for BL/BLX (immediate). 
llvm-svn: 137948
 2011-08-18 17:00:09 +00:00
Richard Osborne 56f3b70225 Add intrinsics for SETEV, GETED, GETET. 
llvm-svn: 137938
 2011-08-18 13:00:48 +00:00
Bruno Cardoso Lopes 3c7d6eb64c Cleanup vector logical ops in AVX and add use int versions for simple 
v2i64

llvm-svn: 137919
 2011-08-18 02:11:34 +00:00
Owen Anderson a90896397b Port new Thumb1 encoding tests over to decoding tests. 
llvm-svn: 137902
 2011-08-17 23:37:33 +00:00
Jim Grosbach 1b43828958 ARM assembly parsing and encoding test for BKPT. 
llvm-svn: 137898
 2011-08-17 23:11:13 +00:00
Jim Grosbach e3bdcd0ea8 ARM assembly parsing and encoding test for BIC. 
llvm-svn: 137895
 2011-08-17 23:00:53 +00:00
Jim Grosbach cbd4ab104b Thumb assembly parsing and encoding for B. 
llvm-svn: 137891
 2011-08-17 22:57:40 +00:00
Jim Grosbach d3e8e29124 Thumb assembly parsing and encoding for ASR. 
llvm-svn: 137889
 2011-08-17 22:49:09 +00:00
Eli Friedman 9a468153e1 Atomic load/store handling for the passes using memdep (GVN, DSE, memcpyopt). 
llvm-svn: 137888
 2011-08-17 22:22:24 +00:00
Bruno Cardoso Lopes 1a87fcb9ba Fix PR10688. Add support for spliting 256-bit vector shifts when the 
shift amount is variable

llvm-svn: 137885
 2011-08-17 22:12:20 +00:00
Jim Grosbach e2a0404a69 Thumb assembly parsing and encoding for ADR. 
llvm-svn: 137864
 2011-08-17 20:37:40 +00:00
Jim Grosbach e2d152016f Add a couple of FIXMEs. 
llvm-svn: 137861
 2011-08-17 20:35:57 +00:00
Devang Patel 35ea5cfd46 Fix test case. 
llvm-svn: 137847
 2011-08-17 18:48:28 +00:00
Devang Patel ae2848ed69 Remove superficial test. 
llvm-svn: 137846
 2011-08-17 18:39:13 +00:00
Devang Patel 3fee10b7d2 Robustify test. 
llvm-svn: 137845
 2011-08-17 18:38:44 +00:00
Owen Anderson d40d838cc4 Start building a Thumb1 decoding test file based on the Thumb1 parsing/encoding test file. 
llvm-svn: 137840
 2011-08-17 18:21:36 +00:00
Eli Friedman d7749be2d7 Silly mistake from r137777; restore significant isStructTy() checks. While here, be a bit more defensive 
with unknown instructions.

Fixes PR10687.

llvm-svn: 137836
 2011-08-17 18:10:43 +00:00
Jim Grosbach 80636b48c0 Thumb assembly parsing and encoding for ADC(register) instruction. 
llvm-svn: 137833
 2011-08-17 17:55:28 +00:00
Jim Grosbach a806eebe13 Add missing '@' delimiter. 
llvm-svn: 137832
 2011-08-17 17:46:01 +00:00
Owen Anderson a4043c4b32 Allow the MCDisassembler to return a "soft fail" status code, indicating an instruction that is disassemblable, but invalid. Only used for ARM UNPREDICTABLE instructions at the moment. 
Patch by James Molloy.

llvm-svn: 137830
 2011-08-17 17:44:15 +00:00
Bruno Cardoso Lopes be5e987379 Introduce matching patterns for vbroadcast AVX instruction. The idea is to 
match splats in the form (splat (scalar_to_vector (load ...))) whenever
the load can be folded. All the logic and instruction emission is
working but because of PR8156, there are no ways to match loads, cause
they can never be folded for splats. Thus, the tests are XFAILed, but
I've tested and exercised all the logic using a relaxed version for
checking the foldable loads, as if the bug was already fixed. This
should work out of the box once PR8156 gets fixed since MayFoldLoad will
work as expected.

llvm-svn: 137810
 2011-08-17 02:29:19 +00:00
Bruno Cardoso Lopes 3400825b41 Update test to not use the scalar type to splat from a load 
llvm-svn: 137809
 2011-08-17 02:29:15 +00:00
Bruno Cardoso Lopes ed786a346e Now that we have a canonical way to handle 256-bit splats: 
vinsertf128 $1 + vpermilps $0, remove the old code that used to first
do the splat in a 128-bit vector and then insert it into a larger one.
This is better because the handling code gets simpler and also makes a
better room for the upcoming vbroadcast!

llvm-svn: 137807
 2011-08-17 02:29:10 +00:00
Akira Hatanaka 5360f88355 Add support for ext and ins. 
llvm-svn: 137804
 2011-08-17 02:05:42 +00:00
Jim Grosbach e9ab47a72a Thumb ADD(immediate) parsing support. 
llvm-svn: 137788
 2011-08-16 23:57:34 +00:00
Eli Friedman e1df253200 An additional atomic test; related to r137662. 
llvm-svn: 137786
 2011-08-16 23:29:17 +00:00
Jim Grosbach b7fa2c0a53 Thumb parsing diagnostics for low-reg requirements on ADD and MOV. 
llvm-svn: 137779
 2011-08-16 22:20:01 +00:00
Eli Friedman 0793eb4c46 A bunch of misc fixes to SCCPSolver::ResolvedUndefsIn, including a fix to stop 
making random bad assumptions about instructions which are not explicitly listed.  

Includes fix for rdar://9956541, a version of "undef ^ undef should return
0 because it's easier than arguing with users".

llvm-svn: 137777
 2011-08-16 22:06:31 +00:00
Eric Christopher d56ba41bc3 Remove tests that have been obsoleted or migrated to clang/optimizer tests. 
llvm-svn: 137775
 2011-08-16 21:46:25 +00:00
Jim Grosbach 58ffdccab1 Thumb assembly parsing and encoding for ADD(register) instruction. 
llvm-svn: 137759
 2011-08-16 21:34:08 +00:00
Eli Friedman 56f2f21254 Minor bug in SCCP found by inspection. (I don't think it's possible to hit this with a normal pass pipeline, but fixing for completeness.) 
llvm-svn: 137755
 2011-08-16 21:12:35 +00:00
Jim Grosbach 2c21bf4b43 Add testcase for r137746. 
llvm-svn: 137754
 2011-08-16 21:11:21 +00:00
Jim Grosbach d3ad0aa413 Tidy up formatting. 
llvm-svn: 137747
 2011-08-16 20:55:41 +00:00
Jim Grosbach 3e941aee69 ARM thumb assembly parsing for arithmetic flag setting instructions. 
Thumb one requires that many arithmetic instruction forms have an 'S'
suffix. For Thumb2, the whether the suffix is required or precluded depends
on whether the instruction is in an IT block. Use target parser predicates
to check for these sorts of context-sensitive constraints.

llvm-svn: 137746
 2011-08-16 20:45:50 +00:00
Bruno Cardoso Lopes 2e99f1b3aa Instead of always leaving the work to the generic legalizer when 
there is no support for native 256-bit shuffles, be more smart in some
cases, for example, when you can extract specific 128-bit parts and use
regular 128-bit shuffles for them. Example:

For this shuffle:
  shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32>
                <i32 1, i32 0, i32 7, i32 6>

This was expanded to:
  vextractf128  $1, %ymm1, %xmm2
  vpextrq $0, %xmm2, %rax
  vmovd %rax, %xmm1
  vpextrq $1, %xmm2, %rax
  vmovd %rax, %xmm2
  vpunpcklqdq %xmm1, %xmm2, %xmm1
  vpextrq $0, %xmm0, %rax
  vmovd %rax, %xmm2
  vpextrq $1, %xmm0, %rax
  vmovd %rax, %xmm0
  vpunpcklqdq %xmm2, %xmm0, %xmm0
  vinsertf128 $1, %xmm1, %ymm0, %ymm0
  ret

Now we get:
  vshufpd $1, %xmm0, %xmm0, %xmm0
  vextractf128  $1, %ymm1, %xmm1
  vshufpd $1, %xmm1, %xmm1, %xmm1
  vinsertf128 $1, %xmm1, %ymm0, %ymm0

llvm-svn: 137733
 2011-08-16 18:21:54 +00:00
Akira Hatanaka 7d7bec5acf Add test case for r137711. 
llvm-svn: 137725
 2011-08-16 17:32:01 +00:00
Jim Grosbach 45e50d8a0b ARM .align NOP padding uses different encoding pre-ARMv6. 
Patch by Kristof Beyls and James Malloy.

llvm-svn: 137723
 2011-08-16 17:06:20 +00:00
Akira Hatanaka 2263c10946 Fix handling of double precision loads and stores when Mips1 is targeted. 
Mips1 does not support double precision loads or stores, therefore two single
precision loads or stores must be used in place of these instructions. This 
patch treats double precision loads and stores as if they are legal
instructions until MCInstLowering, instead of generating the single precision
instructions during instruction selection or Prolog/Epilog code insertion.

Without the changes made in this patch, llc produces code that has the same 
problem described in r137484 or bails out when
MipsInstrInfo::storeRegToStackSlot or loadRegFromStackSlot is called before
register allocation.

llvm-svn: 137711
 2011-08-16 03:51:51 +00:00
Eli Friedman ac992afd93 Fix test. 
llvm-svn: 137703
 2011-08-16 01:42:56 +00:00
Eli Friedman a917d4f9b4 Revert a bit of r137667; the logic in question can safely handle atomic load/store. 
llvm-svn: 137702
 2011-08-16 01:28:22 +00:00
Eric Christopher 5403862ab7 Migrate this test from llvm/test/FrontendC++/ptr-to-method-devirt.cpp and 
FileCheckize. It is more properly an optimizer test.

llvm-svn: 137700
 2011-08-16 01:17:17 +00:00
Eli Friedman 0ffdf2ea0b Update SimplifyCFG for atomic operations. 
This commit includes a mention of the landingpad instruction, but it's not
changing the behavior around it.  I think the current behavior is correct,
though.  Bill, can you double-check that?

llvm-svn: 137691
 2011-08-15 23:59:28 +00:00
Eli Friedman 01a67111d1 Add comments and test for atomic load/store and mem2reg. 
llvm-svn: 137690
 2011-08-15 23:55:52 +00:00
Owen Anderson 53440984b3 Add a test file for Thumb2 NEON. 
llvm-svn: 137687
 2011-08-15 23:42:20 +00:00
Bruno Cardoso Lopes 67005029bc Reorder declarations of vmovmskp* and also put the necessary AVX 
predicate and TB encoding fields. This fix the encoding for the
attached testcase. This fixes PR10625.

llvm-svn: 137684
 2011-08-15 23:36:45 +00:00
Eli Friedman 8bc586e770 Update instcombine for atomic load/store. 
llvm-svn: 137664
 2011-08-15 22:09:40 +00:00
Bruno Cardoso Lopes cbe7feeab9 Fix PR10656. It's only profitable to use 128-bit inserts and extracts 
when AVX mode is one. Otherwise is just more work for the type
legalizer.

llvm-svn: 137661
 2011-08-15 21:45:54 +00:00
Owen Anderson 5286bd2d01 Add some more comprehensive VFP decoding tests. 
llvm-svn: 137657
 2011-08-15 21:29:01 +00:00
Eric Christopher 8c5f3f7624 Fix this test to avoid leaving a temporary file behind. 
llvm-svn: 137651
 2011-08-15 20:55:03 +00:00
Eli Friedman 91386c7be4 Atomic load/store support in LICM. 
llvm-svn: 137648
 2011-08-15 20:52:09 +00:00
Owen Anderson 1d5d2cac8c Enforce the constraint that Rt must be even on LDRD/STRD instructions in ARM mode. Update tests to reflect this fact. 
Patch by James Molloy.

llvm-svn: 137647
 2011-08-15 20:51:32 +00:00
Eric Christopher 990dd3d0fb Add an ipsccp test. Migrated from test/FrontendC++. 
llvm-svn: 137646
 2011-08-15 20:50:36 +00:00
Owen Anderson 944f4923a4 Add a test for Thumb1 LDRSH decoding. 
llvm-svn: 137645
 2011-08-15 20:15:43 +00:00
Owen Anderson f746b0ec53 Add testcase for STRH. Patch by James Molloy. 
llvm-svn: 137644
 2011-08-15 20:12:03 +00:00
Owen Anderson 61a3ece665 Fix incorrect encoding of UMAAL and friends. Patch by James Molloy. 
llvm-svn: 137641
 2011-08-15 20:08:25 +00:00
Owen Anderson 3157f2eebe Fix decoding LDRSB and LDRSH in Thumb1 mode. Patch by James Molloy. 
llvm-svn: 137636
 2011-08-15 19:00:06 +00:00
Owen Anderson b9d82f411c Fix problems decoding the to/from-lane NEON memory instructions, and add a comprehensive NEON decoding testcase. 
llvm-svn: 137635
 2011-08-15 18:44:44 +00:00
Nick Lewycky 746e317953 This transform is not safe. Thanks to Eli for pointing that out! 
llvm-svn: 137575
 2011-08-14 04:51:49 +00:00
Nick Lewycky ae13df60a6 Don't attempt to add 'nsw' when intermediate instructions had no such guarantee. 
llvm-svn: 137572
 2011-08-14 03:41:33 +00:00
Nick Lewycky de49278c26 Teach instcombine to preserve the nsw bit by doing an after-the-fact analysis 
when combining add and sub instructions. Patch by Pranav Bhandarkar!

llvm-svn: 137570
 2011-08-14 01:45:19 +00:00
Eli Friedman 9f56acc124 Fix test. 
llvm-svn: 137556
 2011-08-13 17:06:34 +00:00
Bob Wilson d1de7764be Expand VMOVQQQQ pseudo instructions. 
Apparently we never added code to expand these pseudo instructions, and in
over a year, no one has noticed.  Our register allocator must be awesome!

llvm-svn: 137551
 2011-08-13 05:14:55 +00:00
Eli Friedman 02e737b08e Move "atomic" and "volatile" designations on instructions after the opcode 
of the instruction.

Note that this change affects the existing non-atomic load and store
instructions; the parser now accepts both forms, and the change is noted
in the release notes.

llvm-svn: 137527
 2011-08-12 22:50:01 +00:00
Bruno Cardoso Lopes f15dfe5818 The VPERM2F128 is a AVX instruction which permutes between two 256-bit 
vectors. It operates on 128-bit elements instead of regular scalar
types. Recognize shuffles that are suitable for VPERM2F128 and teach
the x86 legalizer how to handle them.

llvm-svn: 137519
 2011-08-12 21:48:26 +00:00
Akira Hatanaka 2fcc1cfdce Define unaligned load and store. 
llvm-svn: 137515
 2011-08-12 21:30:06 +00:00
Owen Anderson 2d1d7a11f8 Fix some remaining issues with decoding ARM-mode memory instructions, and add another batch of tests. 
llvm-svn: 137502
 2011-08-12 20:36:11 +00:00
Owen Anderson ed6d3e813e Port over the basic ARM encodings test file to a decoding test file. Greatly increases our test coverage of basic ARM-mode instructions. 
llvm-svn: 137495
 2011-08-12 19:42:45 +00:00
Akira Hatanaka 2f6b944f56 Test case for 137484 
llvm-svn: 137486
 2011-08-12 18:12:06 +00:00
Jim Grosbach d1b60f7a6d Tidy up formatting. 
llvm-svn: 137471
 2011-08-12 17:43:31 +00:00
Jim Grosbach 234317d12a Tidy up formatting. 
llvm-svn: 137464
 2011-08-12 17:01:02 +00:00
Benjamin Kramer 91ea511436 MachOWriter: Don't crash on fixups with arithmetic, emit a relocation instead. This matches what as does. 
llvm-svn: 137414
 2011-08-12 01:51:29 +00:00
Dan Gohman 10a18d55ce Don't convert objc_autoreleaseReturnValue to objc_autorelease if the result 
is returned through a bitcast.

llvm-svn: 137402
 2011-08-12 00:36:31 +00:00
Dan Gohman 121302772d Don't let arbitrary calls disrupt nested retain+release pairs if 
the retains and releases all use the same SSA pointer value.

Also, don't let CFG hazards disrupt nested retain+release pair
optimizations.

llvm-svn: 137399
 2011-08-12 00:26:31 +00:00
Jim Grosbach 1978ddf769 Clean up formatting a bit. 
llvm-svn: 137393
 2011-08-11 23:57:17 +00:00
Jim Grosbach 8cffa28af8 ARM vector compare to zero instruction assembly parsing support. 
llvm-svn: 137389
 2011-08-11 23:51:13 +00:00
Andrew Trick 2d8494a030 A slew of unit tests for the recent LoopInfo::updateUnloop feature 
checked in at r137276 and r137341.

llvm-svn: 137385
 2011-08-11 23:38:09 +00:00
Andrew Trick 2b6860f0a1 Allow loop unrolling to get known trip counts from ScalarEvolution. 
SCEV unrolling can unroll loops with arbitrary induction variables. It
is a prerequisite for -disable-iv-rewrite performance. It is also
easily handles loops of arbitrary structure including multiple exits
and is generally more robust.

This is under a temporary option to avoid affecting default
behavior for the next couple of weeks. It is needed so that I can
checkin unit tests for updateUnloop.

llvm-svn: 137384
 2011-08-11 23:36:16 +00:00
Akira Hatanaka 79d60d0e94 Enclose directive .cprestore with .set macro and nomacro to silence assembler 
warning. 

llvm-svn: 137378
 2011-08-11 22:42:31 +00:00
Jim Grosbach aa07cb6a98 Fix tests per now-correct encoding as of r137371. 
llvm-svn: 137376
 2011-08-11 22:31:48 +00:00
Jim Grosbach e25942154c ARM STRT assembly parsing and encoding. 
llvm-svn: 137372
 2011-08-11 22:18:00 +00:00