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14049 Commits

Author SHA1 Message Date
Roman Divacky 71038e7021 Set CR1EQ only when lowering vararg floating arguments (not any vararg 
arguments as before), unset CR1EQ otherwise.

llvm-svn: 138802
 2011-08-30 17:04:16 +00:00
Craig Topper 4f2fba1108 Add vvvv support to disassembling of instructions with MRMDestMem and MRMDestReg form. Needed to support mem dest form of vmaskmovps/d. Fixes PR10807. 
llvm-svn: 138795
 2011-08-30 07:09:35 +00:00
Evan Cheng e891654a58 Change ARM / Thumb2 addc / adde and subc / sube modeling to use physical 
register dependency (rather than glue them together). This is general
goodness as it gives scheduler more freedom. However it is motivated by
a nasty bug in isel.

When a i64 sub is expanded to subc + sube.
  libcall #1
     \
      \        subc 
       \       /  \
        \     /    \
         \   /    libcall #2
          sube

If the libcalls are not serialized (i.e. both have chains which are dag
entry), legalizer can serialize them in arbitrary orders. If it's
unlucky, it can force libcall #2 before libcall #1 in the above case.

  subc
   |
  libcall #2
   |
  libcall #1
   |
  sube

However since subc and sube are "glued" together, this ends up being a
cycle when the scheduler combine subc and sube as a single scheduling
unit.

The right solution is to fix LegalizeType too chains the libcalls together.
However, LegalizeType is not processing nodes in order so that's harder than
it should be. For now, the move to physical register dependency will do.

rdar://10019576

llvm-svn: 138791
 2011-08-30 01:34:54 +00:00
Owen Anderson 3e0aa03fe9 Add missing encoding information for some of the GPR<->FP register moves. 
llvm-svn: 138780
 2011-08-29 23:15:25 +00:00
Jim Grosbach 4b23a65582 Remove redundant tests from XFAIL'ed test file. 
llvm-svn: 138779
 2011-08-29 23:04:04 +00:00
Jim Grosbach 55d6f43cab Thumb2 assembly parsing and encoding support for ADC(immediate). 
llvm-svn: 138778
 2011-08-29 23:01:38 +00:00
Jim Grosbach 89a12be8bb Remove test file. Superceded by other more exhaustive tests. 
llvm-svn: 138777
 2011-08-29 23:00:19 +00:00
Jim Grosbach ed16ec4248 Thumb2 parsing and encoding for IT blocks. 
llvm-svn: 138773
 2011-08-29 22:24:09 +00:00
Kevin Enderby 7e2489a7c9 Fix the disassembly of the X86 crc32 instruction. Bug 10702 and rdar://8795217 
llvm-svn: 138771
 2011-08-29 22:06:28 +00:00
Eli Friedman 850b9a9a84 Explicitly zero out parts of a vector which are required to be zero by the algorithm in LowerUINT_TO_FP_i32. This only has a substantial effect on the generated code when the input is extracted from a vector register; other ways of loading an i32 do the appropriate zeroing implicitly. Fixes PR10802. 
llvm-svn: 138768
 2011-08-29 21:15:46 +00:00
Bill Wendling e79ce47ad7 Update tests to new EH model. Add landingpad instructions to landing pads. 
llvm-svn: 138759
 2011-08-29 20:39:23 +00:00
Nadav Rotem 5fc81ffbac Fixes following the CR by Chris and Duncan: 
Optimize chained bitcasts of the form A->B->A.
Undo r138722 and change isEliminableCastPair to allow this case.

llvm-svn: 138756
 2011-08-29 19:58:36 +00:00
Owen Anderson 967674d26c Improve handling of #-0 offsets for many more pre-indexed addressing modes. 
llvm-svn: 138754
 2011-08-29 19:36:44 +00:00
Owen Anderson baa7edb06a Add testcase for r138746. 
llvm-svn: 138747
 2011-08-29 18:02:40 +00:00
Owen Anderson f02d98d7c0 Add support for parsing #-0 on non-memory-operand immediate values, and add a testcase that necessitates it. 
llvm-svn: 138739
 2011-08-29 17:17:09 +00:00
Duncan Sands 4d63542b82 Fix PR5329: pay attention to constructor/destructor priority 
when outputting them.  With this, the entire LLVM testsuite
passes when built with dragonegg.

llvm-svn: 138724
 2011-08-28 13:17:22 +00:00
Nadav Rotem 52600ee8c3 Bitcasts are transitive. Bitcast-Bitcast-X becomes Bitcast-X. 
llvm-svn: 138722
 2011-08-28 11:51:08 +00:00
Andrew Trick d22f9b395b Reverted r138652, valgrind doesn't understand obj:*/tblgen. 
llvm-svn: 138703
 2011-08-27 06:17:30 +00:00
Bill Wendling ba198e661e Auto upgrade the old EH scheme to use the new one. This is on a trial basis. If 
things to disasterously over night, this can be reverted.

llvm-svn: 138702
 2011-08-27 06:11:03 +00:00
Bill Wendling 2f92d2cdae Update to new EH scheme. 
llvm-svn: 138699
 2011-08-27 04:53:41 +00:00
Bill Wendling 46c720994a Cannot have an llvm.eh.exception call in a non-landing pad block. 
llvm-svn: 138698
 2011-08-27 04:53:28 +00:00
Andrew Trick 4f3cb540a6 Excluding ARM JIT tests until someone can fix this compilation path. 
llvm-svn: 138676
 2011-08-26 23:39:30 +00:00
Owen Anderson b205c029a4 Improve encoding support for BLX with immediat eoperands, and fix a BLX decoding bug this uncovered. 
llvm-svn: 138675
 2011-08-26 23:32:08 +00:00
Owen Anderson 6c70e58041 Correct encoding of BL with immediate offset. 
llvm-svn: 138673
 2011-08-26 22:54:51 +00:00
Eli Friedman 5e5704277f Add support for generating CMPXCHG16B on x86-64 for the cmpxchg IR instruction. 
llvm-svn: 138660
 2011-08-26 21:21:21 +00:00
Bill Wendling ac88ab7cce Revert r138606 until LowerInvoke has been converted to the new EH scheme. 
llvm-svn: 138656
 2011-08-26 21:11:23 +00:00
Owen Anderson 16d33f36d5 invalid-LDR_PRE-arm.txt was already passing, but for the wrong reasons. We were failing to specify enough fixed bits of LDR_PRE/LDRB_PRE, resulting in decoding conflicts. Separate them into immediate vs. register versions, allowing us to specify the necessary fixed bits. This in turn results in the test being decoded properly, and being rejected as UNPREDICTABLE rather than a hard failure. 
llvm-svn: 138653
 2011-08-26 20:43:14 +00:00
Andrew Trick 28dc5abd05 valgrind: Always suppress tblgen leaks. 
I'll clean up the rest of the XFAIL: vg_leak lines if this works.

llvm-svn: 138652
 2011-08-26 20:41:20 +00:00
Bill Wendling eed1e8905a Don't sink landingpad instructions during ind-var simplification. 
llvm-svn: 138651
 2011-08-26 20:40:15 +00:00
Andrew Trick 07aeb629ec Use %% for literals in RUN lines. 
llvm-svn: 138647
 2011-08-26 20:09:48 +00:00
Owen Anderson a01bcbfc80 Support an extension of ARM asm syntax to allow immediate operands to ADR instructions. This is helpful for disassembler testing, and indeed exposed a disassembler bug that is also fixed here. 
llvm-svn: 138635
 2011-08-26 18:09:22 +00:00
Benjamin Kramer 6eb9666bb8 We don't care if TableGen leaks memory. 
llvm-svn: 138634
 2011-08-26 17:00:30 +00:00
Owen Anderson f3b6507e26 Add a testcase for r138625. 
llvm-svn: 138626
 2011-08-26 06:45:08 +00:00
Craig Topper c66d50d1a2 Fix disassembling of VCVTSD2SI 
llvm-svn: 138623
 2011-08-26 04:49:29 +00:00
Eli Friedman 452aae6202 Atomic load/store on ARM/Thumb. 
I don't really like the patterns, but I'm having trouble coming up with a
better way to handle them.

I plan on making other targets use the same legalization
ARM-without-memory-barriers is using... it's not especially efficient, but
if anyone cares, it's not that hard to fix for a given target if there's
some better lowering.

llvm-svn: 138621
 2011-08-26 02:59:24 +00:00
Benjamin Kramer fb212a6309 SimplifyCFG: If we have a PHI node that can evaluate to NULL and do a load or store to the address returned by the PHI node then we can consider this incoming value as dead and remove the edge pointing there, unless there are instructions that can affect control flow executed in between. 
In theory this could be extended to other instructions, eg. division by zero, but it's likely that it will "miscompile" some code because people depend on div by zero not trapping. NULL pointer dereference usually leads to a crash so we should be on the safe side.

This shrinks the size of a Release clang by 16k on x86_64.

llvm-svn: 138618
 2011-08-26 01:22:29 +00:00
Bill Wendling 62fe9e9aa6 Update to the new EH scheme. 
llvm-svn: 138606
 2011-08-25 23:48:37 +00:00
Bruno Cardoso Lopes 8347b86293 Add support for AVX 256-bit version of MOVDDUP! 
llvm-svn: 138588
 2011-08-25 21:40:37 +00:00
Owen Anderson 5e30972cff Port over additional encoding tests to decoding tests, and fix an operand ordering bug this exposed. 
llvm-svn: 138575
 2011-08-25 18:30:18 +00:00
Andrew Trick 6446bf780a ARM fix for missing implicit operands on ldmia_ret. 
rdar://10005094: miscompile of 176.gcc

llvm-svn: 138568
 2011-08-25 17:50:53 +00:00
Craig Topper 76e3e0b554 Give ATTR_VEX higher priority when generating the disassembler context table. Fixes disassembling of VEX instructions with 'pp'=00. Fixes subset of PR10678. 
llvm-svn: 138552
 2011-08-25 07:42:00 +00:00
Craig Topper e1541838f9 Add TB encoding to VEROALL, VZEROUPPER, and VCVTPS2PD to allow them to be disassembled. Fixes PR10723. 
llvm-svn: 138551
 2011-08-25 06:57:46 +00:00
Bill Wendling 3fb137f7ef LSR wants to split the landing pad's critical edge. Let it do it, but use the 
proper function to do it.

llvm-svn: 138550
 2011-08-25 05:55:40 +00:00
Bruno Cardoso Lopes 296256fb32 Add support for 256-bit versions of VSHUFPD and VSHUFPS. 
llvm-svn: 138546
 2011-08-25 02:58:26 +00:00
Bill Wendling ff2091737e Update tests to the newest EH syntax. 
llvm-svn: 138541
 2011-08-25 01:30:18 +00:00
Bill Wendling b37db20e40 Add feature test for the new exception handling stuff. 
llvm-svn: 138539
 2011-08-25 01:19:13 +00:00
Eli Friedman 9c73a57b20 Hook up 64-bit atomic load/store on x86-32. I plan to write more efficient implementations eventually. 
llvm-svn: 138505
 2011-08-24 22:33:28 +00:00
Evan Cheng eee864520c Some autoconf tests use module level inline asm to test compiler's handling of 
.cfi_startproc. e.g. libffi:

 $ cat confopt.c 
asm (".cfi_startproc\n\t.cfi_endproc");

int main () { return 0; }

Teach MC / dwarf emission to handle these cfi directives which essentially
create an empty frame.

rdar://10017184

llvm-svn: 138504
 2011-08-24 22:31:37 +00:00
Jim Grosbach b2a2c031b8 Update tests for 138501. 
llvm-svn: 138502
 2011-08-24 22:30:18 +00:00
Jim Grosbach 4b701af908 Thumb parsing and encoding for SUB (SP minu immediate). 
Fix FiXME in test file. Remove FIXME for SUB (SP minus register) since that
form is Thumb2 only.

llvm-svn: 138494
 2011-08-24 21:42:27 +00:00