We check the address of the last element accessed, but with 0 calculating that
address results in element -1. This patch bails out early (and avoids a bunch
of other work at that).
Fixes PR12807.
llvm-svn: 156769
Returning a temporary BitVector is very expensive. If you must, create
the temporary explicitly: Use BitVector(A).flip() instead of ~A.
llvm-svn: 156768
These operators were crazy slow, calling malloc to return a temporary
result. At the same time, they look very innocent when used in code.
If you need temporary BitVectors to compute your thing, create them
explicitly, and use the inplace logical operators. This makes the high
cost explicit in the code.
llvm-svn: 156767
Register units can be used to compute if two registers overlap:
A overlaps B iff units(A) intersects units(B).
With this change, the above holds true even on targets that use ad hoc
aliasing (currently only ARM). This means that register units can be
used to implement regsOverlap() more efficiently, and the register
allocator can use the concept to model interference.
When there is no ad hoc aliasing, the register units correspond to the
maximal cliques in the register overlap graph. This is optimal, no other
register unit assignment can have fewer units.
With ad hoc aliasing, weird things are possible, and we don't try too
hard to compute the maximal cliques. The current approach is always
correct, and it works very well (probably optimally) as long as the ad
hoc aliasing doesn't have cliques larger than pairs. It seems unlikely
that any target would need more.
llvm-svn: 156763
The ad hoc aliasing specified in the 'Aliases' list in .td files is
currently only used by computeOverlaps(). It will soon be needed to
build accurate register units as well, so build the undirected graph in
CodeGenRegister::buildObjectGraph() instead.
Aliasing is a symmetric relationship with only one direction specified
in the .td files. Make sure both directions are represented in
getExplicitAliases().
llvm-svn: 156762
TableGen creates new register classes and sub-register indices based on
the sub-register structure present in the register bank. So far, it has
been doing that on a per-register basis, but that is not very efficient.
This patch teaches TableGen to compute topological signatures for
registers, and use that to reduce the amount of redundant computation.
Registers get the same TopoSig if they have identical sub-register
structure.
TopoSigs are not currently exposed outside TableGen.
llvm-svn: 156761
Collect info about all dynamic libraries in the process (name, base, size).
Determine to what dyn lib the address relates, route request to addr2line instance for the lib.
llvm-svn: 156759
Races on stack of main thread are problematic for COMPAT mapping, because it's not 1-to-1 and race addr is not properly mapped from shadow back to application memory.
Update output tests to race heap memory.
llvm-svn: 156758
Currently cold functions are marked with the "optsize" attribute in CodeGen
so they are always optimized for size. The hot attribute is just ignored,
LLVM doesn't have a way to express hotness at the moment.
llvm-svn: 156723
* Document index argument in TranslationUnit.from_source
* Add numeric error code to TranslationUnitSaveError string representation
* Use None instead of [] for default argument value in
TranslationUnit.codeComplete
llvm-svn: 156722
Once we've found a "good" method, we don't need to check its argument types
again. (Even if we might have later found a "bad" method, we were already
caching the method we first looked up.)
llvm-svn: 156719
Chandler Carruth