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127 Commits

Author SHA1 Message Date
Colin LeMahieu 1445553474 [Hexagon] Adding dealloc_return encoding and absolute address stores. 
llvm-svn: 225267
 2015-01-06 16:15:15 +00:00
Colin LeMahieu dacf057bdc [Hexagon] Adding add/sub with carry, logical shift left by immediate and memop instructions. Removing old defs without bits and updating references. 
llvm-svn: 225210
 2015-01-05 21:36:38 +00:00
Craig Topper d3c02f177a Replace several 'assert(false' with 'llvm_unreachable' or fold a condition into the assert. 
llvm-svn: 225160
 2015-01-05 10:15:49 +00:00
Colin LeMahieu 9014890819 [Hexagon] Removing old newvalue store variants. Adding postincrement immediate newvalue stores. 
llvm-svn: 225009
 2014-12-30 22:28:31 +00:00
Colin LeMahieu 820d5cb608 [Hexagon] Adding indexed store new-value variants. 
llvm-svn: 225007
 2014-12-30 22:00:26 +00:00
Colin LeMahieu 2bad4a7177 [Hexagon] Adding indexed store of immediates. 
llvm-svn: 225006
 2014-12-30 21:01:38 +00:00
Colin LeMahieu 94a498bf0e [Hexagon] Adding indexed stores. 
llvm-svn: 225005
 2014-12-30 20:42:23 +00:00
Colin LeMahieu 9161d47476 [Hexagon] Adding reg-reg indexed load forms. 
llvm-svn: 224997
 2014-12-30 18:58:47 +00:00
Colin LeMahieu bda31b42a0 [Hexagon] Adding post-increment register form stores and register-immediate form stores with tests. 
llvm-svn: 224952
 2014-12-29 20:44:51 +00:00
Colin LeMahieu 9a3cd3f58c [Hexagon] Replacing the remaining postincrement stores with versions that have encoding bits. 
llvm-svn: 224951
 2014-12-29 20:00:43 +00:00
Colin LeMahieu 3d34afb32d [Hexagon] Renaming old multiclass for removal. Adding post-increment store classes and instruction defs. 
llvm-svn: 224949
 2014-12-29 19:42:14 +00:00
Colin LeMahieu c83cbbf6a1 [Hexagon] Adding remaining post-increment instruction variants. Removing unused classes. 
llvm-svn: 224868
 2014-12-26 19:31:46 +00:00
Colin LeMahieu fe9612e09d [Hexagon] Adding post-increment unsigned byte loads. 
llvm-svn: 224867
 2014-12-26 19:12:11 +00:00
Colin LeMahieu 96976a10a3 [Hexagon] Adding post-increment signed byte loads with tests. 
llvm-svn: 224866
 2014-12-26 18:57:13 +00:00
Colin LeMahieu 947cd70413 [Hexagon] Adding doubleword load. 
llvm-svn: 224787
 2014-12-23 20:44:59 +00:00
Colin LeMahieu 026e88d317 [Hexagon] Reapplying 224775 load words. 
llvm-svn: 224786
 2014-12-23 20:02:16 +00:00
Colin LeMahieu 20be15718b Reverting 224775 until mayLoad flag is addressed. 
llvm-svn: 224783
 2014-12-23 19:22:59 +00:00
Colin LeMahieu 122aeaafea [Hexagon] Adding word loads. 
llvm-svn: 224775
 2014-12-23 18:06:56 +00:00
Colin LeMahieu 8e39cad934 [Hexagon] Adding signed halfword loads. 
llvm-svn: 224774
 2014-12-23 17:25:57 +00:00
Colin LeMahieu a9386d28a5 [Hexagon] Adding unsigned halfword load. 
llvm-svn: 224772
 2014-12-23 16:42:57 +00:00
Colin LeMahieu 4b1eac4dda [Hexagon] Adding memb instruction. Fixing whitespace in test from 224730. 
llvm-svn: 224735
 2014-12-22 21:40:43 +00:00
Colin LeMahieu af1e5de141 [Hexagon] Adding classes and load unsigned byte instruction, updating usages. 
llvm-svn: 224730
 2014-12-22 21:20:03 +00:00
Colin LeMahieu 0f850bde0e [Hexagon] Removing old variants of instructions and updating references. 
llvm-svn: 224612
 2014-12-19 20:29:29 +00:00
Colin LeMahieu 402f772b82 [Hexagon] Adding doubleregs for control registers. Renaming control register class. 
llvm-svn: 224598
 2014-12-19 18:56:10 +00:00
Colin LeMahieu 5ccbb1298b [Hexagon] Adding loop0/1 sp0/1/2loop0 instructions. 
llvm-svn: 224556
 2014-12-19 00:06:53 +00:00
Colin LeMahieu 174476ed96 Reverting 224550, was not ready for commit. 
llvm-svn: 224552
 2014-12-18 23:36:15 +00:00
Colin LeMahieu 9000481cda [Hexagon] Adding loop0/1 sp0/1/2loop0 instructions. 
llvm-svn: 224550
 2014-12-18 23:27:51 +00:00
Colin LeMahieu db0b13cef0 [Hexagon] Adding encodings for JR class instructions. Updating complier usages. 
llvm-svn: 223967
 2014-12-10 21:24:10 +00:00
Colin LeMahieu 4af437fee5 [Hexagon] Updating rr/ri 32/64 transfer encodings and adding tests. 
llvm-svn: 223821
 2014-12-09 20:23:30 +00:00
Colin LeMahieu b580d7d8c8 [Hexagon] Adding word combine dot-new form and replacing old combine opcode. 
llvm-svn: 223815
 2014-12-09 19:23:45 +00:00
Colin LeMahieu 30dcb232b0 [Hexagon] Updating predicate register transfers and adding tstbit to allow select selection. Updating ll tests with predicate transfers that previously had nop encodings. 
llvm-svn: 223800
 2014-12-09 18:16:49 +00:00
Colin LeMahieu 5cf5632696 [Hexagon] Removing old def versions and replacing usages with versions that have encodings. 
llvm-svn: 223720
 2014-12-08 23:55:43 +00:00
Colin LeMahieu 9bfe5473da [Hexagon] Adding xtype doubleword comparisons. Removing unused multiclass. 
llvm-svn: 223701
 2014-12-08 21:56:47 +00:00
Colin LeMahieu 6e0f9f8d61 [Hexagon] Adding cmp* immediate form instructions. 
llvm-svn: 222849
 2014-11-26 19:43:12 +00:00
Colin LeMahieu 902157c249 [Hexagon] Replacing cmp* instructions with ones that contain encoding bits. 
llvm-svn: 222771
 2014-11-25 18:20:52 +00:00
Colin LeMahieu 287c4e1762 Removing unused variable. 
llvm-svn: 222676
 2014-11-24 18:55:32 +00:00
Colin LeMahieu 397a25e7cd [Hexagon] Adding asrh instruction, removing unused multiclasses. 
llvm-svn: 222670
 2014-11-24 18:04:42 +00:00
Colin LeMahieu 3b3197ef95 [Hexagon] Adding aslh instruction. 
llvm-svn: 222668
 2014-11-24 17:44:19 +00:00
Colin LeMahieu 098256c5e6 [Hexagon] Adding zxth instruction. 
llvm-svn: 222662
 2014-11-24 17:11:34 +00:00
Colin LeMahieu bb7d6f5514 [Hexagon] Adding zxtb instruction. 
llvm-svn: 222660
 2014-11-24 16:48:43 +00:00
Colin LeMahieu 310991c66f [Hexagon] Adding sxth instruction. 
llvm-svn: 222577
 2014-11-21 21:54:59 +00:00
Colin LeMahieu 91ffec908f [Hexagon] Adding sxtb instruction. Renaming some identically named classes that will be removed after converting referencing defs. 
llvm-svn: 222575
 2014-11-21 21:35:52 +00:00
Colin LeMahieu e88447d8de [Hexagon] Removing SUB_rr and replacing with A2_sub. 
llvm-svn: 222571
 2014-11-21 21:19:18 +00:00
Colin LeMahieu ac00643603 [Hexagon] Adding A2_xor instruction with IR selection pattern and test. 
llvm-svn: 222399
 2014-11-19 23:22:23 +00:00
Colin LeMahieu 21866546ae [Hexagon] Adding A2_or instruction with IR selection pattern and test. 
llvm-svn: 222396
 2014-11-19 22:58:04 +00:00
Colin LeMahieu 44fd1c8bdf [Hexagon] Adding A2_and instruction. 
llvm-svn: 222274
 2014-11-18 22:45:47 +00:00
Colin LeMahieu efa74e0280 [Hexagon] Converting from ADD_rr to A2_add which has encoding bits. 
Adding test to show correct instruction selection and encoding.

llvm-svn: 222249
 2014-11-18 20:28:11 +00:00
Eric Christopher 143f02c47d Remove unused argument to CreateTargetScheduleState and change 
the TargetMachine to a TargetSubtargetInfo since everything
we wanted is off of that.

llvm-svn: 219382
 2014-10-09 01:59:35 +00:00
Alexey Samsonov 2651ae6513 Fix undefined behavior (left shift of negative value) in Hexagon backend. 
This bug is reported by UBSan.

llvm-svn: 216125
 2014-08-20 21:22:03 +00:00
Eric Christopher d913448b38 Remove the TargetMachine forwards for TargetSubtargetInfo based 
information and update all callers. No functional change.

llvm-svn: 214781
 2014-08-04 21:25:23 +00:00