20c9e4cbee
Add new CC lowering rule: provide a list of registers, which can be 'shadowed',
...
when some another register is used for argument passing.
Currently is used on Win64.
llvm-svn: 49079
2008-04-02 05:23:57 +00:00
fd967cf3fa
Recommitting EH patch; this should answer most of the
...
review feedback.
-enable-eh is still accepted but doesn't do anything.
EH intrinsics use Dwarf EH if the target supports that,
and are handled by LowerInvoke otherwise.
The separation of the EH table and frame move data is,
I think, logically figured out, but either one still
causes full EH info to be generated (not sure how to
split the metadata correctly).
MachineModuleInfo::needsFrameInfo is no longer used and
is removed.
llvm-svn: 49064
2008-04-02 00:25:04 +00:00
b86595fb0a
ReMat of load from stub in pic mode extends the life of pic base. Currently spiller doesn't do a good job of estimating the impact. Disable for now.
...
llvm-svn: 49059
2008-04-01 23:26:12 +00:00
19a6dd9f2a
Remove unnecessary and non-deterministic checking code. Re-enable remat of load from gv stub.
...
llvm-svn: 49054
2008-04-01 21:38:20 +00:00
cb9f8f6e4e
Don't use __bzero for memset if the second argument isn't zero.
...
llvm-svn: 49050
2008-04-01 20:56:18 +00:00
980d7200c1
Speculatively micro-optimize memory-zeroing calls on Darwin 10.
...
llvm-svn: 49048
2008-04-01 20:38:36 +00:00
5e4e051c2a
Revert 49006 for the moment.
...
llvm-svn: 49046
2008-04-01 20:00:57 +00:00
306e3dcff4
Disabling remat of load from gv stub (temporarily) again to fix llvmgcc bootstrap miscompare.
...
llvm-svn: 49037
2008-04-01 07:33:13 +00:00
86e476b7cb
Unbreak ARM / Thumb soft FP support.
...
llvm-svn: 49012
2008-04-01 01:50:16 +00:00
efa81a6979
Accept 'y' constraint (MMX) in inline asm.
...
llvm-svn: 49011
2008-04-01 00:57:48 +00:00
7d02cf3c9c
Emit exception handling info for functions which are
...
not marked nounwind, or for all functions when -enable-eh
is set, provided the target supports Dwarf EH.
llvm-gcc generates nounwind in the right places; other FEs
will need to do so also. Given such a FE, -enable-eh should
no longer be needed.
llvm-svn: 49006
2008-03-31 23:40:23 +00:00
e4f77c69ac
It's not safe to fold a load from GV stub or constantpool into a two-address use.
...
llvm-svn: 49002
2008-03-31 23:19:51 +00:00
ed6e34fe41
Move reMaterialize() from TargetRegisterInfo to TargetInstrInfo.
...
llvm-svn: 48995
2008-03-31 20:40:39 +00:00
1973a46cd3
Re-apply 48911.
...
llvm-svn: 48977
2008-03-31 07:54:19 +00:00
9fb8908457
Moved from PR1570.
...
llvm-svn: 48965
2008-03-30 19:07:11 +00:00
0f760dfe09
Fix "Control reaches the end of non-void function" warnings,
...
patch by David Chisnall.
llvm-svn: 48963
2008-03-30 18:22:13 +00:00
fd2eb00cc2
Fix a tokenfactor node to use the load chain rather than the
...
load value. This fixes PR2177.
llvm-svn: 48932
2008-03-28 23:45:16 +00:00
b8654202dd
Backing out 48911 for now. It's breaking stuff.
...
llvm-svn: 48922
2008-03-28 17:49:06 +00:00
81e0c9a32c
New entry.
...
llvm-svn: 48912
2008-03-28 07:07:06 +00:00
9ae4d7b719
Load from stub is already re-materializable.
...
llvm-svn: 48911
2008-03-28 06:49:25 +00:00
308e564693
Code clean up.
...
llvm-svn: 48856
2008-03-27 01:45:11 +00:00
29e62a59f3
Allow certain lea instructions to be rematerialized.
...
llvm-svn: 48855
2008-03-27 01:41:09 +00:00
4fb07c6500
Remove an unused command line option.
...
llvm-svn: 48854
2008-03-27 01:30:24 +00:00
358e04a185
Use a linked data structure for the uses lists of an SDNode, just like
...
LLVM Value/Use does and MachineRegisterInfo/MachineOperand does.
This allows constant time for all uses list maintenance operations.
The idea was suggested by Chris. Reviewed by Evan and Dan.
Patch is tested and approved by Dan.
On normal use-cases compilation speed is not affected. On very big basic
blocks there are compilation speedups in the range of 15-20% or even better.
llvm-svn: 48822
2008-03-26 12:39:26 +00:00
292063603e
Fix some SSE4.1 instruction encoding bugs.
...
llvm-svn: 48815
2008-03-26 08:11:49 +00:00
ad6c23d5e9
Use ## for comment delimiter on darwin x86-32, so
...
llvm's output .s files will go through gcc -std=c99
without triggering preprocesser errors. Approach
suggested by Daveed Vandevoorde.
llvm-svn: 48808
2008-03-25 23:29:30 +00:00
ddc58ff92a
Smaller function alignment when optimizing for size.
...
llvm-svn: 48805
2008-03-25 22:29:46 +00:00
88c44ef91f
Rename option -optimizefor-size to -optimize-size.
...
llvm-svn: 48804
2008-03-25 22:28:39 +00:00
c60c67fc37
Add explicit keywords.
...
llvm-svn: 48801
2008-03-25 22:06:05 +00:00
bdc24adaaf
A quick nm audit turned up several fixed tables and objects that were
...
marked read-write. Use const so that they can be allocated in a
read-only segment.
llvm-svn: 48800
2008-03-25 21:45:14 +00:00
246a52740b
Add optimize-for-size knob.
...
llvm-svn: 48793
2008-03-25 21:02:35 +00:00
883cbfd0ba
Add CMP32mr and friends to the load-unfolding table. Among
...
other things, this allows the scheduler to unfold a load operand
in the 2008-01-08-SchedulerCrash.ll testcase, so it now successfully
clones the comparison to avoid a pushf+popf.
llvm-svn: 48777
2008-03-25 16:53:19 +00:00
50b536eef9
Add \t after .set. Fix by Jay Freeman.
...
llvm-svn: 48753
2008-03-24 23:36:49 +00:00
6306183df3
Use the bit size of the operand instead of the hard-coded 32 to generate the
...
mask.
llvm-svn: 48750
2008-03-24 23:16:37 +00:00
615488ab45
- SSE4.1 extractfps extracts a f32 into a gr32 register. Very useful! Not. Fix the instruction specification and teaches lowering code to use it only when the only use is a store instruction.
...
llvm-svn: 48746
2008-03-24 21:52:23 +00:00
58db865d6e
Remove duplicated entries.
...
llvm-svn: 48714
2008-03-23 22:56:07 +00:00
1fdd5e9133
Minor typo fixes. Also add another FIXME.
...
llvm-svn: 48710
2008-03-23 20:32:06 +00:00
17fb491469
Add license header
...
llvm-svn: 48707
2008-03-23 14:53:18 +00:00
9f0e820fa3
Add Win64 compilation callback. This allows easy examples to be JITed on Win64!
...
llvm-svn: 48706
2008-03-23 14:44:32 +00:00
a347663762
Provide a JIT selector on win64
...
llvm-svn: 48704
2008-03-23 13:43:47 +00:00
7574ead985
Hack out the PIC mode on Win64 targets. This needs to be investigated later.
...
llvm-svn: 48703
2008-03-23 13:41:18 +00:00
4733e72a25
Code cleanup. Provide generic way of selecting JIT pointer bitwidth regardless
...
of compiler used.
llvm-svn: 48702
2008-03-23 13:40:45 +00:00
bd47269f13
Remove old-standing obsolete code.
...
llvm-svn: 48701
2008-03-23 12:32:54 +00:00
cec773d8e7
Honour built-in defines on win64 targets for automatically subtarget recognize.
...
Force stack alignment to 16 bytes on win targets.
llvm-svn: 48695
2008-03-22 21:18:22 +00:00
07a789d2b5
Recognize "windows" in target triple, not only "win32"
...
llvm-svn: 48694
2008-03-22 21:12:53 +00:00
b86e0936f1
Add information about callee-saved registers on Win64
...
llvm-svn: 48692
2008-03-22 21:04:01 +00:00
7f125b2ba5
Add convenient helper for win64 check. Simplify things slightly.
...
llvm-svn: 48691
2008-03-22 20:57:27 +00:00
7b4f4e1a86
Initial support for Win64 calling conventions. Still in early state.
...
llvm-svn: 48690
2008-03-22 20:37:30 +00:00
2fa75184f3
Another comments fixing
...
llvm-svn: 48683
2008-03-22 07:53:40 +00:00
c55b444a8f
Restore this assert now that the livevar bug is fixed.
...
This verifies kill info for "ret" fp operands is right.
llvm-svn: 48656
2008-03-21 20:41:27 +00:00
d97eea372a
Introduce a new node for holding call argument
...
flags. This is needed by the new legalize types
infrastructure which wants to expand the 64 bit
constants previously used to hold the flags on
32 bit machines. There are two functional changes:
(1) in LowerArguments, if a parameter has the zext
attribute set then that is marked in the flags;
before it was being ignored; (2) PPC had some bogus
code for handling two word arguments when using the
ELF 32 ABI, which was hard to convert because of
the bogusness. As suggested by the original author
(Nicolas Geoffray), I've disabled it for the moment.
Tested with "make check" and the Ada ACATS testsuite.
llvm-svn: 48640
2008-03-21 09:14:45 +00:00
68b11e14bc
remove Evan's "ugly hack" that sorta attempted to get
...
x86-64 return conventions correct, but was never enabled.
We can now do the "right thing" with multiple return values.
llvm-svn: 48635
2008-03-21 06:50:21 +00:00
5abbe6cef5
Add support for calls that return two FP values in
...
ST(0)/ST(1).
llvm-svn: 48634
2008-03-21 06:38:26 +00:00
7e59a30e9f
disable a bogus assertion.
...
llvm-svn: 48633
2008-03-21 06:01:05 +00:00
b6f04a3e0a
Enable support for returning two long-double values in ST(0)/ST(1).
...
This allows us to compile fp-stack-2results.ll into:
_test:
fldz
fld1
ret
which returns 1 in ST(0) and 0 in ST(1). This is needed for x86-64
_Complex long double.
llvm-svn: 48632
2008-03-21 05:57:20 +00:00
92b4488202
Undo 48570. Correctly match mmx shift instructions with an immediate operand.
...
llvm-svn: 48627
2008-03-21 00:40:09 +00:00
fd5fe2a83d
add a note.
...
llvm-svn: 48583
2008-03-20 04:46:13 +00:00
7a3e750fd2
Fix this xform: (sra (shl X, m), result_size) -> (sign_extend (trunc (shl X, result_size - n - m)))
...
llvm-svn: 48578
2008-03-20 02:18:41 +00:00
a7cca362af
detabify llvm, patch by Mike Stump!
...
llvm-svn: 48577
2008-03-20 01:22:40 +00:00
bbaf3edace
Add more patterns to match in the integer comparison test harnesses.
...
Fix bugs encountered, mostly due to range matching for immediates;
the CellSPU's 10-bit immediates are sign extended, covering a
larger range of unsigned values.
llvm-svn: 48575
2008-03-20 00:51:36 +00:00
bbba76fc99
Add intrinsics to match mmx shift builtin's with immediate operand.
...
llvm-svn: 48569
2008-03-19 23:38:52 +00:00
718da668ab
PassInfo keep tracks whether a pass is an analysis pass or not.
...
llvm-svn: 48554
2008-03-19 21:56:59 +00:00
b9056838d2
Add support for multiple return values for the PPC target by
...
converting call result lowering to use the CallingConvLowering
infastructure.
llvm-svn: 48552
2008-03-19 21:39:28 +00:00
7da2bceb3b
Don't loose incoming argument registers. Fix documentation style.
...
llvm-svn: 48545
2008-03-19 16:39:45 +00:00
8fe9109469
Fix X86's isTruncateFree to not claim that truncate to i1 is free. This fixes Bill's testcase that failed for r48491.
...
llvm-svn: 48542
2008-03-19 08:30:06 +00:00
2f6ab65d77
On Darwin, GCC issues a ".globl" for something that has a "visibility protected"
...
attribute instead of ".protected".
llvm-svn: 48516
2008-03-18 23:38:12 +00:00
484064370a
Fix a x86-64 isel lowering bug that's been around forever. A x86-64 varargs function implicitly reads X86::AL, don't clobber it!
...
llvm-svn: 48515
2008-03-18 23:36:35 +00:00
cf87e71053
Make Complex long long/double/long double work
...
in ppc64 mode.
llvm-svn: 48459
2008-03-17 17:11:08 +00:00
7d4152bda6
Check in some #ifdef'd out code switching call argument
...
lowering over to SparcCallingConv.td. We can't make the switch
yet because we can't say to pass f64 registers in 2 x i32 registers
with the td file yet.
llvm-svn: 48449
2008-03-17 06:58:37 +00:00
52f16deb65
minor cleanups
...
llvm-svn: 48448
2008-03-17 06:57:02 +00:00
24bc123e80
Unbreak JIT. Ignore TargetInstrInfo::IMPLICIT_DEF.
...
llvm-svn: 48447
2008-03-17 06:56:52 +00:00
4eabbb8f11
remove dead code
...
llvm-svn: 48445
2008-03-17 06:04:10 +00:00
db26db2158
Switch sparc from using LowerCallTo to using LowerOperation(CALL) like
...
other targets. Use autogenerated calling conv to lower result of
calls.
llvm-svn: 48444
2008-03-17 06:01:07 +00:00
49b269d780
Start moving sparc to use SparcCallingConv.td, switching over
...
return lowering first. This fixes a bug where the top and bottom
of i64 values were returned in the wrong registers before.
llvm-svn: 48443
2008-03-17 05:41:48 +00:00
0a1762e374
split sparc lowering out into SparcISelLowering.{cpp|h} to follow
...
best practices.
llvm-svn: 48442
2008-03-17 03:21:36 +00:00
5c5597a572
refactor the LowerOperation code out to individual functions for
...
each lowering, which is 'best practice'.
llvm-svn: 48441
2008-03-17 02:52:07 +00:00
92dcf1e0c2
Next round of PPC32 ABI changes. Allow for gcc
...
behavior where a callee thinks a param will be
present in memory, even though the ABI doc says
it doesn't have to be. Handle complex long long
and complex double (4 and 8 return regs).
llvm-svn: 48439
2008-03-17 02:13:43 +00:00
af8d3c6699
various rotate fun.
...
llvm-svn: 48438
2008-03-17 01:47:51 +00:00
9030ecec88
Add a couple missing SSE4 instructions
...
llvm-svn: 48430
2008-03-16 21:14:46 +00:00
ab4b7d36cd
C and Objective Caml bindings for the TargetData class.
...
llvm-svn: 48422
2008-03-16 20:08:03 +00:00
d3d0ad3f58
Make insert_subreg a two-address instruction, vastly simplifying LowerSubregs pass. Add a new TII, subreg_to_reg, which is like insert_subreg except that it takes an immediate implicit value to insert into rather than a register.
...
llvm-svn: 48412
2008-03-16 03:12:01 +00:00
ec7533b620
Remove isImplicitDef TargetInstrDesc flag.
...
llvm-svn: 48381
2008-03-15 00:19:36 +00:00
0e7b00d79f
Replace all target specific implicit def instructions with a target independent one: TargetInstrInfo::IMPLICIT_DEF.
...
llvm-svn: 48380
2008-03-15 00:03:38 +00:00
0dfd3f33f7
Implement the real calling convention for ppc32 Altivec:
...
vectors go at the end of the memory area, after all
non-vector parameters.
llvm-svn: 48364
2008-03-14 17:41:26 +00:00
5be52a6053
Fix some 80 col violations.
...
llvm-svn: 48361
2008-03-14 07:46:48 +00:00
96bdbd6c5d
Fix a number of encoding bugs. SSE 4.1 instructions MPSADBWrri, PINSRDrr, etc. have 8-bits immediate field (ImmT == Imm8).
...
llvm-svn: 48360
2008-03-14 07:39:27 +00:00
77c8da7f00
Add debugging stuff.
...
llvm-svn: 48359
2008-03-14 07:13:42 +00:00
477d0f5294
Add an issue that is preventing instcombine from doing a simplification.
...
llvm-svn: 48356
2008-03-14 06:00:19 +00:00
eac0c96371
Use SDTNone instead of duplicating it.
...
llvm-svn: 48346
2008-03-13 23:07:40 +00:00
dd55d3f1b2
Get rid of a pseudo instruction and replace it with subreg based operation on real instructions, ridding the asm printers of the hack used to do this previously. In the process, update LowerSubregs to be careful about eliminating copies that have side affects.
...
Note: the coalescer will have to be careful about this too, when it starts coalescing insert_subreg nodes.
llvm-svn: 48329
2008-03-13 05:47:01 +00:00
6424bd0b11
Do not promote float params to double in varargs
...
calls here. This was done earlier for params in
the varargs part of the params; any float params
that survive to here are in the non-varargs part,
and must not be promoted.
llvm-svn: 48310
2008-03-12 23:40:01 +00:00
8a923e7c28
Reimplement the parameter attributes support, phase #1 . hilights:
...
1. There is now a "PAListPtr" class, which is a smart pointer around
the underlying uniqued parameter attribute list object, and manages
its refcount. It is now impossible to mess up the refcount.
2. PAListPtr is now the main interface to the underlying object, and
the underlying object is now completely opaque.
3. Implementation details like SmallVector and FoldingSet are now no
longer part of the interface.
4. You can create a PAListPtr with an arbitrary sequence of
ParamAttrsWithIndex's, no need to make a SmallVector of a specific
size (you can just use an array or scalar or vector if you wish).
5. All the client code that had to check for a null pointer before
dereferencing the pointer is simplified to just access the
PAListPtr directly.
6. The interfaces for adding attrs to a list and removing them is a
bit simpler.
Phase #2 will rename some stuff (e.g. PAListPtr) and do other less
invasive changes.
llvm-svn: 48289
2008-03-12 17:45:29 +00:00
99ee78ef63
Clean up my own mess.
...
X86 lowering normalize vector 0 to v4i32. However DAGCombine can fold (sub x, x) -> 0 after legalization. It can create a zero vector of a type that's not expected (e.g. v8i16). We don't want to disable the optimization since leaving a (sub x, x) is really bad. Add isel patterns for other types of vector 0 to ensure correctness. It's highly unlikely to happen other than in bugpoint reduced test cases.
llvm-svn: 48279
2008-03-12 07:02:50 +00:00
0d98256c05
One more bit of Altivec parameter passing.
...
llvm-svn: 48269
2008-03-12 00:49:20 +00:00
b28456ef18
Implement Altivec passing to varargs functions on ppc.
...
llvm-svn: 48264
2008-03-12 00:22:17 +00:00
e8fa50f63a
Correctly propagate thread-local flag from aliasee to alias. This fixes PR2137
...
llvm-svn: 48257
2008-03-11 22:38:53 +00:00
24570836b2
Use PassManagerBase instead of FunctionPassManager for functions
...
that merely add passes. This allows them to be used with either
FunctionPassManager or PassManager, or even with a custom new
kind of pass manager.
llvm-svn: 48256
2008-03-11 22:29:46 +00:00
8abed80a69
Implement basic support for the 'f' register class constraint. This basically
...
works, but probably won't if you mix it with 't' or 'u' yet.
llvm-svn: 48243
2008-03-11 19:50:13 +00:00
7b27ccfd5e
coalesce away 80-bit floating point copies.
...
llvm-svn: 48241
2008-03-11 19:30:09 +00:00
7930d8e775
convert a massive if statement to a switch.
...
llvm-svn: 48240
2008-03-11 19:28:17 +00:00
120ad01fcb
start handling the 'f' x87 constraint.
...
llvm-svn: 48239
2008-03-11 19:06:29 +00:00
342e4104d3
Missed part of recommit.
...
llvm-svn: 48224
2008-03-11 10:27:36 +00:00
aa7c2105de
Recommitting parts of r48130. These do not appear to cause the observed failures.
...
llvm-svn: 48223
2008-03-11 10:09:17 +00:00
d85667b89c
If there are multiple register classes that a register belongs to, return the super-class (e.g. on x86, returns GR32, not GR32_).
...
llvm-svn: 48220
2008-03-11 07:54:14 +00:00
e88a625ecd
When the register allocator runs out of registers, spill a physical register around the def's and use's of the interval being allocated to make it possible for the interval to target a register and spill it right away and restore a register for uses. This likely generates terrible code but is before than aborting.
...
llvm-svn: 48218
2008-03-11 07:19:34 +00:00
5b59e372dc
In 32-bit mode, mark 64-bit GPR's as unallocatable.
...
llvm-svn: 48217
2008-03-11 07:16:00 +00:00
a3860a2422
Fix the build on gcc 4.2.
...
llvm-svn: 48212
2008-03-11 05:56:09 +00:00
1bd44363f2
Change the model for FP Stack return to use fp operands on the
...
RET instruction instead of using FpSET_ST0_32. This also generalizes
the code to handling returning of multiple FP results.
llvm-svn: 48209
2008-03-11 03:23:40 +00:00
d6819da453
Generalize ExpandIntToFP to handle the case where the operand is legal
...
and it's the result that requires expansion. This code is a little confusing
because the TargetLoweringInfo tables for [US]INT_TO_FP use the operand type
(the integer type) rather than the result type.
llvm-svn: 48206
2008-03-11 01:59:03 +00:00
a4fa0ad30d
abort with an assert instead of a cerr to get line#
...
llvm-svn: 48199
2008-03-10 23:56:08 +00:00
92275427e5
- Style cleanup in IA64ISelLowering.h: add 'virtual' keyword for consistency.
...
- Add test pattern matching in CellSPU's icmp32.ll test harness
- Fix CellSPU fcmp.ll-generated assert.
llvm-svn: 48197
2008-03-10 23:49:09 +00:00
7362d38391
Don't emit FP_REG_KILL into a block that just returns. Nothing
...
can be live out of the block anyway, so it isn't needed.
llvm-svn: 48192
2008-03-10 23:34:12 +00:00
0fb187f81b
Disable prolog code that aligns the stack when a
...
local object of >16 byte alignment exists. It does not
work and getting it to work is not trivial, as explained
in the comment. This fixes all the remaining ppc32
failures in the struct-layout-1 part of the gcc testsuite.
(gcc does not support this either, and the only way to
get such an object is with __attribute__((aligned)) or
generic vectors; it can't be done in a standard-conforming
program, or with Altivec. So I think disabling it is OK.)
llvm-svn: 48188
2008-03-10 22:59:46 +00:00
c6c48fca74
Change the "enable/disable" mechanism so that we can enable PPC register
...
scavenging for 32-bit and 64-bit separately.
llvm-svn: 48186
2008-03-10 22:49:16 +00:00
4b3a7fa823
Eliminate the FP_GET_ST0/FP_SET_ST0 target-specific dag nodes, just lower to
...
copyfromreg/copytoreg instead.
llvm-svn: 48174
2008-03-10 21:08:41 +00:00
ae2c56d93e
Default ISD::PREFETCH to expand.
...
llvm-svn: 48169
2008-03-10 19:38:10 +00:00
d4e1d9eeb2
Revert 48125, 48126, and 48130 for now to unbreak some x86-64 tests.
...
llvm-svn: 48167
2008-03-10 19:31:26 +00:00
514b3ed536
fix 80 col violations.
...
llvm-svn: 48166
2008-03-10 18:55:53 +00:00
708784ea4f
Stylistic modifications. No functionality changes.
...
llvm-svn: 48158
2008-03-10 17:46:45 +00:00
48e3375544
Integer comparison tests for CellSPU.
...
llvm-svn: 48152
2008-03-10 16:58:52 +00:00
a6729e8666
Give TargetLowering::getSetCCResultType() a parameter so that ISD::SETCC's
...
return ValueType can depend its operands' ValueType.
This is a cosmetic change, no functionality impacted.
llvm-svn: 48145
2008-03-10 15:42:14 +00:00
b1de7a35f9
Add description of individual bits in CR. This fix PR1765.
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llvm-svn: 48143
2008-03-10 14:12:10 +00:00
4ba3f0430b
Allow insert_subreg into implicit, target-specific values.
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Change insert/extract subreg instructions to be able to be used in TableGen patterns.
Use the above features to reimplement an x86-64 pseudo instruction as a pattern.
llvm-svn: 48130
2008-03-10 06:12:08 +00:00
4e622ec86d
Increase ISD::ParamFlags to 64 bits. Increase the ByValSize
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field to 32 bits, thus enabling correct handling of ByVal
structs bigger than 0x1ffff. Abstract interface a bit.
Fixes gcc.c-torture/execute/pr23135.c and
gcc.c-torture/execute/pr28982b.c in gcc testsuite (were ICE'ing
on ppc32, quietly producing wrong code on x86-32.)
llvm-svn: 48122
2008-03-10 02:17:22 +00:00
aed9406bb7
Darwin PPC64 indirect call target goes in X12, not R12. This fixes these
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two regression tests:
test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert.ll
test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert2.ll
llvm-svn: 48120
2008-03-09 20:49:33 +00:00
78e817d7fc
cell really does support cross-regclass moves, because R3 is in lots of different regclasses, and the code is not consistent when it comes to value tracking.
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llvm-svn: 48119
2008-03-09 20:31:11 +00:00
3ba79ed9e8
make sure ar.pfs is in a register class, this fixes test/CodeGen/IA64/ret-0.ll
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llvm-svn: 48118
2008-03-09 20:12:44 +00:00
86829f0ff7
teach X86InstrInfo::copyRegToReg how to copy into ST(0) from
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an RFP register class.
Teach ScheduleDAG how to handle CopyToReg with different src/dst
reg classes.
This allows us to compile trivial inline asms that expect stuff
on the top of x87-fp stack.
llvm-svn: 48107
2008-03-09 09:15:31 +00:00
b79bafcec8
add some code to support cross-register class copying from
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RST -> RFP{32/64/80}. We only handle ST(0) for now.
llvm-svn: 48104
2008-03-09 08:46:19 +00:00
c4c9dde04c
rearrange some code, no functionality change.
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llvm-svn: 48101
2008-03-09 07:58:04 +00:00
459f518703
claim ST(x) registers are 80 bits, which is true. This doesn't affect
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codegen yet because these can't be spilled (they don't exist until after RA).
llvm-svn: 48098
2008-03-09 07:49:01 +00:00
4c869594bc
rename FP_SETRESULT -> FP_SET_ST0
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llvm-svn: 48094
2008-03-09 07:08:44 +00:00
d587e580a6
rename FpGETRESULT32 -> FpGET_ST0_32 etc. Add support for
...
isel'ing value preserving FP roundings from one fp stack reg to another
into a noop, instead of stack traffic.
llvm-svn: 48093
2008-03-09 07:05:32 +00:00
b6387c8a74
Finish implementing a readme entry: when inserting an i64 variable
...
into a vector of zeros or undef, and when the top part is obviously
zero, we can just use movd + shuffle. This allows us to compile
vec_set-B.ll into:
_test3:
movl $1234567, %eax
andl 4(%esp), %eax
movd %eax, %xmm0
ret
instead of:
_test3:
subl $28, %esp
movl $1234567, %eax
andl 32(%esp), %eax
movl %eax, (%esp)
movl $0, 4(%esp)
movq (%esp), %xmm0
addl $28, %esp
ret
llvm-svn: 48090
2008-03-09 05:42:06 +00:00
93930dc28c
add a note
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llvm-svn: 48064
2008-03-09 01:08:22 +00:00
eef374c197
Implement a readme entry, compiling
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#include <xmmintrin.h>
__m128i doload64(short x) {return _mm_set_epi16(0,0,0,0,0,0,0,1);}
into:
movl $1, %eax
movd %eax, %xmm0
ret
instead of a constant pool load.
llvm-svn: 48063
2008-03-09 01:05:04 +00:00
ad58828354
1) Improve comments.
...
2) Don't try to insert an i64 value into the low part of a
vector with movq on an x86-32 target. This allows us to
compile:
__m128i doload64(short x) {return _mm_set_epi16(0,0,0,0,0,0,0,1);}
into:
_doload64:
movaps LCPI1_0, %xmm0
ret
instead of:
_doload64:
subl $28, %esp
movl $0, 4(%esp)
movl $1, (%esp)
movq (%esp), %xmm0
addl $28, %esp
ret
llvm-svn: 48057
2008-03-08 22:59:52 +00:00
8a6ebd23a8
minor simplifications to this code, don't create a dead
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SCALAR_TO_VECTOR on paths that end up not using it.
llvm-svn: 48056
2008-03-08 22:48:29 +00:00
35adf46967
This one looks easy, add a note.
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llvm-svn: 48055
2008-03-08 22:32:39 +00:00
a76e23a935
move these to the appropriate file
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llvm-svn: 48054
2008-03-08 22:28:45 +00:00
21a8f144a6
More ppc32 byval handling (bug fixes). Things
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are looking pretty good now.
llvm-svn: 48043
2008-03-08 01:41:42 +00:00
95cf661534
Implement x86 support for @llvm.prefetch. It corresponds to prefetcht{0|1|2} and prefetchnta instructions.
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llvm-svn: 48042
2008-03-08 00:58:38 +00:00
d2ab5fd713
Add support for calls with i128 return values on ppc64.
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llvm-svn: 48041
2008-03-08 00:19:12 +00:00
968f32ce3d
PPC64 passes arguments of integral type in i64 registers, not i32. Reflect this
...
by promoting smaller integral values (i32 at this point) to i64, then truncating
to get the wanted size.
llvm-svn: 48030
2008-03-07 20:49:02 +00:00
8d2ead2e34
Add support for lowering 128-bit shifts on ppc64.
...
llvm-svn: 48029
2008-03-07 20:36:53 +00:00
bfa252d402
Next bits of PPC byval handling. Basically functional
...
but there are bugs.
llvm-svn: 48028
2008-03-07 20:27:40 +00:00
20b5a2b037
Add support for ppc64 shifts with 7-bit (oversized) shift amount (e.g. PPCshl).
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llvm-svn: 48027
2008-03-07 20:18:24 +00:00
25ff7e217d
Replace SDT_PPCShiftOp in favor of SDTIntBinOps. This allows it to work
...
with 32 or 64-bit operands/results.
llvm-svn: 48026
2008-03-07 20:13:51 +00:00
d4defb00df
mark frem as expand for all legal fp types on x86, regardless of whether
...
we're using SSE or not. This fixes PR2122.
llvm-svn: 48006
2008-03-07 06:36:32 +00:00
636ab19205
some more spelling changes
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llvm-svn: 47996
2008-03-06 10:51:21 +00:00
e9b690b7f1
Refine Cell's i64 constant generation code to cover more constants where the
...
upper and lower 32-bits are the same (in addition to 0 and -1 previously.)
llvm-svn: 47985
2008-03-06 04:02:54 +00:00
dcabdb1b38
gcc likes things spelled correctly
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llvm-svn: 47981
2008-03-05 23:41:37 +00:00
0d235052d1
Next bit of PPC ByVal handling; call-site code seems
...
correct now.
llvm-svn: 47978
2008-03-05 23:31:27 +00:00
42f56b4838
- Fix support for "special" i64 immediates that can be loaded
...
using IL, ILA, et. al. v2i64 and i64 are now supported by
the select bits (SELB) instruction.
- Add missing comparison operations (testcase forthcoming)
- More multiclass refactoring.
llvm-svn: 47973
2008-03-05 23:02:02 +00:00
7c08a01698
evan implemented this.
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llvm-svn: 47948
2008-03-05 17:11:51 +00:00
3ea44e4ee9
isTwoAddress = 1 -> Constraints.
...
llvm-svn: 47941
2008-03-05 08:19:16 +00:00
6ec7dc6bea
PSLLWri etc. are two-address instructions.
...
llvm-svn: 47940
2008-03-05 08:11:27 +00:00
2acd0c25f6
add a note
...
llvm-svn: 47939
2008-03-05 07:22:39 +00:00
3bd59641ac
Ignore debugging related instructions if they get this far.
...
llvm-svn: 47934
2008-03-05 02:34:36 +00:00
801bfb2cf7
Rather than asserting. Dump out the MI that we are not able to encode and abort.
...
llvm-svn: 47933
2008-03-05 02:08:03 +00:00
0a62cb44ce
Add a target lowering hook to control whether it's worthwhile to compress fp constant.
...
For x86, if sse2 is available, it's not a good idea since cvtss2sd is slower than a movsd load and it prevents load folding. On x87, it's important to shrink fp constant since fldt is very expensive.
llvm-svn: 47931
2008-03-05 01:30:59 +00:00
357061a74d
64bit CAS on 32bit x86.
...
llvm-svn: 47929
2008-03-05 01:15:49 +00:00
6325446666
Refactor code. Remove duplicated functions that basically do the same thing as
...
findRegisterUseOperandIdx, findRegisterDefOperandIndx. Fix some naming inconsistencies.
llvm-svn: 47927
2008-03-05 00:59:57 +00:00
3fcd946c26
Removed spurious EnablePPCRS check.
...
llvm-svn: 47918
2008-03-04 23:27:33 +00:00
85d41a1c44
Move PPC lowering functions into PPCTargetLowering
...
class (cosmetic). First piece of byval implementation;
this doesn't work yet. No functional change.
llvm-svn: 47917
2008-03-04 23:17:14 +00:00
1af20ad336
Use a command-line option to turn register scavenging on/off for PPC.
...
llvm-svn: 47915
2008-03-04 23:13:51 +00:00
4fee9f35b5
x86-64 atomics
...
llvm-svn: 47903
2008-03-04 21:13:33 +00:00
59d58ab8c4
80 column violations.
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llvm-svn: 47878
2008-03-04 03:20:06 +00:00
33ff36321e
Remove -always-fold-and-in-test.
...
llvm-svn: 47871
2008-03-04 00:40:35 +00:00
a986eea82f
Add support for lowering i64 SRA_PARTS and friends on x86-64.
...
llvm-svn: 47865
2008-03-03 22:22:09 +00:00
632ea65072
This is the initial check-in for adding register scavenging to PPC. (Currently,
...
PPC-64 doesn't work.) This also lowers the spilling of the CR registers so that
it uses a register other than the default R0 register (the scavenger scrounges
for one). A significant part of this patch fixes how kill information is
handled.
llvm-svn: 47863
2008-03-03 22:19:16 +00:00
9d91785987
s/isReturnStruct()/hasStructRetAttr()/g
...
llvm-svn: 47857
2008-03-03 21:46:28 +00:00
d51372aa96
another random note
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llvm-svn: 47831
2008-03-02 19:29:42 +00:00
6b0a189225
add a note
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llvm-svn: 47830
2008-03-02 19:27:34 +00:00
a70df9e2ee
Evan implemented these.
...
llvm-svn: 47828
2008-03-02 18:05:14 +00:00
bd0bb3f07f
Evan implemented this.
...
llvm-svn: 47827
2008-03-02 17:56:29 +00:00
c93b48caeb
add support for lvsl, fixing PR1481
...
llvm-svn: 47825
2008-03-02 08:54:27 +00:00
8fb4c98284
add support for the sse.cmp.* intrinsics, which fixes sse.isamax with the CBE.
...
llvm-svn: 47824
2008-03-02 08:47:13 +00:00
9044719798
refactor intrinsic handling code out into its own method.
...
llvm-svn: 47823
2008-03-02 08:29:41 +00:00
2541f1dac6
fix printing of undef vectors, this fixes "simple" and "build" in UnitTests/Vector.
...
Now they all pass.
llvm-svn: 47820
2008-03-02 08:14:45 +00:00
4c058b39e4
insertelement got the wrong operands.
...
llvm-svn: 47819
2008-03-02 08:10:16 +00:00
051709436e
Several changes:
...
* Simplify handling of byval, making it easier to understand and more
consistent. This fixes PR2065.
* Clean up and simplify handling of GEPs. I can actually understand it now!
* Implement support for GEP'ing into vectors, this fixes
SingleSource/UnitTests/Vector/build2 among others.
llvm-svn: 47818
2008-03-02 08:07:24 +00:00
9140fba6ad
Fix a bug I introduced in constant array and constant vector handling.
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llvm-svn: 47816
2008-03-02 05:46:57 +00:00
7295bc15a0
implement shufflevector.
...
llvm-svn: 47815
2008-03-02 05:41:07 +00:00
689d830b6d
implement extractelement.
...
llvm-svn: 47812
2008-03-02 03:57:08 +00:00
d9cc003b0d
implement insertelement.
...
llvm-svn: 47811
2008-03-02 03:52:39 +00:00
92d929c21d
respect isSigned for vector types, fixing sdiv of vectors etc.
...
llvm-svn: 47810
2008-03-02 03:41:23 +00:00
fe1083be61
print the attribute in the right place, this fixes function returning vectors.
...
llvm-svn: 47809
2008-03-02 03:39:43 +00:00
d861066d15
vector types are simple types. This fixes div/rem of vectors.
...
llvm-svn: 47807
2008-03-02 03:33:31 +00:00
b104be599a
Print vector types appropriately. This gets basic vector code working
...
(PR1126)
llvm-svn: 47806
2008-03-02 03:29:50 +00:00
c8d974a323
rename PT -> VT for VectorTypes.
...
llvm-svn: 47805
2008-03-02 03:18:46 +00:00
895aef4720
Print i32/i64 integer constants as 1u instead of ((unsigned int)1).
...
Use dyn_cast better.
llvm-svn: 47804
2008-03-02 03:16:38 +00:00
647c6642e7
Move pr717 to here.
...
llvm-svn: 47803
2008-03-02 02:51:40 +00:00
20bcdba9ca
good catch anton
...
llvm-svn: 47800
2008-03-01 23:18:21 +00:00
f5c90ec12c
make CAS work
...
llvm-svn: 47799
2008-03-01 22:27:48 +00:00
d032c33300
all but CAS working on x86
...
llvm-svn: 47798
2008-03-01 21:52:34 +00:00
0070dd1de3
Add lock prefix support to x86. Also add the instructions necessary for the atomic ops. They are still marked pseudo, since I cannot figure out what format to use, but they are the correct opcode.
...
llvm-svn: 47795
2008-03-01 13:37:02 +00:00
0e8b146152
Use enumeration for preffered EH dwarf encoding reason
...
llvm-svn: 47770
2008-02-29 22:09:08 +00:00
17df4cd397
Use the correct instruction encodings for the 64-bit MMX movd.
...
llvm-svn: 47740
2008-02-29 01:35:12 +00:00
95a7be473c
Added option -align-loops=<true/false> to disable loop aligner pass.
...
llvm-svn: 47736
2008-02-28 23:29:57 +00:00
Anton Korobeynikov