615488ab45
- SSE4.1 extractfps extracts a f32 into a gr32 register. Very useful! Not. Fix the instruction specification and teaches lowering code to use it only when the only use is a store instruction.
...
llvm-svn: 48746
2008-03-24 21:52:23 +00:00
58db865d6e
Remove duplicated entries.
...
llvm-svn: 48714
2008-03-23 22:56:07 +00:00
1fdd5e9133
Minor typo fixes. Also add another FIXME.
...
llvm-svn: 48710
2008-03-23 20:32:06 +00:00
17fb491469
Add license header
...
llvm-svn: 48707
2008-03-23 14:53:18 +00:00
9f0e820fa3
Add Win64 compilation callback. This allows easy examples to be JITed on Win64!
...
llvm-svn: 48706
2008-03-23 14:44:32 +00:00
a347663762
Provide a JIT selector on win64
...
llvm-svn: 48704
2008-03-23 13:43:47 +00:00
7574ead985
Hack out the PIC mode on Win64 targets. This needs to be investigated later.
...
llvm-svn: 48703
2008-03-23 13:41:18 +00:00
4733e72a25
Code cleanup. Provide generic way of selecting JIT pointer bitwidth regardless
...
of compiler used.
llvm-svn: 48702
2008-03-23 13:40:45 +00:00
bd47269f13
Remove old-standing obsolete code.
...
llvm-svn: 48701
2008-03-23 12:32:54 +00:00
cec773d8e7
Honour built-in defines on win64 targets for automatically subtarget recognize.
...
Force stack alignment to 16 bytes on win targets.
llvm-svn: 48695
2008-03-22 21:18:22 +00:00
07a789d2b5
Recognize "windows" in target triple, not only "win32"
...
llvm-svn: 48694
2008-03-22 21:12:53 +00:00
b86e0936f1
Add information about callee-saved registers on Win64
...
llvm-svn: 48692
2008-03-22 21:04:01 +00:00
7f125b2ba5
Add convenient helper for win64 check. Simplify things slightly.
...
llvm-svn: 48691
2008-03-22 20:57:27 +00:00
7b4f4e1a86
Initial support for Win64 calling conventions. Still in early state.
...
llvm-svn: 48690
2008-03-22 20:37:30 +00:00
2fa75184f3
Another comments fixing
...
llvm-svn: 48683
2008-03-22 07:53:40 +00:00
c55b444a8f
Restore this assert now that the livevar bug is fixed.
...
This verifies kill info for "ret" fp operands is right.
llvm-svn: 48656
2008-03-21 20:41:27 +00:00
d97eea372a
Introduce a new node for holding call argument
...
flags. This is needed by the new legalize types
infrastructure which wants to expand the 64 bit
constants previously used to hold the flags on
32 bit machines. There are two functional changes:
(1) in LowerArguments, if a parameter has the zext
attribute set then that is marked in the flags;
before it was being ignored; (2) PPC had some bogus
code for handling two word arguments when using the
ELF 32 ABI, which was hard to convert because of
the bogusness. As suggested by the original author
(Nicolas Geoffray), I've disabled it for the moment.
Tested with "make check" and the Ada ACATS testsuite.
llvm-svn: 48640
2008-03-21 09:14:45 +00:00
68b11e14bc
remove Evan's "ugly hack" that sorta attempted to get
...
x86-64 return conventions correct, but was never enabled.
We can now do the "right thing" with multiple return values.
llvm-svn: 48635
2008-03-21 06:50:21 +00:00
5abbe6cef5
Add support for calls that return two FP values in
...
ST(0)/ST(1).
llvm-svn: 48634
2008-03-21 06:38:26 +00:00
7e59a30e9f
disable a bogus assertion.
...
llvm-svn: 48633
2008-03-21 06:01:05 +00:00
b6f04a3e0a
Enable support for returning two long-double values in ST(0)/ST(1).
...
This allows us to compile fp-stack-2results.ll into:
_test:
fldz
fld1
ret
which returns 1 in ST(0) and 0 in ST(1). This is needed for x86-64
_Complex long double.
llvm-svn: 48632
2008-03-21 05:57:20 +00:00
92b4488202
Undo 48570. Correctly match mmx shift instructions with an immediate operand.
...
llvm-svn: 48627
2008-03-21 00:40:09 +00:00
7a3e750fd2
Fix this xform: (sra (shl X, m), result_size) -> (sign_extend (trunc (shl X, result_size - n - m)))
...
llvm-svn: 48578
2008-03-20 02:18:41 +00:00
bbba76fc99
Add intrinsics to match mmx shift builtin's with immediate operand.
...
llvm-svn: 48569
2008-03-19 23:38:52 +00:00
7da2bceb3b
Don't loose incoming argument registers. Fix documentation style.
...
llvm-svn: 48545
2008-03-19 16:39:45 +00:00
8fe9109469
Fix X86's isTruncateFree to not claim that truncate to i1 is free. This fixes Bill's testcase that failed for r48491.
...
llvm-svn: 48542
2008-03-19 08:30:06 +00:00
2f6ab65d77
On Darwin, GCC issues a ".globl" for something that has a "visibility protected"
...
attribute instead of ".protected".
llvm-svn: 48516
2008-03-18 23:38:12 +00:00
484064370a
Fix a x86-64 isel lowering bug that's been around forever. A x86-64 varargs function implicitly reads X86::AL, don't clobber it!
...
llvm-svn: 48515
2008-03-18 23:36:35 +00:00
24bc123e80
Unbreak JIT. Ignore TargetInstrInfo::IMPLICIT_DEF.
...
llvm-svn: 48447
2008-03-17 06:56:52 +00:00
9030ecec88
Add a couple missing SSE4 instructions
...
llvm-svn: 48430
2008-03-16 21:14:46 +00:00
d3d0ad3f58
Make insert_subreg a two-address instruction, vastly simplifying LowerSubregs pass. Add a new TII, subreg_to_reg, which is like insert_subreg except that it takes an immediate implicit value to insert into rather than a register.
...
llvm-svn: 48412
2008-03-16 03:12:01 +00:00
0e7b00d79f
Replace all target specific implicit def instructions with a target independent one: TargetInstrInfo::IMPLICIT_DEF.
...
llvm-svn: 48380
2008-03-15 00:03:38 +00:00
5be52a6053
Fix some 80 col violations.
...
llvm-svn: 48361
2008-03-14 07:46:48 +00:00
96bdbd6c5d
Fix a number of encoding bugs. SSE 4.1 instructions MPSADBWrri, PINSRDrr, etc. have 8-bits immediate field (ImmT == Imm8).
...
llvm-svn: 48360
2008-03-14 07:39:27 +00:00
77c8da7f00
Add debugging stuff.
...
llvm-svn: 48359
2008-03-14 07:13:42 +00:00
477d0f5294
Add an issue that is preventing instcombine from doing a simplification.
...
llvm-svn: 48356
2008-03-14 06:00:19 +00:00
dd55d3f1b2
Get rid of a pseudo instruction and replace it with subreg based operation on real instructions, ridding the asm printers of the hack used to do this previously. In the process, update LowerSubregs to be careful about eliminating copies that have side affects.
...
Note: the coalescer will have to be careful about this too, when it starts coalescing insert_subreg nodes.
llvm-svn: 48329
2008-03-13 05:47:01 +00:00
8a923e7c28
Reimplement the parameter attributes support, phase #1 . hilights:
...
1. There is now a "PAListPtr" class, which is a smart pointer around
the underlying uniqued parameter attribute list object, and manages
its refcount. It is now impossible to mess up the refcount.
2. PAListPtr is now the main interface to the underlying object, and
the underlying object is now completely opaque.
3. Implementation details like SmallVector and FoldingSet are now no
longer part of the interface.
4. You can create a PAListPtr with an arbitrary sequence of
ParamAttrsWithIndex's, no need to make a SmallVector of a specific
size (you can just use an array or scalar or vector if you wish).
5. All the client code that had to check for a null pointer before
dereferencing the pointer is simplified to just access the
PAListPtr directly.
6. The interfaces for adding attrs to a list and removing them is a
bit simpler.
Phase #2 will rename some stuff (e.g. PAListPtr) and do other less
invasive changes.
llvm-svn: 48289
2008-03-12 17:45:29 +00:00
99ee78ef63
Clean up my own mess.
...
X86 lowering normalize vector 0 to v4i32. However DAGCombine can fold (sub x, x) -> 0 after legalization. It can create a zero vector of a type that's not expected (e.g. v8i16). We don't want to disable the optimization since leaving a (sub x, x) is really bad. Add isel patterns for other types of vector 0 to ensure correctness. It's highly unlikely to happen other than in bugpoint reduced test cases.
llvm-svn: 48279
2008-03-12 07:02:50 +00:00
e8fa50f63a
Correctly propagate thread-local flag from aliasee to alias. This fixes PR2137
...
llvm-svn: 48257
2008-03-11 22:38:53 +00:00
24570836b2
Use PassManagerBase instead of FunctionPassManager for functions
...
that merely add passes. This allows them to be used with either
FunctionPassManager or PassManager, or even with a custom new
kind of pass manager.
llvm-svn: 48256
2008-03-11 22:29:46 +00:00
8abed80a69
Implement basic support for the 'f' register class constraint. This basically
...
works, but probably won't if you mix it with 't' or 'u' yet.
llvm-svn: 48243
2008-03-11 19:50:13 +00:00
7b27ccfd5e
coalesce away 80-bit floating point copies.
...
llvm-svn: 48241
2008-03-11 19:30:09 +00:00
7930d8e775
convert a massive if statement to a switch.
...
llvm-svn: 48240
2008-03-11 19:28:17 +00:00
120ad01fcb
start handling the 'f' x87 constraint.
...
llvm-svn: 48239
2008-03-11 19:06:29 +00:00
342e4104d3
Missed part of recommit.
...
llvm-svn: 48224
2008-03-11 10:27:36 +00:00
aa7c2105de
Recommitting parts of r48130. These do not appear to cause the observed failures.
...
llvm-svn: 48223
2008-03-11 10:09:17 +00:00
5b59e372dc
In 32-bit mode, mark 64-bit GPR's as unallocatable.
...
llvm-svn: 48217
2008-03-11 07:16:00 +00:00
a3860a2422
Fix the build on gcc 4.2.
...
llvm-svn: 48212
2008-03-11 05:56:09 +00:00
1bd44363f2
Change the model for FP Stack return to use fp operands on the
...
RET instruction instead of using FpSET_ST0_32. This also generalizes
the code to handling returning of multiple FP results.
llvm-svn: 48209
2008-03-11 03:23:40 +00:00
a4fa0ad30d
abort with an assert instead of a cerr to get line#
...
llvm-svn: 48199
2008-03-10 23:56:08 +00:00
7362d38391
Don't emit FP_REG_KILL into a block that just returns. Nothing
...
can be live out of the block anyway, so it isn't needed.
llvm-svn: 48192
2008-03-10 23:34:12 +00:00
4b3a7fa823
Eliminate the FP_GET_ST0/FP_SET_ST0 target-specific dag nodes, just lower to
...
copyfromreg/copytoreg instead.
llvm-svn: 48174
2008-03-10 21:08:41 +00:00
ae2c56d93e
Default ISD::PREFETCH to expand.
...
llvm-svn: 48169
2008-03-10 19:38:10 +00:00
d4e1d9eeb2
Revert 48125, 48126, and 48130 for now to unbreak some x86-64 tests.
...
llvm-svn: 48167
2008-03-10 19:31:26 +00:00
a6729e8666
Give TargetLowering::getSetCCResultType() a parameter so that ISD::SETCC's
...
return ValueType can depend its operands' ValueType.
This is a cosmetic change, no functionality impacted.
llvm-svn: 48145
2008-03-10 15:42:14 +00:00
4ba3f0430b
Allow insert_subreg into implicit, target-specific values.
...
Change insert/extract subreg instructions to be able to be used in TableGen patterns.
Use the above features to reimplement an x86-64 pseudo instruction as a pattern.
llvm-svn: 48130
2008-03-10 06:12:08 +00:00
4e622ec86d
Increase ISD::ParamFlags to 64 bits. Increase the ByValSize
...
field to 32 bits, thus enabling correct handling of ByVal
structs bigger than 0x1ffff. Abstract interface a bit.
Fixes gcc.c-torture/execute/pr23135.c and
gcc.c-torture/execute/pr28982b.c in gcc testsuite (were ICE'ing
on ppc32, quietly producing wrong code on x86-32.)
llvm-svn: 48122
2008-03-10 02:17:22 +00:00
86829f0ff7
teach X86InstrInfo::copyRegToReg how to copy into ST(0) from
...
an RFP register class.
Teach ScheduleDAG how to handle CopyToReg with different src/dst
reg classes.
This allows us to compile trivial inline asms that expect stuff
on the top of x87-fp stack.
llvm-svn: 48107
2008-03-09 09:15:31 +00:00
b79bafcec8
add some code to support cross-register class copying from
...
RST -> RFP{32/64/80}. We only handle ST(0) for now.
llvm-svn: 48104
2008-03-09 08:46:19 +00:00
c4c9dde04c
rearrange some code, no functionality change.
...
llvm-svn: 48101
2008-03-09 07:58:04 +00:00
459f518703
claim ST(x) registers are 80 bits, which is true. This doesn't affect
...
codegen yet because these can't be spilled (they don't exist until after RA).
llvm-svn: 48098
2008-03-09 07:49:01 +00:00
4c869594bc
rename FP_SETRESULT -> FP_SET_ST0
...
llvm-svn: 48094
2008-03-09 07:08:44 +00:00
d587e580a6
rename FpGETRESULT32 -> FpGET_ST0_32 etc. Add support for
...
isel'ing value preserving FP roundings from one fp stack reg to another
into a noop, instead of stack traffic.
llvm-svn: 48093
2008-03-09 07:05:32 +00:00
b6387c8a74
Finish implementing a readme entry: when inserting an i64 variable
...
into a vector of zeros or undef, and when the top part is obviously
zero, we can just use movd + shuffle. This allows us to compile
vec_set-B.ll into:
_test3:
movl $1234567, %eax
andl 4(%esp), %eax
movd %eax, %xmm0
ret
instead of:
_test3:
subl $28, %esp
movl $1234567, %eax
andl 32(%esp), %eax
movl %eax, (%esp)
movl $0, 4(%esp)
movq (%esp), %xmm0
addl $28, %esp
ret
llvm-svn: 48090
2008-03-09 05:42:06 +00:00
93930dc28c
add a note
...
llvm-svn: 48064
2008-03-09 01:08:22 +00:00
eef374c197
Implement a readme entry, compiling
...
#include <xmmintrin.h>
__m128i doload64(short x) {return _mm_set_epi16(0,0,0,0,0,0,0,1);}
into:
movl $1, %eax
movd %eax, %xmm0
ret
instead of a constant pool load.
llvm-svn: 48063
2008-03-09 01:05:04 +00:00
ad58828354
1) Improve comments.
...
2) Don't try to insert an i64 value into the low part of a
vector with movq on an x86-32 target. This allows us to
compile:
__m128i doload64(short x) {return _mm_set_epi16(0,0,0,0,0,0,0,1);}
into:
_doload64:
movaps LCPI1_0, %xmm0
ret
instead of:
_doload64:
subl $28, %esp
movl $0, 4(%esp)
movl $1, (%esp)
movq (%esp), %xmm0
addl $28, %esp
ret
llvm-svn: 48057
2008-03-08 22:59:52 +00:00
8a6ebd23a8
minor simplifications to this code, don't create a dead
...
SCALAR_TO_VECTOR on paths that end up not using it.
llvm-svn: 48056
2008-03-08 22:48:29 +00:00
35adf46967
This one looks easy, add a note.
...
llvm-svn: 48055
2008-03-08 22:32:39 +00:00
a76e23a935
move these to the appropriate file
...
llvm-svn: 48054
2008-03-08 22:28:45 +00:00
95cf661534
Implement x86 support for @llvm.prefetch. It corresponds to prefetcht{0|1|2} and prefetchnta instructions.
...
llvm-svn: 48042
2008-03-08 00:58:38 +00:00
d4defb00df
mark frem as expand for all legal fp types on x86, regardless of whether
...
we're using SSE or not. This fixes PR2122.
llvm-svn: 48006
2008-03-07 06:36:32 +00:00
636ab19205
some more spelling changes
...
llvm-svn: 47996
2008-03-06 10:51:21 +00:00
7c08a01698
evan implemented this.
...
llvm-svn: 47948
2008-03-05 17:11:51 +00:00
3ea44e4ee9
isTwoAddress = 1 -> Constraints.
...
llvm-svn: 47941
2008-03-05 08:19:16 +00:00
6ec7dc6bea
PSLLWri etc. are two-address instructions.
...
llvm-svn: 47940
2008-03-05 08:11:27 +00:00
2acd0c25f6
add a note
...
llvm-svn: 47939
2008-03-05 07:22:39 +00:00
3bd59641ac
Ignore debugging related instructions if they get this far.
...
llvm-svn: 47934
2008-03-05 02:34:36 +00:00
801bfb2cf7
Rather than asserting. Dump out the MI that we are not able to encode and abort.
...
llvm-svn: 47933
2008-03-05 02:08:03 +00:00
0a62cb44ce
Add a target lowering hook to control whether it's worthwhile to compress fp constant.
...
For x86, if sse2 is available, it's not a good idea since cvtss2sd is slower than a movsd load and it prevents load folding. On x87, it's important to shrink fp constant since fldt is very expensive.
llvm-svn: 47931
2008-03-05 01:30:59 +00:00
357061a74d
64bit CAS on 32bit x86.
...
llvm-svn: 47929
2008-03-05 01:15:49 +00:00
6325446666
Refactor code. Remove duplicated functions that basically do the same thing as
...
findRegisterUseOperandIdx, findRegisterDefOperandIndx. Fix some naming inconsistencies.
llvm-svn: 47927
2008-03-05 00:59:57 +00:00
4fee9f35b5
x86-64 atomics
...
llvm-svn: 47903
2008-03-04 21:13:33 +00:00
59d58ab8c4
80 column violations.
...
llvm-svn: 47878
2008-03-04 03:20:06 +00:00
33ff36321e
Remove -always-fold-and-in-test.
...
llvm-svn: 47871
2008-03-04 00:40:35 +00:00
a986eea82f
Add support for lowering i64 SRA_PARTS and friends on x86-64.
...
llvm-svn: 47865
2008-03-03 22:22:09 +00:00
9d91785987
s/isReturnStruct()/hasStructRetAttr()/g
...
llvm-svn: 47857
2008-03-03 21:46:28 +00:00
a70df9e2ee
Evan implemented these.
...
llvm-svn: 47828
2008-03-02 18:05:14 +00:00
20bcdba9ca
good catch anton
...
llvm-svn: 47800
2008-03-01 23:18:21 +00:00
f5c90ec12c
make CAS work
...
llvm-svn: 47799
2008-03-01 22:27:48 +00:00
d032c33300
all but CAS working on x86
...
llvm-svn: 47798
2008-03-01 21:52:34 +00:00
0070dd1de3
Add lock prefix support to x86. Also add the instructions necessary for the atomic ops. They are still marked pseudo, since I cannot figure out what format to use, but they are the correct opcode.
...
llvm-svn: 47795
2008-03-01 13:37:02 +00:00
0e8b146152
Use enumeration for preffered EH dwarf encoding reason
...
llvm-svn: 47770
2008-02-29 22:09:08 +00:00
17df4cd397
Use the correct instruction encodings for the 64-bit MMX movd.
...
llvm-svn: 47740
2008-02-29 01:35:12 +00:00
95a7be473c
Added option -align-loops=<true/false> to disable loop aligner pass.
...
llvm-svn: 47736
2008-02-28 23:29:57 +00:00
507713de08
Set to default: x86 no longer fold and into test if it has more than one use.
...
llvm-svn: 47711
2008-02-28 07:46:38 +00:00
83e80cd368
Add a random not very important note
...
llvm-svn: 47704
2008-02-28 04:52:59 +00:00
c799065cc3
Add a quick and dirty "loop aligner pass". x86 uses it to align its loops to 16-byte boundaries.
...
llvm-svn: 47703
2008-02-28 00:43:03 +00:00
93e8b679a3
A few more small things I've run into.
...
llvm-svn: 47702
2008-02-28 00:21:43 +00:00
ae24cca0e4
Preparation step for some cleanup/generalization in EH information emission:
...
provide TAI hook for selection of EH data emission format. Currently unused.
llvm-svn: 47699
2008-02-27 23:33:50 +00:00
3d17e4c427
This is done.
...
llvm-svn: 47688
2008-02-27 20:26:32 +00:00
83263b8cfb
Make X86TargetLowering::LowerSINT_TO_FP return without creating a dead
...
stack slot and store if the SINT_TO_FP is actually legal. This allows
us to compile:
double a(double b) {return (unsigned)b;}
to:
_a:
cvttsd2siq %xmm0, %rax
movl %eax, %eax
cvtsi2sdq %rax, %xmm0
ret
instead of:
_a:
subq $8, %rsp
cvttsd2siq %xmm0, %rax
movl %eax, %eax
cvtsi2sdq %rax, %xmm0
addq $8, %rsp
ret
crazy.
llvm-svn: 47660
2008-02-27 05:57:41 +00:00
5fe95a04f5
this code is correct but strange looking ;-)
...
llvm-svn: 47659
2008-02-27 05:48:44 +00:00
3c7d3d5700
Compile x86-64-and-mask.ll into:
...
_test:
movl %edi, %eax
ret
instead of:
_test:
movl $4294967295, %ecx
movq %rdi, %rax
andq %rcx, %rax
ret
It would be great to write this as a Pat pattern that used subregs
instead of a 'pseudo' instruction, but I don't know how to do that
in td files.
llvm-svn: 47658
2008-02-27 05:47:54 +00:00
3f86109fd1
add a note
...
llvm-svn: 47652
2008-02-27 01:17:20 +00:00
3bfca3e942
Refactor according to Evan's and Anton's suggestions.
...
llvm-svn: 47635
2008-02-26 22:21:54 +00:00
c24ea4fb41
Change "Name" to "AsmName" in the target register info. Gee, a refactoring tool
...
would have been a Godsend here!
llvm-svn: 47625
2008-02-26 21:11:01 +00:00
1f17bf6171
Correct function comments.
...
llvm-svn: 47606
2008-02-26 17:50:59 +00:00
80d6b87934
De-tabify
...
llvm-svn: 47600
2008-02-26 10:57:23 +00:00
69a10f4112
Add support for intermodule tail calls on x86/32bit with
...
GOT-style position independent code. Before only tail calls to
protected/hidden functions within the same module were optimized.
Now all function calls are tail call optimized.
llvm-svn: 47594
2008-02-26 10:21:54 +00:00
b01b99ec78
Change the lowering of arguments for tail call optimized
...
calls. Before arguments that could overwrite each other were
explicitly lowered to a stack slot, not giving the register allocator
a chance to optimize. Now a sequence of copyto/copyfrom virtual
registers ensures that arguments are loaded in (virtual) registers
before they are lowered to the stack slot (and might overwrite each
other). Also parameter stack slots are marked mutable for
(potentially) tail calling functions.
llvm-svn: 47593
2008-02-26 09:19:59 +00:00
a790af3a88
Revert the assert for MUL_LOHI with an unused high result; Chris
...
pointed out that this isn't correct at -O0.
llvm-svn: 47575
2008-02-25 22:43:48 +00:00
65b404d61c
Revise previous patch per review.
...
llvm-svn: 47573
2008-02-25 22:29:22 +00:00
0be2f3b941
Add an assert to verify that we don't see an
...
{S,U}MUL_LOHI with an unused high value.
llvm-svn: 47569
2008-02-25 22:15:55 +00:00
2ff975e749
Remove the hack that turned an {S,U}MUL_LOHI with an unused high
...
result into a MUL late in the X86 codegen process. ISD::MUL is
once again Legal on X86, so this is no longer needed. And, the
hack was suboptimal; see PR1874 for details.
llvm-svn: 47567
2008-02-25 21:57:04 +00:00
1f372edd97
Convert MaskedValueIsZero and all its users to use APInt. Also add
...
a SignBitIsZero function to simplify a common use case.
llvm-svn: 47561
2008-02-25 21:11:39 +00:00
32d84b1772
Expand removal of MMX memory copies to allow 1 level
...
of TokenFactor underneath chain (seems to be enough)
llvm-svn: 47554
2008-02-25 19:20:14 +00:00
42cb72e52c
Turning on remat of pic loads.
...
llvm-svn: 47524
2008-02-23 02:07:42 +00:00
4d17671997
No need recognize load from a fixed argument slot as re-materializable. LiveIntervalAnalysis already handles it as a special case.
...
llvm-svn: 47522
2008-02-23 01:47:44 +00:00
09f410b6d7
Split ParameterAttributes.h, putting the complicated
...
stuff into ParamAttrsList.h. Per feedback from
ParamAttrs changes.
llvm-svn: 47504
2008-02-22 22:17:59 +00:00
eac159c1f0
MMX vectors are passed 4-byte aligned.
...
llvm-svn: 47483
2008-02-22 17:47:28 +00:00
94ba37f8e3
Allow re-materialization of pic load (controlled by -remat-pic-load for now).
...
llvm-svn: 47476
2008-02-22 09:25:47 +00:00
ab8bfc28c8
copy mmx values from/to memory with GPRs on x86-32
...
instead of with mmx registers. This horribleness is apparently
done by gcc to avoid having to insert emms in places that really
should have it. This is the second half of rdar://5741668.
llvm-svn: 47474
2008-02-22 05:18:04 +00:00
997b3a65ca
Start using GPR's to copy around mmx value instead of mmx regs.
...
GCC apparently does this, and code depends on not having to do
emms when this happens. This is x86-64 only so far, second half
should handle x86-32.
rdar://5741668
llvm-svn: 47470
2008-02-22 02:09:43 +00:00
5d8fa828f1
A few minor updates, removing implemented stuff and adding a couple of
...
new things.
llvm-svn: 47458
2008-02-21 21:16:49 +00:00
e86c91f5b2
Dan implemented one multiply issue. Replace it with another. :)
...
llvm-svn: 47431
2008-02-21 06:51:29 +00:00
95528943e9
Atomic op support. If any gcc test uses __sync builtins, it might start failing on archs that haven't implemented them yet
...
llvm-svn: 47430
2008-02-21 06:45:13 +00:00
b6b69208ba
Poorly named option.
...
llvm-svn: 47400
2008-02-20 20:57:32 +00:00
18991d78fa
Fix newly-introduced 4.3 warnings
...
llvm-svn: 47375
2008-02-20 12:07:57 +00:00
40d67c59d5
Remove bunch of gcc 4.3-related warnings from Target
...
llvm-svn: 47369
2008-02-20 11:22:39 +00:00
579f07135a
Unbreak build with gcc 4.3: provide missed includes and silence most annoying warnings.
...
llvm-svn: 47367
2008-02-20 11:08:44 +00:00
7626ab33d8
Disable for now. This is pessimizing code.
...
llvm-svn: 47354
2008-02-20 02:29:17 +00:00
5ce8dd93ef
Add hidden option -x86-fold-and-in-test to test the effect the test / and folding change.
...
llvm-svn: 47351
2008-02-19 23:36:51 +00:00
97b9662f78
Don't fold and's into test instructions if they have multiple uses.
...
This compiles test-nofold.ll into:
_test:
movl $15, %ecx
andl 4(%esp), %ecx
testl %ecx, %ecx
movl $42, %eax
cmove %ecx, %eax
ret
instead of:
_test:
movl 4(%esp), %eax
movl %eax, %ecx
andl $15, %ecx
testl $15, %eax
movl $42, %eax
cmove %ecx, %eax
ret
llvm-svn: 47330
2008-02-19 17:37:35 +00:00
3b56f506e7
Me not like duplicated comments.
...
llvm-svn: 47300
2008-02-19 02:05:16 +00:00
6200c225e0
- When DAG combiner is folding a bit convert into a BUILD_VECTOR, it should check if it's essentially a SCALAR_TO_VECTOR. Avoid turning (v8i16) <10, u, u, u> to <10, 0, u, u, u, u, u, u>. Instead, simply convert it to a SCALAR_TO_VECTOR of the proper type.
...
- X86 now normalize SCALAR_TO_VECTOR to (BIT_CONVERT (v4i32 SCALAR_TO_VECTOR)). Get rid of X86ISD::S2VEC.
llvm-svn: 47290
2008-02-18 23:04:32 +00:00
c589243107
Chris pointed out that it's not necessary to set i64 MUL to Expand
...
on x86-32 since i64 itself is not a Legal type. And, update some
comments.
llvm-svn: 47282
2008-02-18 19:34:53 +00:00
a827205670
Add a note about sext from i1 plus flags use.
...
llvm-svn: 47278
2008-02-18 18:30:13 +00:00
a589ee11bb
Don't mark scalar integer multiplication as Expand on x86, since x86
...
has plain one-result scalar integer multiplication instructions.
This avoids expanding such instructions into MUL_LOHI sequences that
must be special-cased at isel time, and avoids the problem with that
code that provented memory operands from being folded.
This fixes PR1874, addressesing the most common case. The uncommon
cases of optimizing multiply-high operations will require work
in DAGCombiner.
llvm-svn: 47277
2008-02-18 17:55:26 +00:00
1f6520842c
move PR2053 to here.
...
llvm-svn: 47237
2008-02-17 19:43:57 +00:00
fedcf477b5
I cannot find a libgcc function for this builtin. Therefor expanding it to a noop (which is how it use to be treated). If someone who knows the x86 backend better than me could tell me how to get a lock prefix on an instruction, that would be nice to complete x86 support.
...
llvm-svn: 47213
2008-02-16 14:46:26 +00:00
9b254eed32
llvm.memory.barrier, and impl for x86 and alpha
...
llvm-svn: 47204
2008-02-16 01:24:58 +00:00
7b1431785b
Handle \n's in value names for more targets. The asm printers
...
really really really need refactoring :(
llvm-svn: 47171
2008-02-15 19:04:54 +00:00
318c41f9e8
If the llvm name contains an unprintable character, don't print it in
...
the global comment. This prevents printing things like:
... # foo
bar
when the name is "foo\nbar".
llvm-svn: 47170
2008-02-15 18:56:05 +00:00
67b818f503
Remove warning about 64-bit code on processor
...
that doesn't support it. Per Chris.
llvm-svn: 47162
2008-02-15 18:09:51 +00:00
401a4d72d5
nocona, core2 and penryn support 64 bit.
...
llvm-svn: 47149
2008-02-15 01:22:41 +00:00
4c95dbd69f
In TargetLowering::LowerCallTo, don't assert that
...
the return value is zero-extended if it isn't
sign-extended. It may also be any-extended.
Also, if a floating point value was returned
in a larger floating point type, pass 1 as the
second operand to FP_ROUND, which tells it
that all the precision is in the original type.
I think this is right but I could be wrong.
Finally, when doing libcalls, set isZExt on
a parameter if it is "unsigned". Currently
isSExt is set when signed, and nothing is
set otherwise. This should be right for all
calls to standard library routines.
llvm-svn: 47122
2008-02-14 17:28:50 +00:00
53e1b3f9d5
Change how FP immediates are handled.
...
1) ConstantFP is now expand by default
2) ConstantFP is not turned into TargetConstantFP during Legalize
if it is legal.
This allows ConstantFP to be handled like Constant, allowing for
targets that can encode FP immediates as MachineOperands.
As a bonus, fix up Itanium FP constants, which now correctly match,
and match more constants! Hooray.
llvm-svn: 47121
2008-02-14 08:57:00 +00:00
eb63b09206
upgrade some entries, remove stuff that is done.
...
llvm-svn: 47109
2008-02-14 06:19:02 +00:00
5bc0957f5b
the mid-level optimizer removes this stuff.
...
llvm-svn: 47108
2008-02-14 05:43:18 +00:00
b43983b274
this one is easy.
...
llvm-svn: 47107
2008-02-14 05:41:38 +00:00
3bd37f549a
This readme entry is done, testcase here: CodeGen/X86/zero-remat.ll
...
llvm-svn: 47106
2008-02-14 05:39:46 +00:00
9ca025f1dc
Assigning an APInt to 0 with plain assignment gives it a one-bit
...
size. Initialize these APInts to properly-sized zero values.
llvm-svn: 47099
2008-02-13 23:07:24 +00:00
e1d9ee66ed
Simplify some logic in ComputeMaskedBits. And change ComputeMaskedBits
...
to pass the mask APInt by value, not by reference.
llvm-svn: 47096
2008-02-13 22:28:48 +00:00
21ad494f67
Enable exception handling int JIT
...
llvm-svn: 47079
2008-02-13 18:39:37 +00:00
eea32990a9
readme updates
...
llvm-svn: 47051
2008-02-13 07:06:12 +00:00
244183ef0d
commuteInstr() can now commute non-ssa machine instrs.
...
llvm-svn: 47043
2008-02-13 02:46:49 +00:00
f990faf23b
Convert SelectionDAG::ComputeMaskedBits to use APInt instead of uint64_t.
...
Add an overload that supports the uint64_t interface for use by clients
that haven't been updated yet.
llvm-svn: 47039
2008-02-13 00:35:47 +00:00
ffde4ff5b1
__DATA not __DATA__ is the right segment name on darwin.
...
Spotted by Nick Kledzik.
llvm-svn: 47037
2008-02-12 23:35:09 +00:00
8ef50214f0
SSE4.1 64b integer insert/extract pattern support
...
Move formats into the formats file
llvm-svn: 47035
2008-02-12 22:51:28 +00:00
8a25d6ac53
Only using x86-64 rip relative addressing in non-staic mode?
...
llvm-svn: 47019
2008-02-12 19:20:46 +00:00
352acec37e
Update comment.
...
llvm-svn: 47002
2008-02-12 07:59:55 +00:00
4d8c98b8f9
Unbreak various insert_vector_elt and extract_vector_elt tests in presence of SSE4.
...
llvm-svn: 47001
2008-02-12 07:59:45 +00:00
2d77e8e446
Enable SSE4 codegen and pattern matching.
...
Add some notes to the README.
llvm-svn: 46949
2008-02-11 04:19:36 +00:00
3050f74a1d
xmm0 variable blends
...
llvm-svn: 46931
2008-02-10 18:47:57 +00:00
3a4be0fdef
Rename MRegisterInfo to TargetRegisterInfo.
...
llvm-svn: 46930
2008-02-10 18:45:23 +00:00
727c7634c7
memopv16i8 had wrong alignment requirement, would have broken pabsb
...
pabs{b,w,d} are not two address
fix extract-to-mem sse4 ops
add sse4 vector sign extend nodes
llvm-svn: 46915
2008-02-09 23:46:37 +00:00
6715f755cc
Skeleton of insert and extract matching, more to come
...
llvm-svn: 46902
2008-02-09 01:38:08 +00:00
3b3286d4bc
It's not always safe to fold movsd into xorpd, etc. Check the alignment of the load address first to make sure it's 16 byte aligned.
...
llvm-svn: 46893
2008-02-08 21:20:40 +00:00
36c2967d89
64-bit (MMX) vectors do not need restrictive alignment.
...
128-bit vectors need it only when SSE is on.
llvm-svn: 46890
2008-02-08 19:48:20 +00:00
7a55a94ba1
Avoid needlessly casting away const qualifiers.
...
llvm-svn: 46877
2008-02-08 03:29:40 +00:00
8d59dd119b
Added missing entries in X86 load / store folding tables.
...
llvm-svn: 46866
2008-02-08 00:12:56 +00:00
16d4bc3dc0
Follow Chris' suggestion; change the PseudoSourceValue accessors
...
to return pointers instead of references, since this is always what
is needed.
llvm-svn: 46857
2008-02-07 18:41:25 +00:00
63a8452e9c
Add SourceValue information for outgoing argument stores on x86.
...
llvm-svn: 46854
2008-02-07 16:28:05 +00:00
a20a773654
Fix a x86-64 codegen deficiency. Allow gv + offset when using rip addressing mode.
...
Before:
_main:
subq $8, %rsp
leaq _X(%rip), %rax
movsd 8(%rax), %xmm1
movss _X(%rip), %xmm0
call _t
xorl %ecx, %ecx
movl %ecx, %eax
addq $8, %rsp
ret
Now:
_main:
subq $8, %rsp
movsd _X+8(%rip), %xmm1
movss _X(%rip), %xmm0
call _t
xorl %ecx, %ecx
movl %ecx, %eax
addq $8, %rsp
ret
Notice there is another idiotic codegen issue that needs to be fixed asap:
xorl %ecx, %ecx
movl %ecx, %eax
llvm-svn: 46850
2008-02-07 08:53:49 +00:00
1bc1cae318
In some cases, e.g. ADD32ri, no transformation is made. Guide against it.
...
llvm-svn: 46849
2008-02-07 08:29:53 +00:00
2d489b5081
Re-apply the memory operand changes, with a fix for the static
...
initializer problem, a minor tweak to the way the
DAGISelEmitter finds load/store nodes, and a renaming of the
new PseudoSourceValue objects.
llvm-svn: 46827
2008-02-06 22:27:42 +00:00
d88f1d060e
Implement sseregparm.
...
llvm-svn: 46764
2008-02-05 20:46:33 +00:00
2cb9068c78
Dwarf requires variable entries to be in the source order. Right now, since we are recording variable information at isel time this means parameters would appear in the reverse order. The short term fix is to issue recordVariable() at asm printing time instead.
...
llvm-svn: 46724
2008-02-04 23:06:48 +00:00
e146c0e3fd
The rest of the SSE4.1 intrinsic patterns that are obvious to me. Getting
...
Evan's help with the rest.
llvm-svn: 46697
2008-02-04 06:00:24 +00:00
ccdfd4aa17
Some more SSE 4.1 intrinsic patterns.
...
llvm-svn: 46696
2008-02-04 05:34:34 +00:00
e14fdfaecd
SSE 4.1 Intrinsics and detection
...
llvm-svn: 46681
2008-02-03 07:18:54 +00:00
32e5347eb8
Get rid of the annoying blank lines before labels.
...
llvm-svn: 46667
2008-02-02 08:39:46 +00:00
f5b9938ef6
Don't use uninitialized values. Fixes vec_align.ll on X86 Linux.
...
llvm-svn: 46666
2008-02-02 08:29:58 +00:00
efd142a920
SDIsel processes llvm.dbg.declare by recording the variable debug information descriptor and its corresponding stack frame index in MachineModuleInfo. This only works if the local variable is "homed" in the stack frame. It does not work for byval parameter, etc.
...
Added ISD::DECLARE node type to represent llvm.dbg.declare intrinsic. Now the intrinsic calls are lowered into a SDNode and lives on through out the codegen passes.
For now, since all the debugging information recording is done at isel time, when a ISD::DECLARE node is selected, it has the side effect of also recording the variable. This is a short term solution that should be fixed in time.
llvm-svn: 46659
2008-02-02 04:07:54 +00:00
4e7ff941f1
Frame index can be negative.
...
llvm-svn: 46655
2008-02-02 00:17:00 +00:00
d6e44ab5ec
Remove the nasty LABEL hack with a much less evil one. Now llvm.dbg.func.start implies a stoppoint is set. SelectionDAGISel records a new source line but does not create a ISD::LABEL node for this special stoppoint. Asm printer will magically print this label. This ensures nothing is emitted before.
...
llvm-svn: 46635
2008-02-01 09:10:45 +00:00
27b32b87ed
Revert 46556 and 46585. Dan please fix the PseudoSourceValue problem and re-commit.
...
llvm-svn: 46623
2008-01-31 21:00:00 +00:00
1c6c16ea11
Add an extra operand to LABEL nodes which distinguishes between debug, EH, or misc labels. This fixes the EH breakage. However I am not convinced this is *the* solution.
...
llvm-svn: 46609
2008-01-31 09:59:15 +00:00
6332dbec69
Add x86 specific getFrameIndexOffset(). This fixes local variable debugging info.
...
llvm-svn: 46598
2008-01-31 04:06:00 +00:00
ed346f2ed5
Avoid unnecessarily casting away const.
...
llvm-svn: 46590
2008-01-31 01:01:48 +00:00
9ba4d76816
Rename ISD::FLT_ROUNDS to ISD::FLT_ROUNDS_ to avoid conflicting
...
with the real FLT_ROUNDS (defined in <float.h>).
llvm-svn: 46587
2008-01-31 00:41:03 +00:00
3646fdda67
Create a new class, MemOperand, for describing memory references
...
in the backend. Introduce a new SDNode type, MemOperandSDNode, for
holding a MemOperand in the SelectionDAG IR, and add a MemOperand
list to MachineInstr, and code to manage them. Remove the offset
field from SrcValueSDNode; uses of SrcValueSDNode that were using
it are all all using MemOperandSDNode now.
Also, begin updating some getLoad and getStore calls to use the
PseudoSourceValue objects.
Most of this was written by Florian Brander, some
reorganization and updating to TOT by me.
llvm-svn: 46585
2008-01-31 00:25:39 +00:00
a3395a61cc
Treat the label for the first @llvm.dbg.stoppoint the same way as the dbg_func_start label. Make sure nothing else is inserted before them.
...
Note this solution might be somewhat fragile since ISD::LABEL may be used for other
purposes. If that ends up to be an issue, we may need to introduce a different node
for debug labels.
llvm-svn: 46571
2008-01-30 20:08:35 +00:00
29cfb67e28
Even though InsertAtEndOfBasicBlock is an ugly hack it still deserves a proper name. Rename it to EmitInstrWithCustomInserter since it does not necessarily insert
...
instruction at the end.
llvm-svn: 46562
2008-01-30 18:18:23 +00:00
ed17ef7e18
Skip over the label which marks the beginning of the function before inserting prologue code.
...
llvm-svn: 46546
2008-01-30 03:57:33 +00:00
084a1cdcdd
Work in progress. This patch *fixes* x86-64 calls which are modelled as StructRet but really should be return in registers, e.g. _Complex long double, some 128-bit aggregates. This is a short term solution that is necessary only because llvm, for now, cannot model i128 nor call's with multiple results.
...
Status: This only works for direct calls, and only the caller side is done. Disabled for now.
llvm-svn: 46527
2008-01-29 19:34:22 +00:00
2b3bc30420
Handle 'X' constraint in asm's better.
...
llvm-svn: 46485
2008-01-29 02:21:21 +00:00
2e4719ec55
add a note
...
llvm-svn: 46413
2008-01-27 07:31:41 +00:00
Evan Cheng