876dd3ca9e
Treat common as distinct from weak global on Darwin x86.
...
llvm-svn: 51172
2008-05-16 00:52:06 +00:00
29e59ad6c9
Fix typos and comments.
...
llvm-svn: 51165
2008-05-15 22:13:02 +00:00
ef377adca0
Make use of vector load and store operations to implement memcpy, memmove, and memset. Currently only X86 target is taking advantage of these.
...
llvm-svn: 51140
2008-05-15 08:39:06 +00:00
ad2b7a7b97
Silence warnings.
...
llvm-svn: 51129
2008-05-14 20:33:21 +00:00
ce4396bc92
Add CommonLinkage; currently tentative definitions
...
are represented as "weak", but there are subtle differences
in some cases on Darwin, so we need both. The intent
is that "common" will behave identically to "weak" unless
somebody changes their target to do something else.
No functional change as yet.
llvm-svn: 51118
2008-05-14 20:12:51 +00:00
7fc6027873
Detabification. Fixed indentation and spacing.
...
Changed cout to DOUT, and TODOs to FIXMEs.
Other changes as per coding conventions.
llvm-svn: 51105
2008-05-14 11:31:39 +00:00
fbdca96469
Fix typo in ParameterAttribute fields usage. Add an include
...
to make the Cpp backend output compilable.
llvm-svn: 51095
2008-05-14 07:52:03 +00:00
1f8c9ef4cc
Fixed the file description header at the top to remove the developer name.
...
llvm-svn: 51094
2008-05-14 06:50:01 +00:00
6f34ed0d36
Doh. Alignment is in bytes, not in bits.
...
llvm-svn: 51092
2008-05-14 02:49:43 +00:00
eabd647cd5
Change target-specific classes to use more precise static types.
...
This eliminates the need for several awkward casts, including
the last dynamic_cast under lib/Target.
llvm-svn: 51091
2008-05-14 01:58:56 +00:00
03ce206143
add a note
...
llvm-svn: 51062
2008-05-13 19:56:20 +00:00
f8ab712fa9
- Fix the pasto in the fix for a previous pasto.
...
- Incorporate Chris' comment suggestion.
llvm-svn: 51061
2008-05-13 18:59:59 +00:00
d17f58ae6e
add a note
...
llvm-svn: 51060
2008-05-13 18:48:54 +00:00
6645714f16
Fix one more encoding bug.
...
llvm-svn: 51057
2008-05-13 17:52:09 +00:00
595e226085
- Don't treat anyext 16-bit load as a 32-bit load if it's volatile.
...
- Correct a pasto.
llvm-svn: 51054
2008-05-13 16:45:56 +00:00
4394c2376c
Adding files for Microchip's PIC16 target.
...
A brief description about PIC16:
===============================
PIC16 is an 8-bit microcontroller with only one 8-bit register which is the
accumulator. All arithmetic/load/store operations are 8-bit only.
The architecture has two address spaces: program and data. The program memory
is divided into 2K pages and the data memory is divided into banks of 128 byte, with only 80 usable bytes, resulting in an non-contiguous data memory.
It supports direct data memory access (by specifying the address as part of the instruction) and indirect data and program memory access (in an unorthodox fashion which utilize a 16 bit pointer register).
Two classes of registers exist: (8-bit class which is only one
accumulator) (16-bit class, which contains one or more 16 bit
pointer(s))
llvm-svn: 51027
2008-05-13 09:02:57 +00:00
1120279ae6
Instead of a vector load, shuffle and then extract an element. Load the element from address with an offset.
...
pshufd $1, (%rdi), %xmm0
movd %xmm0, %eax
=>
movl 4(%rdi), %eax
llvm-svn: 51026
2008-05-13 08:35:03 +00:00
50f7ef30bb
Fix and encoding error in the psrad xmm, imm8 instruction.
...
llvm-svn: 51020
2008-05-13 01:47:52 +00:00
3f40c69083
On x86, it's safe to treat i32 load anyext as a normal i32 load. Ditto for i8 anyext load to i16.
...
llvm-svn: 51019
2008-05-13 00:54:02 +00:00
d78c400b5b
Clean up the use of static and anonymous namespaces. This turned up
...
several things that were neither in an anonymous namespace nor static
but not intended to be global.
llvm-svn: 51017
2008-05-13 00:00:25 +00:00
b87e63a730
Teach Legalize how to scalarize VSETCC
...
Teach X86 a few more vsetcc patterns. Custom lowering for unsupported ones is next.
llvm-svn: 51009
2008-05-12 23:09:43 +00:00
b980f6fb3d
Xform bitconvert(build_pair(load a, load b)) to a single load if the load locations are at the right offset from each other.
...
llvm-svn: 51008
2008-05-12 23:04:07 +00:00
1e11768a4f
Constify the machine instruction passed into the
...
"is{Trivially,Really}ReMaterializable" methods.
llvm-svn: 51001
2008-05-12 20:54:26 +00:00
d875c3e2fd
Initial X86 codegen support for VSETCC.
...
llvm-svn: 51000
2008-05-12 20:34:32 +00:00
0863b19ae6
Fix a copy+paste bug; pseudo-instructions shouldn't have
...
encoding information.
llvm-svn: 50997
2008-05-12 20:22:45 +00:00
2609d5e779
Refactor isConsecutiveLoad from X86 to TargetLowering so DAG combiner can make use of it.
...
llvm-svn: 50991
2008-05-12 19:56:52 +00:00
cfcb56091b
Add support for vicmp/vfcmp codegen, more legalize support coming.
...
This is necessary to unbreak the build.
llvm-svn: 50988
2008-05-12 19:40:03 +00:00
906716c40f
Fix a compile error on compilers that still want a return value
...
in a non-void function that calls abort.
llvm-svn: 50969
2008-05-12 16:17:19 +00:00
a38e72d247
Add note
...
llvm-svn: 50959
2008-05-11 14:33:15 +00:00
71b9afb053
When transforming a vector_shuffle to a load, the base address must not be an undef.
...
llvm-svn: 50940
2008-05-10 06:46:49 +00:00
3c0e11af64
For now, abort when an ISD::VAARG is encountered on x86-64, rather
...
than silently generate invalid code.
llvm-gcc does not currently use VAArgInst; it lowers va_arg in the
front-end.
llvm-svn: 50930
2008-05-10 01:26:14 +00:00
da2587cedc
Some clean up.
...
llvm-svn: 50929
2008-05-10 00:59:18 +00:00
bb48d55a88
If movl top bits are undef, let it be selected to movlps, etc.
...
llvm-svn: 50928
2008-05-10 00:58:41 +00:00
867af2678f
Add a pattern to do move the low element of a v4f32 and zero extend the rest.
...
llvm-svn: 50922
2008-05-09 23:37:55 +00:00
961339bbdb
Handle a few more cases of folding load i64 into xmm and zero top bits.
...
Note, some of the code will be moved into target independent part of DAG combiner in a subsequent patch.
llvm-svn: 50918
2008-05-09 21:53:03 +00:00
0360ecbec1
Use movq to move low half of XMM register and zero-extend the rest.
...
llvm-svn: 50874
2008-05-08 22:35:02 +00:00
78af38c392
Handle vector move / load which zero the destination register top bits (i.e. movd, movq, movss (addr), movsd (addr)) with X86 specific dag combine.
...
llvm-svn: 50838
2008-05-08 00:57:18 +00:00
e2b0bf43a7
Output correct exception handling and frame info
...
on x86-64 linux. This causes no regressions on
32 bit linux and 32 bit ppc. More tests pass
on 64 bit ppc with no regressions. I didn't
turn on eh on 64 bit linux because the intrinsics
needed to compile the eh runtime aren't done
yet. But if you turn it on and link with the
mainline runtime then eh seems to work fine
on x86-64 linux with this patch. Thanks to
Dale for testing. The main point of the patch
is that if you output that some object is
encoded using 4 bytes you had better not output
8 bytes for it: the patch makes everything
consistent.
llvm-svn: 50825
2008-05-07 19:11:09 +00:00
888594bdf4
Match things like 'armv5tejl-unknown-linux-gnu' for PR2290
...
llvm-svn: 50698
2008-05-06 02:29:28 +00:00
6a2da37c0e
Make several variable declarations static.
...
llvm-svn: 50696
2008-05-06 01:53:16 +00:00
6e2bf7c67e
add a micro optzn.
...
llvm-svn: 50681
2008-05-05 23:19:45 +00:00
310a38d51e
Improved generated code for atomic operators
...
llvm-svn: 50677
2008-05-05 22:56:23 +00:00
dbfcce37fe
Code clean up. No functionality change.
...
llvm-svn: 50675
2008-05-05 22:12:23 +00:00
3e58393c3d
Added addition atomic instrinsics and, or, xor, min, and max.
...
llvm-svn: 50663
2008-05-05 19:05:59 +00:00
b42c28c3dc
Fix IsLinux being uninitialized on non-Linux targets.
...
llvm-svn: 50660
2008-05-05 18:43:07 +00:00
4b0386ce62
Fix 80col violation
...
llvm-svn: 50654
2008-05-05 17:08:59 +00:00
6fd71c6512
Use a dedicated IsLinux flag instead of an ELFLinux TargetType.
...
llvm-svn: 50649
2008-05-05 16:11:31 +00:00
bcde172222
Add AsmPrinter support for emitting a directive to declare that
...
the code being generated does not require an executable stack.
Also, add target-specific code to make use of this on Linux
on x86.
llvm-svn: 50634
2008-05-05 00:28:39 +00:00
9205c8562c
Add General Dynamic TLS model for X86-64. Some parts looks really ugly (look for tlsaddr pattern),
...
but should work. Work is in progress, more models will follow
llvm-svn: 50630
2008-05-04 21:36:32 +00:00
d9481366e3
Select vector shift with non-immediate i32 shift amount operand by first moving the operand into the right register.
...
llvm-svn: 50619
2008-05-04 09:15:50 +00:00
Dale Johannesen