dc445eadc0
Select inline asm memory operands.
...
llvm-svn: 26349
2006-02-24 02:13:31 +00:00
33f4156663
Bump up pattern cost if the resulting instruction is marked
...
usesCustomDAGSchedInserter.
llvm-svn: 26282
2006-02-18 02:33:09 +00:00
5940bc210e
Call InsertISelMapEntry rather than map insertion operator to prevent overly
...
aggrssive inlining. This reduces Select_store frame size from 24k to 10k.
llvm-svn: 26095
2006-02-09 22:12:27 +00:00
9ce762d51f
Match getTargetNode() changes (now returns SDNode* instead of SDOperand).
...
llvm-svn: 26084
2006-02-09 07:16:09 +00:00
6dc90ca172
Change Select() from
...
SDOperand Select(SDOperand N);
to
void Select(SDOperand &Result, SDOperand N);
llvm-svn: 26067
2006-02-09 00:37:58 +00:00
1630c2848f
Hoist all SDOperand declarations within a Select_{opcode}() to the top level
...
to reduce stack memory usage. This is intended to work around the gcc bug.
llvm-svn: 26026
2006-02-07 00:37:41 +00:00
ebf05bea1b
At the end of isel, select a replacement node for each handle that does not
...
have one. This can happen if a load's real uses are dead (i.e. they do not
have uses themselves).
llvm-svn: 26014
2006-02-06 08:12:55 +00:00
308d0090e6
Name change.
...
llvm-svn: 26013
2006-02-06 06:03:35 +00:00
aa26555b25
Handle HANDLENODE: just return itself.
...
llvm-svn: 26011
2006-02-05 08:46:14 +00:00
368f20e53d
Allow more loads to be folded which were previously prevented from happening
...
due to ordering issue. i.e. they were selected for chain use first.
Now at load select time, check if it is being selected for a chain use and if
it has only a single real use. If so, return a HANDLENODE (with the load as
its operand) in its place and record it.
When it is folded or the load is selected for a real use, the isel records it
as the replacement for the HANDLENODE. The replacement is done when all nodes
are selected.
This scheme exposed a couple of problems where cycles can happen. (See comments
in EmitMatchCode() for descriptions of the problems and their workaround /
solutions.) These problems have been resolved with a small compile time
penality.
llvm-svn: 25995
2006-02-05 06:43:12 +00:00
7ab4579c68
Re-committing the last bit of change. It shouldn't break PPC this time.
...
llvm-svn: 25982
2006-02-05 05:22:18 +00:00
586b06281c
Temporarily revert the last change, which breaks PPC and other targets that
...
DO select things.
llvm-svn: 25970
2006-02-04 09:23:06 +00:00
ce87cac555
Complex pattern's custom matcher should not call Select() on any operands.
...
Select them afterwards if it returns true.
llvm-svn: 25968
2006-02-04 08:50:49 +00:00
2bcfc52af6
node predicates add to the complexity of a pattern. This ensures that the
...
X86 backend attempts to match small-immediate versions of instructions before
the full size immediate versions.
llvm-svn: 25937
2006-02-03 18:06:02 +00:00
717db484a5
(store (op (load ...))) folding problem. In the generated matching code,
...
Chain is initially set to the chain operand of store node, when it reaches
load, if it matches the load then Chain is set to the chain operand of the
load.
However, if the matching code that follows this fails, isel moves on to the
next pattern but it does not restore Chain to the chain operand of the store.
So when it tries to match the next store / op / load pattern it would fail on
the Chain == load.getOperand(0) test.
The solution is for each chain operand to get a unique name. e.g. Chain10.
llvm-svn: 25931
2006-02-03 06:22:41 +00:00
88e616d803
If a pattern's root node is a constant, its size should be 3 rather than 2.
...
llvm-svn: 25870
2006-02-01 06:06:31 +00:00
a8821624d4
simplify some code
...
llvm-svn: 25791
2006-01-29 20:01:35 +00:00
1af077c0c7
it is nice not to chop off bits for those blessed with lots of bits
...
llvm-svn: 25766
2006-01-29 05:22:37 +00:00
49f323a90e
make the casts actually cast to the variable type
...
llvm-svn: 25765
2006-01-29 05:17:22 +00:00
c438c51e82
start of the 64bit safety cleanup
...
llvm-svn: 25764
2006-01-29 05:07:04 +00:00
0e352963fd
Emit series of conditionals with &&, emitting stuff like this:
...
if (N1.getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
!CodeGenMap.count(N1.getValue(0)) &&
!CodeGenMap.count(N1.getValue(1))) {
instead of this:
if (N1.getOpcode() == ISD::LOAD) {
if (N1.hasOneUse()) {
if (!CodeGenMap.count(N1.getValue(0))) {
if (!CodeGenMap.count(N1.getValue(1))) {
llvm-svn: 25763
2006-01-29 04:41:05 +00:00
7c0149d1d6
Factor matching code that is common between patterns. This works around
...
GCC not jump-threading across this common code, and produces far nicer
output.
llvm-svn: 25762
2006-01-29 04:25:26 +00:00
d3a63de91e
Split out code generation from analysis from emission
...
llvm-svn: 25759
2006-01-29 02:57:39 +00:00
afe9baeb69
move some code around, no change in the generated code
...
llvm-svn: 25758
2006-01-29 02:43:35 +00:00
5255c6c627
now that we have control over emission of the code, emit the code using nested
...
"if" statements (indenting it appropriately, of course) instead of using goto's.
This inverts the logic for all of the if statements, which makes things simpler
to understand in addition to making the generated code easier to read.
llvm-svn: 25757
2006-01-28 20:43:52 +00:00
4c4da201bf
Change PatternCodeEmitter to emit code into a buffer instead of emitting it
...
directly to the output file. This makes things simple because the code doesn't
have to worry about indentation or the case when there is no goto. It also
allows us to indent the code better without touching everything :)
llvm-svn: 25756
2006-01-28 20:31:24 +00:00
a7d6bbff00
Fit to 80 columns, no functionality change
...
llvm-svn: 25752
2006-01-28 19:06:51 +00:00
e251e92c23
Teach tablegen to generate code that is VC++ warning-free.
...
llvm-svn: 25709
2006-01-27 22:22:28 +00:00
e555a92c8d
(store (op (load ...)), ...)
...
If store's chain operand is load, then use load's chain operand instead. If
it isn't (likely a TokenFactor), then do not allow the folding.
llvm-svn: 25708
2006-01-27 22:13:45 +00:00
5815669251
Teach the dag selectors to select InlineAsm nodes.
...
Aren't we happy the pattern selectors are almost all gone?
llvm-svn: 25666
2006-01-26 23:08:55 +00:00
e9025f1f3b
Another folding problem: if a node r/w chain or flag, don't fold it if it
...
has already been selected. The number of use check is not strong enough since
a node can be replaced with newly created target node. e.g. If the original
node has two uses, when it is selected for one of the uses it is replaced with
another. Each node now has a single use but isel still should not fold it.
llvm-svn: 25651
2006-01-26 19:13:45 +00:00
dc8365d4f3
Add a FIXME comment.
...
llvm-svn: 25635
2006-01-26 02:13:31 +00:00
ecfaa0a1c9
Incoming (and optional) flag bugs. They may be embedded inside a inner node of
...
a pattern. Also, nodes which take incoming flag should not be folded if it has
more than one use.
llvm-svn: 25627
2006-01-26 00:22:25 +00:00
c5c228fa59
Fix an optional in flag bug.
...
llvm-svn: 25590
2006-01-24 20:46:50 +00:00
295e196558
Optional InFlag was not being included in node.
...
llvm-svn: 25588
2006-01-24 20:07:38 +00:00
e272b4ec17
Prevent folding of a node with multiple uses if the node already folds a load!
...
Here is an example where the load ended up being done twice:
%A = global uint 0
uint %test(uint %B, ubyte %C) {
%tmp = load uint *%A;
%X = shl uint %tmp, ubyte %C
%Cv = sub ubyte 32, %C
%Y = shr uint %B, ubyte %Cv
%Z = or uint %Y, %X
store uint %Z, uint* %A
ret uint %Z
}
==>
subl $4, %esp
movl %ebx, (%esp)
movl 8(%esp), %edx
movl A, %eax
movb 12(%esp), %bl
movb %bl, %cl
shldl %cl, %edx, %eax
movb %bl, %cl
shldl %cl, %edx, A
movl (%esp), %ebx
addl $4, %esp
ret
llvm-svn: 25471
2006-01-20 01:11:03 +00:00
9e7fb7b2fc
Bug fix. Flag operand number may be calculated incorrectly.
...
llvm-svn: 25465
2006-01-19 21:57:10 +00:00
a15731cd50
Use pattern information to determine whether the use expects this
...
instruction to produce a result. e.g MUL8m, the instruction does not
produce a explicit result. However it produces an implicit result in
AL which would be copied to a temp. The root operator of the matching
pattern is a mul so the use would expect it to produce a result.
llvm-svn: 25458
2006-01-19 10:12:58 +00:00
acec02ebf5
Prevent unnecessary CopyToReg when the same HW register appears in two spots
...
in the pattern.
llvm-svn: 25437
2006-01-19 01:55:45 +00:00
61864ec3fe
Emit a type matching check for ComplexPatterns.
...
llvm-svn: 25392
2006-01-17 07:36:41 +00:00
a039d439dc
Type inferencing bug
...
llvm-svn: 25337
2006-01-15 10:04:45 +00:00
bd1de84121
Allow transformation from GlobalAddress to TargetGlobalAddress and
...
ExternalSymbol to TargetExternalSymbol.
llvm-svn: 25252
2006-01-12 19:35:54 +00:00
e6300aaabc
GlobalAddress -> TargetGlobalAddress; ExternalSymbol -> TargetExternalSymbol
...
llvm-svn: 25245
2006-01-12 07:54:57 +00:00
31686087cd
Some minor fixes.
...
llvm-svn: 25227
2006-01-11 22:16:13 +00:00
e18ad392d3
Always select target registers to themselves
...
llvm-svn: 25218
2006-01-11 19:52:27 +00:00
3857f6d067
Emit an error instead of an assertion if trying to do bogus things in result patterns.
...
llvm-svn: 25194
2006-01-11 01:33:49 +00:00
4b0623e141
* Remove instruction fields hasInFlag / hasOutFlag and added SNDPInFlag and
...
SNDPOutFlag to DAG nodes. These properties do not belong to target specific
instructions.
* Added DAG node property SNDPOptInFlag. It's same as SNDPInFlag except it's
optional. Used by ret / call, etc.
llvm-svn: 25154
2006-01-09 18:27:06 +00:00
482ef91d26
Pattern complexity calculation fix.
...
llvm-svn: 25133
2006-01-06 22:19:44 +00:00
46634d21e3
Tweak pattern complexity calc.
...
llvm-svn: 25122
2006-01-06 02:30:23 +00:00
6b037909ff
Bug fix wrt chain operand.
...
llvm-svn: 25115
2006-01-06 00:41:12 +00:00
a69bb989f1
Replace fix with one less disruptive to the original code.
...
Also note that GCC 4.1 also correctly flags the syntax error.
llvm-svn: 25076
2006-01-04 03:23:30 +00:00
7d17a6bc86
Tblgen was generating syntactically illegal C++ code like:
...
SDOperand Tmp0,Tmp1,Tmp2,Tmp3,;
GCC has a bug (24907) in which is fails to catch this, but VC++ correctly
notes its illegality, so tblgen must be taught to only generate legal C++.
llvm-svn: 25075
2006-01-04 03:15:19 +00:00
3d38031bef
Remove obsolete comment, make things look a bit nicer
...
llvm-svn: 25070
2006-01-04 00:32:01 +00:00
c29793a077
reduce stack usage of the recursive SelectCode function by out-lining each
...
case of the switch statement into its own method.
llvm-svn: 25069
2006-01-04 00:25:00 +00:00
81e4dbc6a1
Remove my previous ugly hack that tries to reduce the stack space usage
...
of SelectCode to make way for a better solution.
llvm-svn: 25068
2006-01-03 22:55:16 +00:00
def44bec82
HP-UX DVDs are crunchy and good to eat
...
llvm-svn: 25052
2005-12-30 16:41:48 +00:00
336dba6fb1
Add support for generating v4i32 altivec code
...
llvm-svn: 25046
2005-12-30 00:12:56 +00:00
14c53b45f5
Added field noResults to Instruction.
...
Currently tblgen cannot tell which operands in the operand list are results so
it assumes the first one is a result. This is bad. Ideally we would fix this
by separating results from inputs, e.g. (res R32:$dst),
(ops R32:$src1, R32:$src2). But that's a more distruptive change. Adding
'let noResults = 1' is the workaround to tell tblgen that the instruction does
not produces a result. It works for now since tblgen does not support
instructions which produce multiple results.
llvm-svn: 25017
2005-12-26 09:11:45 +00:00
0dc12c38e5
support targetexternalsym
...
llvm-svn: 25005
2005-12-24 23:36:59 +00:00
72aaf8e374
* Support for hasInFlag and hasOutFlag (on instructions). Remove nameless FLAG
...
support which is fragile.
* Fixed a number of bugs.
llvm-svn: 24996
2005-12-23 22:11:47 +00:00
d834d495b2
silence some bogus gcc warnings
...
llvm-svn: 24962
2005-12-22 20:37:36 +00:00
a87d743912
Attempt to fix a crash on WIN32.
...
llvm-svn: 24936
2005-12-22 02:35:21 +00:00
991bc6d6ba
* Added support for FLAG - a special nameless flag register. Can be used as
...
either an operand or a result.
* Fixed some more flag / chain bugs.
llvm-svn: 24933
2005-12-22 02:24:50 +00:00
f646926ecf
Allows instructions which no explicit operands. e.g. X86 RET which has but
...
an implicit flag operand.
llvm-svn: 24916
2005-12-21 20:20:49 +00:00
812a56e888
Eliminate some GCC warnings from the generated code
...
llvm-svn: 24897
2005-12-21 05:31:05 +00:00
4bf64a8ba4
Fix the semantic of Requires<[cond]> to mean if (!cond) goto PXXFail;
...
llvm-svn: 24883
2005-12-20 20:08:01 +00:00
777bb6eb45
This ugly patch works around a GCC bug where it is compiling SelectCode to
...
use too much stack space, overflowing the stack for large functions. Instead
of emitting new SDOperands in each match block, we emit some common ones at
the top of SelectCode then reuse them when possible.
This reduces the stack size of SelectCode from 28K to 21K. Note that GCC
compiles it to 512 bytes :-/
I've filed GCC PR 25505 to track this.
llvm-svn: 24882
2005-12-20 19:41:03 +00:00
9696f63d3e
Now support instructions with implicit write to non-flag registers.
...
llvm-svn: 24878
2005-12-20 07:37:41 +00:00
fe90b604a4
Lefted out a fix in the previous check in.
...
llvm-svn: 24873
2005-12-20 00:06:17 +00:00
19b9f15377
Fix another bug related to chain / flag.
...
llvm-svn: 24868
2005-12-19 22:40:04 +00:00
9bd85c2f19
Fixes for a number of bugs: save flag results in CodeGenMap, folded chains
...
may not all have ResNo == 0.
llvm-svn: 24858
2005-12-19 07:18:51 +00:00
f7ae0a95fe
Handle basic block nodes
...
llvm-svn: 24833
2005-12-18 21:05:44 +00:00
abb11cc83e
More fixes for Selection of copyto/fromreg with a flag
...
llvm-svn: 24829
2005-12-18 15:45:51 +00:00
fc3d4f8fd8
Select copytoreg and copyfromreg nodes that have flag operands correctly.
...
llvm-svn: 24827
2005-12-18 15:28:25 +00:00
e22f9181f7
Support for read / write from explicit registers with FlagVT type.
...
llvm-svn: 24753
2005-12-17 01:19:28 +00:00
d296a43f96
Added support to specify predicates.
...
llvm-svn: 24715
2005-12-14 22:02:59 +00:00
6a31777c8e
Skip over srcvalue nodes when generating ISEL code.
...
llvm-svn: 24704
2005-12-14 02:21:57 +00:00
6148153230
Bug fix: CodeGenMap[N] = ... -> CodeGenMap[N.getValue(0)] = ...
...
llvm-svn: 24680
2005-12-12 23:45:21 +00:00
7e4c01eee3
At top of generated isel SelectCode() is this:
...
if (!N.Val->hasOneUse()) {
std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(N);
if (CGMI != CodeGenMap.end()) return CGMI->second;
}
Suppose a DAG like this:
X
^ ^
/ \
USE1 USE2
Suppose USE1 is being selected first and during which X is selected and
returned a new node. After this, USE1 is no longer an use of X. During USE2
selection, X will be selected again since it has only one use!
The fix is to always query CodeGenMap.
llvm-svn: 24679
2005-12-12 23:22:48 +00:00
cdb16ef6f3
Bug fix: finding the correct incoming chain for pattern with nested src operand. And a minor change to make output code slightly more readible.
...
llvm-svn: 24669
2005-12-12 19:37:43 +00:00
4e56db674c
Add support for TargetConstantPool nodes to the dag isel emitter, and use
...
them in the PPC backend, to simplify some logic out of Select and
SelectAddr.
llvm-svn: 24657
2005-12-10 02:36:00 +00:00
0da396ffe2
Stop emitting a redudant type check for complex pattern node.
...
llvm-svn: 24655
2005-12-10 01:57:33 +00:00
bac252c289
For instructions which produce no result, e.g. store, chain's Resno == 0.
...
llvm-svn: 24652
2005-12-10 00:09:17 +00:00
433573f4c6
Add a new SDTCisPtrTy constraint, which indicates that an operand must have
...
the same type as the pointer type for a target.
llvm-svn: 24649
2005-12-09 22:57:42 +00:00
499ab2a9fa
* Do not allow nodes which produce chain results (e.g. loads) to be folded if
...
it has more than one real use (non-chain uses).
* Record folded chain producing node in CodeGenMap.
* Do not fold a chain producing node if it has already been selected as an
operand of a chain use.
llvm-svn: 24647
2005-12-09 22:45:35 +00:00
c1f911a238
Prevent folding of instructions which produce chains that have more than 1 real use
...
llvm-svn: 24643
2005-12-09 06:06:08 +00:00
f423a17e33
* Make sure complex pattern operands are selected first since their select
...
functions can return false and causing the instruction pattern match to fail.
* Code clean up.
llvm-svn: 24642
2005-12-09 00:48:42 +00:00
c9a620060b
* Added an explicit type field to ComplexPattern.
...
* Renamed MatchingNodes to RootNodes.
llvm-svn: 24636
2005-12-08 02:14:08 +00:00
9b9567bfb5
Added support for ComplexPattern. These are patterns that require C++ pattern
...
matching code that is not currently auto-generated by tblgen, e.g. X86
addressing mode. Selection routines for complex patterns can return multiple operands, e.g. X86 addressing mode returns 4.
llvm-svn: 24634
2005-12-08 02:00:36 +00:00
0fe76d1585
* Infer instruction property hasCtrlDep from pattern if it has one.
...
* Fixed a bug related to hasCtrlDep property use.
llvm-svn: 24610
2005-12-05 23:08:55 +00:00
ba369ae8f1
Implement PR673: for explicit register references, use type information
...
if available
llvm-svn: 24597
2005-12-05 02:36:37 +00:00
d49489f01e
Generate code to silence bogus GCC warnings.
...
llvm-svn: 24593
2005-12-05 00:48:51 +00:00
f02bb9af8b
* Commit the fix (by Chris) for a tblgen type inferencing bug.
...
* Enhanced tblgen to handle instructions which have chain operand and writes a
chain result.
* Enhanced tblgen to handle instructions which produces no results. Part of
the change is a temporary hack which relies on instruction property (e.g.
isReturn, isBranch). The proper fix would be to change the .td syntax to
separate results dag from ops dag.
llvm-svn: 24587
2005-12-04 08:18:16 +00:00
006bb04f3a
Support multiple ValueTypes per RegisterClass, needed for upcoming vector
...
work. This change has no effect on generated code.
llvm-svn: 24563
2005-12-01 04:51:06 +00:00
fed83adbe3
Teach tblgen to accept register source operands in patterns, e.g.
...
def SHL8rCL : I<0xD2, MRM4r, (ops R8 :$dst, R8 :$src),
"shl{b} {%cl, $dst|$dst, %CL}",
[(set R8:$dst, (shl R8:$src, CL))]>, Imp<[CL],[]>;
This generates a CopyToReg operand and added its 2nd result to the shl as
a flag operand.
llvm-svn: 24557
2005-12-01 00:18:45 +00:00
cdf2c67888
Stop checking the ValueType of the CodeGenInstruction. Instead, use the
...
ValueType from the RegisterClass or Operands. This step is necessary to
allow RegisterClasses to have multiple ValueTypes.
llvm-svn: 24555
2005-12-01 00:06:14 +00:00
3e63dc00da
Make the code generated by tblgen return the result of SelectNodeTo, to
...
permit future changes.
llvm-svn: 24553
2005-11-30 23:08:45 +00:00
c8af0cb893
Better error message when unrecognized opcode is seen.
...
llvm-svn: 24519
2005-11-29 18:44:58 +00:00
a70c7dff2e
Validate that the input to 'Pat' patterns is sane.
...
llvm-svn: 24393
2005-11-17 17:43:52 +00:00
2a230e1c1a
teach tblgen to be smart enough to handle tglobaladdr nodes
...
llvm-svn: 24391
2005-11-17 07:39:45 +00:00
b22950df6c
fix a tblgen bug that Evan ran into, where we would lose the '$src' name
...
on patterns like "(set R32:$dst, (i32 imm:$src))"
llvm-svn: 24383
2005-11-16 23:14:54 +00:00
64209fd14b
Reject integer literals that are out of range for their type.
...
llvm-svn: 24162
2005-11-03 05:46:11 +00:00
590176be16
Add support for immediates directly in the pattern, this allows itanium to
...
define:
def : Pat<(i1 1), (CMPEQ r0, r0)>;
llvm-svn: 24149
2005-11-02 06:49:14 +00:00
d91df9d941
Make negative immediates in patterns work correctly, silence some warnings
...
building the itanium backend.
llvm-svn: 24095
2005-10-29 16:39:40 +00:00
7ad0bed89f
Rename Record::getValueAsListDef to getValueAsListOfDefs, to more accurately
...
reflect what it is.
Convert some more code over to use it.
llvm-svn: 24072
2005-10-28 22:49:02 +00:00
802bd8d94f
Use the new interface Jim added
...
llvm-svn: 24071
2005-10-28 22:43:25 +00:00
f277ac7caa
Condcodes are in the ISD namespace
...
llvm-svn: 24010
2005-10-26 17:02:02 +00:00
611b0c634c
Add support for CondCode's
...
llvm-svn: 24008
2005-10-26 16:59:37 +00:00
d980c46f52
Emit some boilerplate for targets
...
llvm-svn: 23983
2005-10-25 20:35:14 +00:00
8bda5afd91
Make tblgen emit:
...
tblgen: In ZAPNOTi: Cannot use 'IZAPX' in an input pattern!
for a bad pattern, instead of an ugly assertion.
llvm-svn: 23854
2005-10-21 01:19:59 +00:00
c9ad735e78
add support for literal immediates in patterns to match, allowing us to
...
write things like this:
def : Pat<(add GPRC:$in, 12),
(ADD12 GPRC:$in)>;
Andrew: if this isn't enough or doesn't work for you, please lemme know.
llvm-svn: 23819
2005-10-19 04:41:05 +00:00
7f6f565846
Add basic support for integer constants in pattern results.
...
llvm-svn: 23817
2005-10-19 04:30:56 +00:00
b8014e10ae
Add support for patterns that have physical registers in them. Testcase:
...
def : Pat<(trunc G8RC:$in),
(OR8To4 G8RC:$in, X0)>;
Even though this doesn't make any sense on PPC :)
llvm-svn: 23815
2005-10-19 02:07:26 +00:00
c8f899f98d
Asserting here is to violent
...
llvm-svn: 23814
2005-10-19 01:55:23 +00:00
8baf5043a8
Nate wants to define 'Pat's which turn into instructions that don't have
...
patterns. Certainly a logical request.
llvm-svn: 23810
2005-10-19 01:27:22 +00:00
ed653cbe43
Duraid pointed out that it is impolite to emit PPC:: into the IA64 backend
...
llvm-svn: 23780
2005-10-18 04:41:01 +00:00
825298b060
Make the generated code significantly more memory efficient, by using
...
SelectNodeTo instead of getTargetNode when possible.
llvm-svn: 23758
2005-10-16 01:41:58 +00:00
6b22d2554a
Implement the last major missing piece in the DAG isel generator: when emitting
...
a pattern match, make sure to emit the (minimal number of) type checks that
verify the pattern matches this specific instruction. This allows FMA32
patterns to not match double expressions for example.
llvm-svn: 23748
2005-10-15 21:34:21 +00:00
c4db8f4163
Now that we have int/fp lattice values, implement the SDTCisOpSmallerThanOp
...
type constraint. This lets tblgen realize that it doesn't need any dynamic
type checks for fextend/fround on PPC (and many other targets), because there
are only two fp types.
llvm-svn: 23730
2005-10-14 06:25:00 +00:00
ecaf56b21a
Fairly serious rework of the typing code to add new int/fp lattice values.
...
Overall, no functionality change yet though.
llvm-svn: 23729
2005-10-14 06:12:03 +00:00
cdf483556f
simplify the code a bit
...
llvm-svn: 23728
2005-10-14 05:08:37 +00:00
4892df38f3
Add basic support for recognizing a new SDTCisOpSmallerThanOp type constraint
...
llvm-svn: 23725
2005-10-14 04:53:53 +00:00
7b0275ba8c
Implement a couple of new (important) features.
...
1. If an operation has to be int or fp and the target only supports one
int or fp type, relize that the op has to have that type.
2. If a target has operations on multiple types, do not emit matching code
for patterns involving those operators, since we do not emit the code to
check for them yet. This prevents PPC from generating FP ops currently.
Also move some code around into more logical places.
llvm-svn: 23724
2005-10-14 04:11:13 +00:00
366fe04301
Teach tablegen to reassociate operators when possible. This allows it to
...
find all of teh pattern matches for EQV from one definition
llvm-svn: 23529
2005-09-29 22:36:54 +00:00
e86824e57a
Teach tblgen to build permutations of instructions, so that the target author
...
doesn't have to specify them manually. It currently handles associativity,
e.g. knowing that (X*Y)+Z also matches X+(Y*Z) and will be extended in
the future.
It is smart enough to not introduce duplicate patterns or patterns that can
never match.
llvm-svn: 23526
2005-09-29 19:28:10 +00:00
492e70f4ec
add support for an associative marker
...
llvm-svn: 23502
2005-09-28 20:58:06 +00:00
8bb25cd68a
Emit an error if instructions or patterns are defined but can never match.
...
Currently we check that immediate values live on the RHS of commutative
operators. Defining ORI like this, for example:
def ORI : DForm_4<24, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
"ori $dst, $src1, $src2",
[(set GPRC:$dst, (or immZExt16:$src2, GPRC:$src1))]>;
results in:
tblgen: In ORI: Instruction can never match: Immediate values must be on the RHS of commutative operators!
llvm-svn: 23501
2005-09-28 19:27:25 +00:00
f74c30c281
collect commutativity information
...
llvm-svn: 23499
2005-09-28 18:28:29 +00:00
3622f15491
Prefer cheaper patterns to more expensive ones. Print the costs to the generated
...
file
llvm-svn: 23492
2005-09-28 17:57:56 +00:00
75b4c5d868
Select Constant nodes to TargetConstant nodes
...
llvm-svn: 23488
2005-09-28 16:58:06 +00:00
d455c36c91
memoize the assert results
...
llvm-svn: 23457
2005-09-26 22:10:24 +00:00
c9153266c6
Emit the switch stmt cases in alphabetical order instead of pointer order,
...
which is not stable.
llvm-svn: 23456
2005-09-26 21:59:35 +00:00
d5de8544f8
implement a fixme: only select values once, even if used multiple times.
...
llvm-svn: 23454
2005-09-26 21:53:26 +00:00
23b1d28e69
Fix VC++ build errors.
...
llvm-svn: 23431
2005-09-25 19:04:43 +00:00
cc1d38160d
memoize translations
...
llvm-svn: 23419
2005-09-24 00:50:51 +00:00
0afb14cade
Teach the DAG isel generator to emit code that creates nodes.
...
Fix a few corner cases parsing things like (i32 imm:$foo)
llvm-svn: 23417
2005-09-24 00:40:24 +00:00
cd093e868e
Emit better code (no more copies for var references), and support DAG patterns
...
(e.g. things like rotates).
llvm-svn: 23416
2005-09-23 23:16:51 +00:00
8ffb99b4fe
Fix a fixme by passing around SDOperand's instead of SDNode*'s
...
llvm-svn: 23415
2005-09-23 21:53:45 +00:00
cc8a564cb1
Emit code that matches the incoming DAG pattern and checks predicates.
...
This does not check that types match yet, but PPC only has one integer type
;-).
This also doesn't have the code to build the resultant dag.
llvm-svn: 23414
2005-09-23 21:33:23 +00:00
323a47970e
emit information about the order patterns are to be matched.
...
llvm-svn: 23413
2005-09-23 20:52:47 +00:00
abb430bad2
start filling in the switch stmt
...
llvm-svn: 23412
2005-09-23 19:36:15 +00:00
7884fffb00
Fix a minor bug, add comments
...
llvm-svn: 23370
2005-09-16 00:29:46 +00:00
59e96143a2
teach the type inference code how to infer types for instructions and node
...
xforms. Run type inference on result patterns, so we always have fully typed
results (and to catch errors in .td files).
llvm-svn: 23369
2005-09-15 22:23:50 +00:00
fedd9a5e1d
put instructions into a map instead of a vector for quick lookup
...
llvm-svn: 23368
2005-09-15 21:57:35 +00:00
f38ce8f756
when parsing instructions remember information about the types taken and
...
returned.
llvm-svn: 23367
2005-09-15 21:51:12 +00:00
a0a986c9ae
Start parsing "Pattern" nodes
...
llvm-svn: 23365
2005-09-15 21:42:00 +00:00
f79ad4cb32
rename a couple of methods, add structure for pattern parsing
...
llvm-svn: 23364
2005-09-15 02:38:02 +00:00
a155256a71
Verify that xform functions only occur in logical places
...
llvm-svn: 23363
2005-09-14 23:05:13 +00:00
991c7c973a
Promote xform fns to be explicit nodes in result patterns, and clean off
...
predicates since they will have already matched at this point.
llvm-svn: 23362
2005-09-14 23:01:59 +00:00
bc7aabce12
start building the instruction dest pattern correctly. Change the xform
...
functions to preserve the Record for the xform instead of making it into a
function name.
llvm-svn: 23361
2005-09-14 22:55:26 +00:00
e389c6154e
catch unnamed inputs
...
llvm-svn: 23360
2005-09-14 22:06:36 +00:00
030f876cf2
check that there are no unexpected operands
...
llvm-svn: 23359
2005-09-14 21:59:34 +00:00
3ced3f8b82
force all instruction operands to be named.
...
llvm-svn: 23358
2005-09-14 21:13:50 +00:00
24ae3494f0
fix a broke range check
...
llvm-svn: 23354
2005-09-14 21:04:12 +00:00
3ba60bf644
Parse significantly more of the instruction pattern, now collecting and
...
verifying information about the operands.
llvm-svn: 23353
2005-09-14 20:53:42 +00:00
22e60c99ce
Verify that set destinations occur first in the instruction operand list.
...
llvm-svn: 23351
2005-09-14 18:19:25 +00:00
1c8d6ce015
remove some code that isn't ready for prime time
...
llvm-svn: 23346
2005-09-14 06:03:10 +00:00
3361eab530
Switch to a slightly more structured representation for instructions
...
llvm-svn: 23345
2005-09-14 04:03:16 +00:00
4cfcb544bf
Add some more checking/verification code
...
llvm-svn: 23344
2005-09-14 02:11:12 +00:00
4c7b604091
start parsing instructions into patterns, start doing many more checks of
...
'set's.
llvm-svn: 23343
2005-09-14 00:09:24 +00:00
bb9b01644e
don't emit the namespace inside the class!
...
llvm-svn: 23341
2005-09-13 22:05:02 +00:00
70a7234111
Emit code suitable for emission into the ISel class, allowing us to use/define
...
methods.
llvm-svn: 23340
2005-09-13 22:03:37 +00:00
3556d849da
continue xform function parsing
...
llvm-svn: 23338
2005-09-13 21:59:15 +00:00
2617de498d
Start parsing node transformation information
...
llvm-svn: 23337
2005-09-13 21:51:00 +00:00
f365e25a5c
completely eliminate TreePattern::PatternType
...
llvm-svn: 23335
2005-09-13 21:20:49 +00:00
ce2173d098
add an accessor to provide more checking
...
llvm-svn: 23289
2005-09-09 01:15:01 +00:00
7a82c06f34
use new accessors to simplify code. Add checking to make sure top-level instr
...
definitions are void
llvm-svn: 23288
2005-09-09 01:11:44 +00:00
debd6e95ab
Fix incorrect comment
...
llvm-svn: 23285
2005-09-08 23:26:30 +00:00
d7d31f3b06
Implement a complete type inference system for dag patterns, based on the
...
constraints defined in the DAG node definitions in the .td files. This
allows us to infer (and check!) the types for all nodes in the current
ppc .td file. For example, instead of:
Inst pattern EQV: (set GPRC:i32:$rT, (xor (xor GPRC:i32:$rA, GPRC:i32:$rB), (imm)<<Predicate_immAllOnes>>))
we now fully infer:
Inst pattern EQV: (set:void GPRC:i32:$rT, (xor:i32 (xor:i32 GPRC:i32:$rA, GPRC:i32:$rB), (imm:i32)<<Predicate_immAllOnes>>))
from: (set GPRC:$rT, (not (xor GPRC:$rA, GPRC:$rB)))
llvm-svn: 23284
2005-09-08 23:22:48 +00:00
1c33104010
Parse information about type constraints on SDNodes
...
llvm-svn: 23281
2005-09-08 21:27:15 +00:00
a3b89dfcef
use node info in the one place we currently use it
...
llvm-svn: 23280
2005-09-08 21:04:46 +00:00
35bcd1488a
start parsing SDNode info records
...
llvm-svn: 23279
2005-09-08 21:03:01 +00:00
399f59f643
Keep names even when inlining. This allows us to realize that ADDI is:
...
(set GPRC:i32:$rD, (add GPRC:i32:$rA, (imm)<<Predicate_immSExt16>>:$imm))
not:
(set GPRC:i32:$rD, (add GPRC:i32:$rA, (imm)<<Predicate_immSExt16>>))
(we keep the ":$imm")
llvm-svn: 23269
2005-09-08 17:45:12 +00:00
d2a5b366f5
Initial cut of the dag isel generator. This is still very much a work in
...
progress. It correctly parses instructions and pattern fragments and glues
together pattern fragments into instructions.
The only code it generates currently is some boilerplate code for things
like the EntryNode.
llvm-svn: 23261
2005-09-07 23:44:43 +00:00
Chris Lattner