Commit Graph

68 Commits

Author SHA1 Message Date
Jim Grosbach e9cc901814 Refact ARM Thumb1 tMOVr instruction family.
Merge the tMOVr, tMOVgpr2tgpr, tMOVtgpr2gpr, and tMOVgpr2gpr instructions
into tMOVr. There's no need to keep them separate. Giving the tMOVr
instruction the proper GPR register class for its operands is sufficient
to give the register allocator enough information to do the right thing
directly.

llvm-svn: 134204
2011-06-30 23:38:17 +00:00
Jim Grosbach b98ab91e39 Thumb1 register to register MOV instruction is predicable.
Fix a FIXME and allow predication (in Thumb2) for the T1 register to
register MOV instructions. This allows some better codegen with
if-conversion (as seen in the test updates), plus it lays the groundwork
for pseudo-izing the tMOVCC instructions.

llvm-svn: 134197
2011-06-30 22:10:46 +00:00
Cameron Zwarich 033026ffc0 Update an insertion point iterator after replacing a return instruction with a
tail call pseudoinstruction. This fixes <rdar://problem/9624333>.

llvm-svn: 133227
2011-06-17 02:16:43 +00:00
Jim Grosbach dca8531821 Fix coordination for using R4 in Thumb1 as a scratch for SP restore.
The logic for reserving R4 for use as a scratch needs to match that for
actually using it. Also, it's not necessary for immediate <=508, so adjust
the value checked.

llvm-svn: 132934
2011-06-13 21:18:25 +00:00
Evan Cheng c0d2004e3c In Thumb2 mode, lower frame indix references to:
add <rd>, sp, #<imm8>
ldr <rd>, [sp, #<imm8>]
When the offset from sp is multiple of 4 and in range of 0-1020.
This saves code size by utilizing 16-bit instructions.

rdar://9321541

llvm-svn: 129971
2011-04-22 01:42:52 +00:00
Jim Grosbach 3af6fe66b9 Clean up ARM tail calls a bit. They're pseudo-instructions for normal branches.
Also more cleanly separate the ARM vs. Thumb functionality. Previously, the
encoding would be incorrect for some Thumb instructions (the indirect calls).

llvm-svn: 127637
2011-03-15 00:30:40 +00:00
Anton Korobeynikov e7410dd0d5 Preliminary support for ARM frame save directives emission via MI flags.
This is just very first approximation how the stuff should be done
(e.g. ARM-only for now). More to follow.

llvm-svn: 127101
2011-03-05 18:43:32 +00:00
Evan Cheng a921dc5860 Fix typo.
llvm-svn: 126467
2011-02-25 01:29:29 +00:00
Evan Cheng 70d29634a9 Each prologue may have multiple vpush instructions to store callee-saved
D registers since the vpush list may not have gaps. Make sure the stack
adjustment instruction isn't moved between them. Ditto for vpop in
epilogues.

Sorry, can't reduce a small test case.
rdar://9043312

llvm-svn: 126457
2011-02-25 00:24:46 +00:00
Bob Wilson 9cd0b581b8 Remove unused bitvectors that record ARM callee-saved registers.
llvm-svn: 125534
2011-02-14 23:40:38 +00:00
Evan Cheng d6093ff4cb Don't merge restore with tail call instruction.
llvm-svn: 124167
2011-01-25 01:28:33 +00:00
Jeffrey Yasskin 249fcd4499 Remove unused variables found by gcc-4.6's -Wunused-but-set-variable.
llvm-svn: 123707
2011-01-18 00:51:23 +00:00
Evan Cheng 572756ac11 Spill R4 if it's going to be used to restore SP from FP.
llvm-svn: 123567
2011-01-16 05:14:33 +00:00
Jakob Stoklund Olesen 4bc5e38960 Teach frame lowering to ignore debug values after the terminators.
llvm-svn: 123399
2011-01-13 21:28:52 +00:00
Bob Wilson 657f227d08 Tidy comments, indentation, and 80-column violations.
llvm-svn: 123397
2011-01-13 21:10:12 +00:00
Evan Cheng e45d685895 Clean up ARM subtarget code by using Triple ADT.
llvm-svn: 123276
2011-01-11 21:46:47 +00:00
Eric Christopher d5bbeba8d0 Expand on the safeness of restoring the sp from the fp a bit more.
llvm-svn: 123193
2011-01-10 23:10:59 +00:00
Anton Korobeynikov 2f93128109 Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs and fixes here and there.
llvm-svn: 123170
2011-01-10 12:39:04 +00:00