Commit Graph

397276 Commits

Author SHA1 Message Date
Philip Reames 58582bae63 Revert "[SCEV] Infer nsw/nuw from nw for addrecs"
This reverts commit 914836b1c8.  Further comments on review came up after initial approval.  Reverting while addressing.
2021-08-24 09:28:37 -07:00
Andrei Elovikov f387a36178 [NFC][clang] Move remaining part of X86Target.def to llvm/Support/X86TargetParser.def
Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D108422
2021-08-24 09:16:31 -07:00
Jessica Paquette 67d4dd5c07 [AArch64][GlobalISel] Select @llvm.aarch64.neon.ld4.*
Reuse the selection code from the ld2 case. This is similar to how SDAG handles
things in AArch64ISelDAGToDAG. (See SelectLoad)

This fell back ~100 times while building clang with GISel enabled for AArch64.

Factoring out the gross subreg copy part ought to make selecting the rest of
this family fairly easy.

Differential Revision: https://reviews.llvm.org/D108600
2021-08-24 09:03:49 -07:00
Philip Reames 1e07f19bfc Revert "Special case common branch patterns in breakLoopBackedge"
This reverts commit aec08e8600.

Several problems have been reported with malformed loopinfo after this change, see discussion on https://reviews.llvm.org/rGaec08e86004b.
2021-08-24 08:53:42 -07:00
Philip Reames 914836b1c8 [SCEV] Infer nsw/nuw from nw for addrecs
If we no an addrec doesn't self-wrap, the increment is strictly positive, and the start value is the smallest representable value, then we know that the corresponding wrap type can not occur.

Differential Revision: https://reviews.llvm.org/D108601
2021-08-24 08:53:21 -07:00
Aart Bik fda176892e [mlir][sparse] use new permutation utility to avoid codedup
Reviewed By: ftynse

Differential Revision: https://reviews.llvm.org/D108636
2021-08-24 08:48:17 -07:00
Simon Pilgrim 307890f85b [X86] Freeze vXi8 shl(x,1) -> add(x,x) vector fold (PR50468)
We don't have any vXi8 shift instructions (other than on XOP which is handled separately), so replace the shl(x,1) -> add(x,x) fold with shl(x,1) -> add(freeze(x),freeze(x)) to avoid the undef issues identified in PR50468.

Split off from D106675 as I'm still looking at whether we can fix the vXi16/i32/i64 issues with the D106679 alternative.

Differential Revision: https://reviews.llvm.org/D108139
2021-08-24 16:08:24 +01:00
Aart Bik a643bd3189 [mlir] add permutation utility
I found myself typing this code several times at different places
by now, so time to make this a general utility instead. Given
a permutation, it returns the permuted position of the input,
for example (i,j,k) -> (k,i,j) yields position 1 for input 0.

Reviewed By: ftynse

Differential Revision: https://reviews.llvm.org/D108347
2021-08-24 08:07:40 -07:00
Simon Pilgrim 194b08000c [DAG] LoadedSlice::canMergeExpensiveCrossRegisterBankCopy - replace getABITypeAlign with allowsMemoryAccess (PR45116)
One of the cases identified in PR45116 - we don't need to limit load combines to ABI alignment, we can use allowsMemoryAccess - which tests using getABITypeAlign, but also checks if a target permits (fast) misaligned memory loads by checking allowsMisalignedMemoryAccesses as a fallback.
2021-08-24 15:28:30 +01:00
Whisperity 8d50a847d4 [clang-tidy] Hotfix default parameter value in 'bugprone-easily-swappable-parameters'
As identified by @RKSimon, there was a missing comma in the default
value for the "ignored parameter type suffixes" array, resulting in
bogus concatenation of two elements.
2021-08-24 16:10:19 +02:00
Kazu Hirata c528c9490b [InstCombine] Remove CreateNonTerminatorUnreachable (NFC)
The function was introduced without a use on Jun 3, 2020 in commit
2a6c871596.  Note that the identical
function is defined in InstCombineInternal.h without static, which is
in use.
2021-08-24 06:52:15 -07:00
Benson Chu 9a5f388850 [AST] Pick last tentative definition as the acting definition
Clang currently picks the second tentative definition when
VarDecl::getActingDefinition is called.

This can lead to attributes being dropped if they are attached to
tentative definitions that appear after the second one. This is
because VarDecl::getActingDefinition loops through VarDecl::redecls
assuming that the last tentative definition is the last element in the
iterator. However, it is the second element that would be the last
tentative definition.

This changeset modifies getActingDefinition to iterate through the
declaration chain in reverse, so that it can immediately return when
it encounters a tentative definition.

Differential Revision: https://reviews.llvm.org/D99732
2021-08-24 08:51:50 -05:00
Simon Pilgrim 6de0b55188 [DAG] TransformFPLoadStorePair - replace getABITypeAlign with allowsMemoryAccess (PR45116)
One of the cases identified in PR45116 - we don't need to limit load combines (in this case for fp->int load/store copies) to ABI alignment, we can use allowsMemoryAccess - which tests using getABITypeAlign, but also checks if a target permits (fast) misaligned memory loads by checking allowsMisalignedMemoryAccesses as a fallback.

Differential Revision: https://reviews.llvm.org/D108318
2021-08-24 13:11:27 +01:00
Simon Pilgrim e431b280c9 [DAG] CombineConsecutiveLoads - replace getABITypeAlign with allowsMemoryAccess (PR45116)
One of the cases identified in PR45116 - we don't need to limit load combines (in this case for ISD::BUILD_PAIR) to ABI alignment, we can use allowsMemoryAccess - which tests using getABITypeAlign, but also checks if a target permits (fast) misaligned memory loads by checking allowsMisalignedMemoryAccesses as a fallback.

This helps in particular for 32-bit X86 cases loading 64-bit size data, reducing codegen diffs vs x86_64.

Differential Revision: https://reviews.llvm.org/D108307
2021-08-24 12:31:22 +01:00
Paul Herman f717060461 Fix documentation and snippets for the handle attributes; NFC 2021-08-24 07:11:38 -04:00
Sindhu Chittireddy 98339f14a0 Avoid nullptr dereferencing of 'Constraint'; NFC
Klocwork static code analysis exposed this bug:
Pointer 'Constraint' returned from call to function
'cast_or_null<clang::ConceptSpecializationExpr,clang::Expr>' may
be NULL and will be dereferenced in the statement following it

Replace 'cast_or_null' with 'cast' so that the latter can assert
when it encounters a NULL.

This also removes an 'assert' that is covered by the previous
call to 'cast<>'.
2021-08-24 07:08:18 -04:00
Matthias Springer ebf35370ff [mlir][tensor] Insert explicit tensor.cast ops for insert_slice src
If additional static type information can be deduced from a insert_slice's size operands, insert an explicit cast of the op's source operand.

This enables other canonicalization patterns that are matching for tensor_cast ops such as `ForOpTensorCastFolder` in SCF.

Differential Revision: https://reviews.llvm.org/D108617
2021-08-24 19:45:04 +09:00
Matthias Springer 0c36082963 [mlir][SCF] Use symbols in loop peeling rewrite
Use symbols in the affine map instead of dims. Dims should not be divided.

Differential Revision: https://reviews.llvm.org/D108431
2021-08-24 19:39:19 +09:00
Krasimir Georgiev befb9dc369 [clang-format] keep TypeScript argument decorators in line
As a follow-up from https://reviews.llvm.org/D108538, ensure TypeScript
argument decorators are kept in line with the argument.

Reviewed By: MyDeveloperDay

Differential Revision: https://reviews.llvm.org/D108620
2021-08-24 12:37:08 +02:00
Dawid Jurczak 2e8534beb2 [NFC][LoopIdiom] Add reproducer of wrong memmove transformation
That's precommit test for D107964.

Differential Revision: https://reviews.llvm.org/D108537
2021-08-24 12:00:24 +02:00
Ricky Taylor 47f52f989b [M68k][AsmParser] Support parsing register masks & fix printing them
Fixes PR51580.

Register masks will now be printed as 'movem.l (%sp), %a0-%a5/%d5'
for example and can now be parsed in the same format.

Previously the printed syntax was 'movem.l (%sp), %a0-%a5,%d', which
didn't match prior art and was too ambiguous to easily parse.

Differential Revision: https://reviews.llvm.org/D108597
2021-08-24 10:40:02 +01:00
Jeremy Morse 992e21eeee [DebugInfo][InstrRef] Fix over-droppage of locations in X86FloatingPoint
Over in D105657, we started dropping instruction numbers (that become
variable locations) from call instructions, as we can't correctly represent
the x87 FP stack. Unfortunately, it turns out that the "special FP
instructions" that this pass transforms includes "every call instruction"
[0]. Thus, we've ended up dropping all return values from all calls. Ouch.

This patch adds a filter: only drop instruction numbers from calls if they
return something on the FP stack. Seeing how LLVM only allows a single
return value, this should drop instruction numbers on anything that returns
a float, and nothing else.

Rather than writing a new test, I've modified the original one to have a
positive and negative case: drop instruction number on a call with an
FP-stack modification, keep it on a plain call.

Differential Revision: https://reviews.llvm.org/D108580
2021-08-24 10:24:07 +01:00
Petar Avramovic 2bf4eeeeb6 [GlobalISel] Avoid creating COPY in LegalizationArtifactCombiner
When Src and Dst used in buildAnyExtOrTrunc or buildSExtOrTrunc
have the same type (creates COPY) use Src register directly or
use replaceRegOrBuildCopy instead.

Differential Revision: https://reviews.llvm.org/D108306
2021-08-24 11:09:56 +02:00
Jingu Kang b52171629f [GVN] Execute performLoopLoadPRE ahead of PerformLoadPRE
Differential Revision: https://reviews.llvm.org/D108204
2021-08-24 09:50:27 +01:00
Cullen Rhodes e9c8973f1c [AArch64][SME] Fix v8.6a bf16 NEON instruction predication
In streaming mode on SME targets only the scalar BFCVT armv8.6-a
instruction is legal, predicate the illegal instructions on NEON to
disable them in streaming mode (see D107902). BFCVT is predicated on
HasNEONorStreamingSVE.

The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2021-06/SIMD-FP-Instructions

Reviewed By: paulwalker-arm

Differential Revision: https://reviews.llvm.org/D108279
2021-08-24 08:13:57 +00:00
Michael Kruse cdbc86dd22 [Polly] Don't redundantly link libPolly into unittests.
With LLVM_LINK_LLVM_DYLIB and LLVM_POLLY_LINK_INTO_TOOLS, Polly is
already linked into libLLVM.so, linking libPolly.a as well into
unittests results in duplicate command line registration errors.
2021-08-24 03:07:30 -05:00
Martin Storsjö 039b469b85 [ARM] Allow using ';' as asm statement separator in MSVC mode
This does the same as D96259, but for ARM, just like AArch64,
using the same comment char as for ELF and MinGW mode.

As the assembly input/output of LLVM is GAS style, trying to
match what MS armasm.exe does isn't needed (because the comment
char used is the least concern when it comes to that; all
directives differ too). If a separate armasm compatible mode
is implemented, it can use its own comment style (just like
llvm-ml implements MS ml.exe compatible assembly parsing).

This fixes building compiler-rt assembly files for ARM in MSVC
mode.

The updated testcase literals-comments.s was only intended to
make sure that '#' isn't interpreted as a comment char.

Differential Revision: https://reviews.llvm.org/D107251
2021-08-24 11:01:49 +03:00
Pushpinder Singh 9b8b7c1180 [AMDGPU][Libomptarget] Delete g_atl_machine global
With uses of g_atl_machine gone, a significant portion of dead
code has been removed.

This patch depends on D104691 and D104695.

Reviewed By: JonChesterfield

Differential Revision: https://reviews.llvm.org/D104696
2021-08-24 07:59:40 +00:00
Zhouyi Zhou 1f8602e16e [clang] NFC: remove superfluous braces
In commit 9bb33f572f, a pair of superfluous braces are introduced to the function Sema::BuildDeclarationNameExpr.
This patch tries to remove the superfluous braces. Also use clang-format to further beautify the above function.

Reviewed By: rjmccall

Differential Revision: https://reviews.llvm.org/D108609
2021-08-24 15:42:50 +08:00
Anton Afanasyev bed587631f [AggressiveInstCombine] Add arithmetic shift right instr to `TruncInstCombine` DAG
Add `ashr` instruction to the DAG post-dominated by `trunc`, allowing
`TruncInstCombine` to reduce bitwidth of expressions containing
these instructions.

We should be shifting by less than the target bitwidth.
Also it is sufficient to require that all truncated bits
of the value-to-be-shifted are sign bits (all zeros or ones) and
one sign bit is left untruncated: https://alive2.llvm.org/ce/z/Ajo2__

Part of https://reviews.llvm.org/D107766

Differential Revision: https://reviews.llvm.org/D108355
2021-08-24 10:41:16 +03:00
Lang Hames 8614cb9f99 [ORC-RT] Add non-const WrapperFunctionResult data access, simplify allocate.
WrapperFunctionResult no longer supports wrapping constant data, so this patch
provides direct non-const access to the wrapped data. Since wrapped data can now
be written, the WrapperFunctionResult::allocate method can be simplified to
return a WrapperFunctionResult.

This is essentially the same change (and with the same motivation) as LLVM
commit 8b117830b1, but applied to the ORC runtime's WrapperFunctionResult code.
2021-08-24 17:34:59 +10:00
Anton Afanasyev 280a0b735f [Test][AggressiveInstCombine] Modify shift tests
Add `sext` for `ashr`, remove unrelated tests
2021-08-24 10:30:27 +03:00
Lang Hames 8b117830b1 [ORC] Add non-const WrapperFunctionResult::data method, simplify allocate.
WrapperFunctionResult no longer supports wrapping constant data, so this patch
adds a non-const data method. Since data can now be written through the data
method, the allocate method can be simplified to return a WrapperFunctionResult.
2021-08-24 17:15:37 +10:00
Pushpinder Singh 07e85823aa [OpenMP][AMDGCN] Enable complex functions
This patch enables basic complex functionality using the ocml builtins.

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D108552
2021-08-24 12:40:41 +05:30
Liu, Chen3 b7795eb646 [X86] Building constant vector which element type is half will cause assertion fail.
Fix assertion fail when building con constant vector which element type is half.

Differential Revision: https://reviews.llvm.org/D108612
2021-08-24 14:34:30 +08:00
Omar Emara 292f013395 [LLDB][GUI] Handle extra navigation keys in forms
This patch handles the up and down keys if they weren't handled by the
selected field. Moreover, it makes sure the form always absorb the key
to take full control until the form is canceled or submitted.

Differential Revision: https://reviews.llvm.org/D108414
2021-08-23 22:42:57 -07:00
Kazu Hirata cb661df58f [IPO] Remove DisableTailCalls (NFC)
The last use was removed on Jun 9, 2015 in commit
d9699bc7bd.
2021-08-23 22:20:23 -07:00
Omar Emara 945cde8b6a [LLDB][GUI] Add submit form key combination
This patch adds a new key ALt+Enter key combination to form windows.
Once invoked, the first action is executed without having to navigate to
its button.

Field exit callbacks are now also invoked on validation to support this
aforementioned key combination.

One concern for this key combination is its potential use by the window
manager of the host. I am not sure if this will be a problem, but it is
worth putting in consideration.

Differential Revision: https://reviews.llvm.org/D108410
2021-08-23 22:07:04 -07:00
Petr Hosek 8111f2f7ee [profile] Update counter offset to account for binary ids
In the raw profile, binary ids immediately follow the header so when
computing counters offset we need to account for the new section.

Differential Revision: https://reviews.llvm.org/D108608
2021-08-23 21:43:30 -07:00
Omar Emara d95d2a8e4a [LLDB][GUI] Add extra keys to text field
This patch adds many new keys to the text field and implements new
behaviors as follows:

```
case KEY_HOME:
case KEY_CTRL_A:
  MoveCursorToStart();
case KEY_END:
case KEY_CTRL_E:
  MoveCursorToEnd();
case KEY_RIGHT:
case KEY_SF:
  MoveCursorRight();
case KEY_LEFT:
case KEY_SR:
  MoveCursorLeft();
case KEY_BACKSPACE:
case KEY_DELETE:
  RemovePreviousChar();
case KEY_DC:
  RemoveNextChar();
case KEY_EOL:
case KEY_CTRL_K:
  ClearToEnd();
case KEY_DL:
case KEY_CLEAR:
  Clear();
```

This patch also refactors scrolling to be dynamic at draw time for
easier handing.

Differential Revision: https://reviews.llvm.org/D108385
2021-08-23 21:16:48 -07:00
Wang, Pengfei c728bd5bba [X86] AVX512FP16 instructions enabling 5/6
Enable FP16 FMA instructions.

Ref.: https://software.intel.com/content/www/us/en/develop/download/intel-avx512-fp16-architecture-specification.html

Reviewed By: LuoYuanke

Differential Revision: https://reviews.llvm.org/D105268
2021-08-24 09:07:19 +08:00
Philip Reames 96ef794fd0 [SCEV] Add a hasFlags utility to improve readability [NFC] 2021-08-23 17:36:52 -07:00
Jessica Paquette 2ec2b25fba [AArch64][GlobalISel] Select @llvm.aarch64.neon.ld2.*
This is pretty similar to the ST2 selection code in
`AArch64InstructionSelector::selectIntrinsicWithSideEffects`.

This is a GISel equivalent of the ld2 case in `AArch64DAGToDAGISel::Select`.
There's some weirdness there that appears here too (e.g. using ld1 for scalar
cases, which are 1-element vectors in SDAG.)

It's a little gross that we have to create the copy and then select it right
after, but I think we'd need to refactor the existing copy selection code
quite a bit to do better.

This was falling back while building llvm-project with GISel for AArch64.

Differential Revision: https://reviews.llvm.org/D108590
2021-08-23 17:15:53 -07:00
Haowei Wu 253cb50c60 [lit] Add the option to output test result as resultdb json format
This change adds the option --resultdb-output=path allow llvm-lit
generating LuCI ResultDB JSON output for the test results, which
can be better integrated with certain CI/CQ framework.

Differential Revision: https://reviews.llvm.org/D108238
2021-08-23 17:00:50 -07:00
MaheshRavishankar b546f4347b [mlir]Linalg] Allow controlling fusion of linalg.generic -> linalg.tensor_expand_shape.
Differential Revision: https://reviews.llvm.org/D108565
2021-08-23 16:28:10 -07:00
Reid Kleckner e42ce422a9 [dllexport] Instantiate default ctor default args
Fixes https://bugs.llvm.org/show_bug.cgi?id=51414.

Differential Revision: https://reviews.llvm.org/D108021
2021-08-23 15:56:29 -07:00
Greg Clayton a58c2e4af0 Fix DWARFDie::getDeclFile(...) to work with DW_AT_specification.
DWARFDie::getDeclFile(...) previously only supported getting the DW_AT_decl_file if the DIE itself contained the DW_AT_decl_file attribute, or if the DIE had a DW_AT_abstract_origin that pointed to another DIE that had a DW_AT_decl_file. This patch allows the function to get the right attribute value if there is a DW_AT_specification that points to another DIE. We also test that if a DW_AT_abtract_origin or DW_AT_specification points to a DIE in another CU with a DW_FORM_ref_addr, that the right line table is used to extract the file index.

Full tests were added for the following cases:
- DIE has a DW_AT_decl_file attribute
- DIE has a DW_AT_abtract_origin that points to another die in the same CU
- DIE has a DW_AT_abtract_origin that points to another die in another CU
- DIE has a DW_AT_specification that points to another die in the same CU
- DIE has a DW_AT_specification that points to another die in another CU

Differential Revision: https://reviews.llvm.org/D108480
2021-08-23 15:43:18 -07:00
Jon Chesterfield d26000e4cc [openmp][devicertl] Freestanding nvptx via stub printf
Compiled nvptx devicertl as freestanding, breaking the
dependency on host glibc and gcc-multilibs. Thus build it by default.

Comes at the cost of #defining out printf. Tried mapping it onto
__builtin_printf but that gets transformed back to printf instead
of hitting the cuda/openmp lowering transform.

Printf could be preserved by one of:
- dropping all the standard headers and ffreestanding
- providing a header only printf implementation
- changing the compiler handling of printf

Reviewed By: grokos

Differential Revision: https://reviews.llvm.org/D108349
2021-08-23 23:07:47 +01:00
Mircea Trofin 1055c5e1d3 [MLGO] Make sure inliner logs when deleting callees
When using final reward (which is now the default), we were skipping
logging decisions that were leading to callee deletion. This fixes that.

Differential Revision: https://reviews.llvm.org/D108587
2021-08-23 14:54:46 -07:00
Azharuddin Mohammed d898693f72 [ExecutionEngine] Use the libunwind __register_frame on Darwin
This was already the case, but the recent change (957334382c) altered
the behavior on some of our bots where __unw_add_dynamic_fde is not
found. This restores the prior behavior on Darwin while also retaining
the new behavior from that change.
2021-08-23 14:51:14 -07:00