Summary:
Since the changes to introduce vec3 and vec5, INSERT_VECTOR for these
sizes has been marked "expand", which made LegalizeDAG lower it to loads
and stores via a stack slot. The code got optimized a bit later, but the
now-unused stack slot was never deleted.
This commit avoids that problem by custom lowering INSERT_SUBVECTOR into
an EXTRACT_VECTOR_ELT and INSERT_VECTOR_ELT for each element in the
subvector to insert.
V2: Addressed review comments re test.
Differential Revision: https://reviews.llvm.org/D63160
Change-Id: I9e3c13e36f68cfa3431bb9814851cc1f673274e1
llvm-svn: 365148
We allow forming a splat (broadcast) shuffle, but we were conservatively limiting
that to cases where all elements of the vector are specified. It should be safe
from a codegen perspective to allow undefined lanes of the vector because the
expansion of a splat shuffle would become the chain of inserts again.
Forming splat shuffles can reduce IR and help enable further IR transforms.
Motivating bugs:
https://bugs.llvm.org/show_bug.cgi?id=42174https://bugs.llvm.org/show_bug.cgi?id=16739
Differential Revision: https://reviews.llvm.org/D63848
llvm-svn: 365147
Summary:
As explained in D63668, malloc(0) could return a null pointer. llvm-c-test does not handle this case correctly. Instead of calling malloc(0), avoid the operation altogether.
Authored By: andusy
Reviewers: hubert.reinterpretcast, xingxue, jasonliu, daltenty, cebowleratibm
Reviewed By: hubert.reinterpretcast
Subscribers: mehdi_amini, dexonsmith, jsji, llvm-commits
Tags: LLVM
Differential Revision: https://reviews.llvm.org/D63788
llvm-svn: 365144
The difference from D63432/r365015 is that this patch does not place
SHF_STRINGS sections with different alignments into the same
MergeSyntheticSection. Doing that would:
(1) create unnecessary padding and thus waste space.
Add a test tail-merge-string-align2.s to check no extra padding is created.
(2) make some input sections unaligned when tail merge (-O2) is enabled.
The alignment of MergeTailAlignment::Builder was out of sync in D63432.
MOVAPS on such unaligned strings can raise SIGSEGV.
This should fix PR42289: the Linux kernel has a use case that input
files have .rodata.cst32 sections with different alignments. The
expectation (and what ld.bfd and gold do) is that in the -r link, there
is only one .rodata.cst32 (SHF_MERGE sections with different alignments
can be combined), but lld currently creates one for each different
alignment.
The current merging strategy:
1) Group SHF_MERGE sections by (name, sh_flags, sh_entsize and
sh_addralign). Merging is performed among a group, even if -O0 is specified.
2) Create one output section for each group. This is a special case in
addInputSec().
This patch changes 1) to:
1) Group SHF_MERGE sections by (name, sh_flags, sh_entsize).
Merging is performed among a group, even if -O0 is specified.
We will thus create just one .rodata.cst32 . This also improves merging
efficiency when sections with the same name but different alignments are
combined.
Reviewed By: peter.smith
Differential Revision: https://reviews.llvm.org/D64200
llvm-svn: 365139
Summary:
gcc invokes cc1 through a path deduced from argv[0] therefore it must
be correctly set.
Also it prints the search path to stderr not stdout, this also applies to clang.
Reviewers: sammccall
Subscribers: ilya-biryukov, MaskRay, jkorous, arphaman, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D64196
llvm-svn: 365132
If %t1.o has a weak reference on foo, and %t2.so has a non-weak
reference on foo: `ld.lld %t1.o %t2.so -o %t`
We incorrectly set the binding of the undefined foo to STB_GLOBAL.
Fix this by ignoring undefined symbols in a SharedFile for Undefined and
SharedSymbol.
This fixes the binding of pthread_once when the program links against
both librt.so and libpthread.so
```
a.o: STB_WEAK reference to pthread_once
librt.so: STB_GLOBAL reference to pthread_once # should be ignored
libstdc++.so: STB_WEAK reference to pthread_once # should be ignored
libgcc_s.so.1: STB_WEAK reference to pthread_once # should be ignored
```
The STB_GLOBAL pthread_once issue (not fixed by D63974) can cause a link error when the result
DSO is used to link another DSO with -z defs if -lpthread is not specified. (libstdc++.so.6 not having a dependency on libpthread.so is a really nasty hack...)
We happened to create a weak undef before D63974 because libgcc_s.so.1
was linked the last and it changed the binding again to weak.
Reviewed By: ruiu
Differential Revision: https://reviews.llvm.org/D64136
llvm-svn: 365129
Bitcast v4i32 to v8f32 and back again - it might be worth adding isel patterns for X86PShufd v8i32 on AVX1 targets like we did for X86Blendi to avoid the bitcasts?
llvm-svn: 365125
Summary:
Clangd currently doesn't cache any indexing failures, which results in
retrying those failed files even if their contents haven't changed.
Reviewers: sammccall
Subscribers: ilya-biryukov, MaskRay, jkorous, arphaman, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D63986
llvm-svn: 365120
Without this fix gcc (7.4) complains with
../lib/Remarks/RemarkParser.cpp: In function 'std::unique_ptr<llvm::remarks::ParserImpl> formatToParserImpl(llvm::remarks::ParserFormat, llvm::StringRef)':
../lib/Remarks/RemarkParser.cpp:29:1: error: control reaches end of non-void function [-Werror=return-type]
}
^
../lib/Remarks/RemarkParser.cpp: In function 'std::unique_ptr<llvm::remarks::ParserImpl> formatToParserImpl(llvm::remarks::ParserFormat, llvm::StringRef, const llvm::remarks::ParsedStringTable&)':
../lib/Remarks/RemarkParser.cpp:38:1: error: control reaches end of non-void function [-Werror=return-type]
}
^
The Format enum currently only contains the value YAML which is indeed
already handled in the switches, but gcc complains anyway.
Adding a default case with an llvm_unreachable silences gcc.
llvm-svn: 365118
The arm condition codes for GE is N==V (and for LT is N!=V). If the source of
flags cannot set V (overflow), such as a cmp against #0, then we can use the
simpler PL and MI conditions that only check N. As these PL/MI conditions are
simpler than GE/LT, other passes like the peephole optimiser can have a better
time optimising away the redundant CMPs.
The exception is the VSEL instruction, which cannot take the PL code, so there
the transform favours GE.
Differential Revision: https://reviews.llvm.org/D64160
llvm-svn: 365117
The --show-children option description describes what it does, and
references the =<offset> parameter of section dump switches. I don't
think it needs to be explained again in the documentation of the
section dump switches too.
Reviewed by: JDevlieghere
Differential Revision: https://reviews.llvm.org/D64132
llvm-svn: 365115
When a Tablegen instruction description uses `OperandWithDefaultOps`,
isel patterns for that instruction don't have to fill in the default
value for the operand in question. But the flip side is that they
actually //can't// override the defaults even if they want to.
This will be very inconvenient for the Arm backend, when we start
wanting to write isel patterns that generate the many MVE predicated
vector instructions, in the form with predication actually enabled. So
this small Tablegen fix makes it possible to write an isel pattern
either with or without values for a defaulted operand, and have the
default values filled in only if they are not overridden.
If all the defaulted operands come at the end of the instruction's
operand list, there's a natural way to match them up to the arguments
supplied in the pattern: consume pattern arguments until you run out,
then fill in any missing instruction operands with their default
values. But if defaulted and non-defaulted operands are interleaved,
it's less clear what to do. This does happen in existing targets (the
first example I came across was KILLGT, in the AMDGPU/R600 backend),
and of course they expect the previous behaviour (that the default for
those operands is used and a pattern argument is not consumed), so for
backwards compatibility I've stuck with that.
Reviewers: nhaehnle, hfinkel, dmgreen
Subscribers: mehdi_amini, javed.absar, tpr, kristof.beyls, steven_wu, dexonsmith, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63814
llvm-svn: 365114
This adds patterns for the simpler VAND, VORR and VEOR bitwise vector
instructions. It also adjusts the top16Zero PatLeaf to not match on vector
instructions, which can otherwise cause problems.
Code written by David Sherwood.
Differential Revision: https://reviews.llvm.org/D63867
llvm-svn: 365113
r363757 renamed ExpandISelPseudo to FinalizeISel, so the RUN line in
select-must-add-unconditional-jump.mir needed updating to refer to finalize-isel.
llvm-svn: 365108
Summary:
"ww" and "ws" are both constraint codes for VSX vector registers that
hold scalar double data. "ww" is preferred for float while "ws" is
preferred for double.
Reviewed By: jsji
Differential Revision: https://reviews.llvm.org/D64119
llvm-svn: 365106
Summary: Removed excess new lines from documentations. As far as I can tell, it seems as though restructured text is agnostic to new lines, the use of new lines was inconsistent and had no effect on how the files were being displayed.
Reviewers: jhenderson, rupprecht, JDevlieghere
Reviewed By: jhenderson
Subscribers: llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63971
llvm-svn: 365105
Added array of valid architectures and function returning array.
Modified llvm-lipo to include list of valid architectures in error message for invalid arch.
Patch by Anusha Basana <anusha.basana@gmail.com>
Differential Revision: https://reviews.llvm.org/D63735
llvm-svn: 365099
Tim Renouf