Commit Graph

163707 Commits

Author SHA1 Message Date
Omer Paparo Bivas 54596e1c1a [InstCombine] new testcases for OverflowingBinaryOperators and PossiblyExactOperators transformations; NFC
instcombine should transform the relevant cases if the OverflowingBinaryOperator/PossiblyExactOperator can be proven to be safe.

Change-Id: I7aec62a31a894e465e00eb06aed80c3ea0c9dd45
llvm-svn: 331265
2018-05-01 14:27:10 +00:00
Simon Pilgrim dd8eae128b [X86] Split WriteFShuffle into XMM and YMM/ZMM scheduler classes
Removes more WriteFShuffle InstRW overrides

llvm-svn: 331264
2018-05-01 14:25:01 +00:00
Simon Pilgrim f6b81dae9e [X86] Convert all uses of WriteFShuffle to X86SchedWriteWidths.
In preparation of splitting WriteFShuffle by vector width.

llvm-svn: 331262
2018-05-01 14:14:42 +00:00
Sander de Smalen 788dc70c78 [AArch64][SVE] Asm: Support for contiguous ST1 (scalar+scalar) store instructions.
Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, javed.absar

Reviewed By: fhahn

Differential Revision: https://reviews.llvm.org/D46121

llvm-svn: 331260
2018-05-01 13:36:03 +00:00
Simon Dardis 3d562fb975 Reland r331175: "[mips] Fix the predicates of jump and branch and link instructions"
The previous version of this patch restricted the 'jal' instruction to MIPS and
microMIPSr3. microMIPS32r6 does not have this instruction and instead uses jal
as an alias for balc.

Original commit message:
> Reviewers: smaksimovic, atanasyan, abeserminji
>
> Differential Revision: https://reviews.llvm.org/D46114
>

llvm-svn: 331259
2018-05-01 13:06:49 +00:00
Simon Pilgrim 57f2b185ac [X86] Split WriteVecLogic into XMM and YMM/ZMM scheduler classes
This removes all the WriteVecLogic InstRW overrides.

llvm-svn: 331258
2018-05-01 12:39:17 +00:00
Omer Paparo Bivas 82ef8e19ef [InstCombine] Adjusting bswap pattern matching to hold for And/Shift mixed case
Differential Revision: https://reviews.llvm.org/D45731

Change-Id: I85d4226504e954933c41598327c91b2d08192a9d
llvm-svn: 331257
2018-05-01 12:25:46 +00:00
Simon Pilgrim 6f710a6440 [X86] Convert all uses of WriteFLogic/WriteVecLogic to X86SchedWriteWidths.
In preparation of splitting WriteVecLogic by vector width.

llvm-svn: 331256
2018-05-01 12:15:29 +00:00
Florian Hahn ba4d85ee3f [MC] Add llvm_unreachable to toString to fix compile time warning.
Without this change, GCC 7 raises the warning below:
        control reaches end of non-void function

Reviewers: sbc100, andreadb

Reviewed By: andreadb

Differential Revision: https://reviews.llvm.org/D46304

llvm-svn: 331255
2018-05-01 11:18:31 +00:00
Simon Pilgrim fc0c26f1a6 [X86] Tag PSLLDQ/PSRLDQ as WriteShuffle scheduler classes instead of shifts.
Although they are encoded similar to bit shifts, the byte shifts behave like shuffles from a scheduling point of view.

llvm-svn: 331253
2018-05-01 11:05:42 +00:00
Andrea Di Biagio d4c58400c5 [X86] Correct spill slot size.
This patch fixes a bug introduced by revision 330778 (originally reviewed at:
https://reviews.llvm.org/D44782), where function isFrameLoadOpcode returned
the wrong number of bytes read for opcodes VMOVSSrm and VMOVSDrm.

This corrects that mistake, and extends the regression test to catch cases where
the dead stores should be removed.

Patch by Jeremy Morse.

Differential Revision: https://reviews.llvm.org/D46256

llvm-svn: 331252
2018-05-01 10:29:38 +00:00
Gabor Buella 0537fdbcab NFC, Avoid a warning in WasmObjectWriter
The warning was (introduced in r331220):

lib/MC/WasmObjectWriter.cpp:51:1: warning: control reaches end of non-void function [-Wreturn-type]
 }
 ^

llvm-svn: 331251
2018-05-01 10:21:10 +00:00
Gabor Buella c8ded04e85 [X86] movdiri and movdir64b instructions
Reviewers: spatel, craig.topper, RKSimon

Reviewed By: craig.topper, RKSimon

Differential Revision: https://reviews.llvm.org/D45983

llvm-svn: 331248
2018-05-01 10:01:16 +00:00
Chandler Carruth 2c85a23123 [PM/LoopUnswitch] Remove the last manual domtree update code from loop
unswitch and replace it with the amazingly simple update API code.

This addresses piles of FIXMEs around the update logic here and makes
everything substantially simpler.

llvm-svn: 331247
2018-05-01 09:54:39 +00:00
Chandler Carruth 44aab925fd [PM/LoopUnswitch] Add back a successor set that was removed based on
code review.

It turns out this *is* necessary, and I read the comment on the API
correctly the first time. ;]

The `applyUpdates` routine requires that updates are "balanced". This is
in order to cleanly handle cycles like inserting, removing, nad then
re-inserting the same edge. This precludes inserting the same edge
multiple times in a row as handling that would cause the insertion logic
to become *ordered* instead of *unordered* (which is what the API
provides).

It happens that in this specific case nothing (other than an assert and
contract violation) goes wrong because we're never inserting and
removing the same edge. The implementation *happens* to do the right
thing to eliminate redundant insertions in that case.

But the requirement is there and there is an assert to catch it.
Somehow, after the code review I never did another asserts-clang build
testing loop-unswich for a long time. As a consequence, I didn't notice
this despite a bunch of testing going on, but it shows up immediately
with an asserts build of clang itself.

llvm-svn: 331246
2018-05-01 09:42:09 +00:00
Craig Topper 33dc01d105 [X86] Remove 'opaque ptr' from the intel syntax parser and printer.
Previously for instructions like fxsave we would print "opaque ptr" as part of the memory operand. Now we print nothing.

We also no longer accept "opaque ptr" in the parser. We still accept any size to be specified for these instructions, but we may want to consider only parsing when no explicit size is specified. This what gas does.

llvm-svn: 331243
2018-05-01 04:42:00 +00:00
Eric Christopher 8024425801 Temporarily revert "[DEBUG] Initial adaptation of NVPTX target for debug info emission."
This appears to have some issues associated with the file directive output
causing multiple global symbols with the name "file" to be emitted into a
startup section. I'm investigating more specific causes and working with the
original author.

This reverts commit r330271.

Also Revert "[DEBUGINFO, NVPTX] Add the test for the debug info of the local"

This reverts commit r330592 and the follow up of 330779 as the testcase is dependent upon r330271.

llvm-svn: 331237
2018-05-01 00:10:13 +00:00
Sanjay Patel 1934cb1c49 [InstCombine] fix test to restore intent
This test had values that differed in only in capitalization,
and that causes problems for the auto-generating check line
script. So I changed that in rL331226, but I accidentally
forgot to change a subsequent use of a param.

llvm-svn: 331228
2018-04-30 21:28:18 +00:00
Sanjay Patel dab8515370 [InstCombine] add tests, update checks; NFC
llvm-svn: 331226
2018-04-30 21:03:36 +00:00
Nico Weber dd3c75a067 Stop setting LLVM_ON_WIN32 in config.h and llvm-config.h.
See thread "Replacing LLVM_ON_WIN32 with just _WIN32" on llvm-dev and cfe-dev.

I replaced all uses of LLVM_ON_WIN32 with _WIN32 in r331127 (llvm),
r331069 (clang), r329697 (lldb), r329696 (lld), r329696 (clang-tools-extra).

If your out-of-tree program used LLVM_ON_WIN32, just use _WIN32 instead, which
is set at exactly the same time to exactly the same value.

https://reviews.llvm.org/D46264

llvm-svn: 331224
2018-04-30 20:19:48 +00:00
Alina Sbirlea 020363edcc [ModRefInfo] Rename local variable IsMustAlias to avoid shadowing MustAlias enum entry.
llvm-svn: 331222
2018-04-30 20:11:13 +00:00
Florian Hahn 3df8844b92 [SimplifyCFG] Use BB::instructionsWithoutDebug to skip DbgInfo (NFC).
This patch updates some code responsible the skip debug info to use
BasicBlock::instructionsWithoutDebug. I think this makes things slightly
simpler and more direct.

Reviewers: aprantl, vsk, hans, danielcdh

Reviewed By: hans

Differential Revision: https://reviews.llvm.org/D46252

llvm-svn: 331221
2018-04-30 20:10:53 +00:00
Sam Clegg a165f2d60d [WebAssembly] MC: Improve debug output
llvm-svn: 331220
2018-04-30 19:40:57 +00:00
Krzysztof Parzyszek 1cf329c933 [LivePhysRegs] Remove registers clobbered by regmasks from the live set
Dead defs were being removed from the live set (in stepForward), but
registers clobbered by regmasks weren't (more specifically, they were
actually removed by removeRegsInMask, but then they were added back in).

llvm-svn: 331219
2018-04-30 19:38:47 +00:00
Nirav Dave 6c0665e221 [MC] Change AsmParser to leverage Assembler during evaluation
Teach AsmParser to check with Assembler for when evaluating constant
expressions.  This improves the handing of preprocessor expressions
that must be resolved at parse time. This idiom can be found as
assembling-time assertion checks in source-level assemblers. Note that
this relies on the MCStreamer to keep sufficient tabs on Section /
Fragment information which the MCAsmStreamer does not. As a result the
textual output may fail where the equivalent object generation would
pass. This can most easily be resolved by folding the MCAsmStreamer
and MCObjectStreamer together which is planned for in a separate
patch.

Currently, this feature is only enabled for assembly input, keeping IR
compilation consistent between assembly and object generation.

Reviewers: echristo, rnk, probinson, espindola, peter.smith

Reviewed By: peter.smith

Subscribers: eraman, peter.smith, arichardson, jyknight, hiraditya, llvm-commits

Differential Revision: https://reviews.llvm.org/D45164

llvm-svn: 331218
2018-04-30 19:22:40 +00:00
Florian Hahn 8fe04ad3f7 [LoopSimplify] Use BB::instructionsWithoutDebug to skip DbgInfo (NFC).
This patch updates some code responsible the skip debug info to use
BasicBlock::instructionsWithoutDebug. I think this makes things slightly
simpler and more direct.

Reviewers: aprantl, vsk, chandlerc

Reviewed By: aprantl

Differential Revision: https://reviews.llvm.org/D46253

llvm-svn: 331217
2018-04-30 19:19:36 +00:00
Matt Arsenault 0084adc516 AMDGPU: Add Vega12 and Vega20
Changes by
  Matt Arsenault
  Konstantin Zhuravlyov

llvm-svn: 331215
2018-04-30 19:08:16 +00:00
Roman Tereshin 46f838f370 [MIR] Reset unique MBB numbering in MachineFunction::reset()
No need to waste space nor number MBBs differently if MF gets recreated.

Reviewers: qcolombet, stoklund, t.p.northover, bogner, javed.absar

Reviewed By: qcolombet

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D46078

llvm-svn: 331213
2018-04-30 18:58:57 +00:00
Sanjay Patel 1babf5ff32 [DAGCombiner] rename function attribute for disabling ftrunc transform
This is the matching name change for the Clang patch at:
D46236
rL331209

Differential Revision: https://reviews.llvm.org/D46237 

llvm-svn: 331210
2018-04-30 18:20:33 +00:00
Simon Pilgrim 3c35408e48 [X86] Introduce X86SchedWriteWidths schedule wrapper for different vector widths.
We need to split most of the scheduler classes by vector width to remove more of the InstRW overrides, this patch should make this easier/tidier by allowing us to pass the X86SchedWriteWidths wrapper to multi-width multiclasses and then split as required.

I've included fields for Scl (scalar float/double), MMX (MMX integer), XMM, YMM and ZMM widths. These fields mostly share the same classes but it should give us the flexibility that we may need in the future.

This patch has replaced a set of example SSE/AVX512 instruction cases but isn't exhaustive as it gets very noisy before we really need the functionality.

Differential Revision: https://reviews.llvm.org/D46266

llvm-svn: 331208
2018-04-30 18:18:38 +00:00
Roman Lebedev aa4faec114 [InstCombine] Unfold masked merge with constant mask
Summary:
As discussed in D45733, we want to do this in InstCombine.

https://rise4fun.com/Alive/LGk

Reviewers: spatel, craig.topper

Reviewed By: spatel

Subscribers: chandlerc, xbolva00, llvm-commits

Differential Revision: https://reviews.llvm.org/D45867

llvm-svn: 331205
2018-04-30 17:59:33 +00:00
Roman Lebedev b7ae4ef82b [InstCombine][NFC] Add tests for unfolding masked merge with constant mask
Summary: As discussed in D45733, we want to do this in InstCombine.

Differential Revision: https://reviews.llvm.org/D45866

llvm-svn: 331204
2018-04-30 17:59:26 +00:00
Ulrich Weigand c3ec80fea1 [SystemZ] Handle SADDO et.al. and ADD/SUBCARRY
This provides an optimized implementation of SADDO/SSUBO/UADDO/USUBO
as well as ADDCARRY/SUBCARRY on top of the new CC implementation.

In particular, multi-word arithmetic now uses UADDO/ADDCARRY instead
of the old ADDC/ADDE logic, which means we no longer need to use
"glue" links for those instructions.  This also allows making full
use of the memory-based instructions like ALSI, which couldn't be
recognized due to limitations in the DAG matcher previously.

Also, the llvm.sadd.with.overflow et.al. intrinsincs now expand to
directly using the ADD instructions and checking for a CC 3 result.

llvm-svn: 331203
2018-04-30 17:54:28 +00:00
Ulrich Weigand b32f3656d2 [SystemZ] Do not use glue to represent condition code dependencies
Currently, an instruction setting the condition code is linked to
the instruction using the condition code via a "glue" link in the
SelectionDAG.  This has a number of drawbacks; in particular, it
means the same CC cannot be used by multiple users.  It also makes
it more difficult to efficiently implement SADDO et. al.

This patch changes the back-end to represent CC dependencies as
normal values during SelectionDAG matching, along the lines of
how this is handled in the X86 back-end already.

In addition to the core mechanics of updating all relevant patterns,
this requires a number of additional changes:

- We now need to be able to spill/restore a CC value into a GPR
  if necessary.  This means providing a copyPhysReg implementation
  for moves involving CC, and defining getCrossCopyRegClass.

- Since we still prefer to avoid such spills, we provide an override
  for IsProfitableToFold to avoid creating a merged LOAD / ICMP if
  this would result in multiple users of the CC.

- combineCCMask no longer requires a single CC user, and no longer
  need to be careful about preventing invalid glue/chain cycles.

- emitSelect needs to be more careful in marking CC live-in to
  the basic block it generates.  Also, we can now optimize the
  case of multiple subsequent selects with the same condition
  just like X86 does.

llvm-svn: 331202
2018-04-30 17:52:32 +00:00
Daniel Sanders 2de9d4ad5d Fix infinite loop after r331115
There are two separate fixes here:
* The lowering code for non-extending loads should report UnableToLegalize instead of emitting the same instruction.
* The target should not be requesting lowering of non-extending loads.

llvm-svn: 331201
2018-04-30 17:20:01 +00:00
Jonas Devlieghere 4bbcb5ab04 [DebugInfo] Prevent infinite recursion for malformed DWARF
This prevents infinite recursion in DWARFDie::findRecursively for
malformed DWARF where a DIE references itself.

This fixes PR36257.

Differential revision: https://reviews.llvm.org/D43092

llvm-svn: 331200
2018-04-30 17:02:41 +00:00
Davide Italiano bd3bf1660b [SLPVectorizer] Debug info shouldn't impact spill cost computation.
<rdar://problem/39794738>

(Also, PR32761).

Differential Revision:  https://reviews.llvm.org/D46199

llvm-svn: 331199
2018-04-30 16:57:33 +00:00
Simon Pilgrim c80a5aa09a [X86][Atom] Remove unnecessary x87 load/move instrw overrides.
llvm-svn: 331198
2018-04-30 16:51:13 +00:00
Tom Stellard add59c052d AMDGPU: Remove some dead code
llvm-svn: 331196
2018-04-30 16:28:02 +00:00
Andrea Di Biagio e047d3529b [llvm-mca] Correctly handle zero-latency stores that consume pipeline resources.
This fixes PR37293.

We can have scheduling classes with no write latency entries, that still consume
processor resources. We don't want to treat those instructions as zero-latency
instructions; they still have to be issued to the underlying pipelines, so they
still consume resource cycles.

This is likely to be a regression which I have accidentally introduced at
revision 330807. Now, if an instruction has a non-empty set of write processor
resources, we conservatively treat it as a normal (i.e. non zero-latency)
instruction.

llvm-svn: 331193
2018-04-30 15:55:04 +00:00
Ulrich Weigand 79e5cd2fc5 [SystemZ] Refactor some VT casts in DAG match patterns
In patterns where we need to specify a result VT, prefer

  [(set (tr.vt tr.op:$V1), (operator ...))]

over

  [(set tr.op:$V1, (tr.vt (operator ...)))]

This is NFC now, but simplifies some future changes.

llvm-svn: 331192
2018-04-30 15:52:28 +00:00
Ulrich Weigand fb56686cd3 [SystemZ] Improve handling of Select pseudo-instructions
If we have LOCR instructions, select them directly from SelectionDAG
instead of first going through a pseudo instruction and then using
the custom inserter to emit the LOCR.

Provide Select pseudo-instructions for VR32/VR64 if we have vector
instructions, to avoid having to go through the first 16 FPRs
unnecessarily.

If we do not have LOCFHR, prefer using LOCR followed by a move
over a conditional branch.

llvm-svn: 331191
2018-04-30 15:49:27 +00:00
Nico Weber da750079fa IWYU for llvm-config.h, removals. Also see r331184.
llvm-svn: 331190
2018-04-30 15:26:01 +00:00
Simon Pilgrim 0a732da261 [X86] Drop unnecessary VPORrm InstrRW override in SkylakeServer.
llvm-svn: 331188
2018-04-30 15:18:33 +00:00
Simon Pilgrim b521ec7525 [X86] Fix SkylakeServer typo in WritePSADBW class - it only uses 1 resource.
llvm-svn: 331187
2018-04-30 15:17:16 +00:00
Tom Stellard 6c81418a63 AMDGPU/GlobalISel: Don't try to lower geometry shaders
Summary: The AMDGPU_GS calling convention is not supported yet.

Reviewers: arsenm, nhaehnle

Reviewed By: nhaehnle

Subscribers: kzhuravl, wdng, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D46041

llvm-svn: 331186
2018-04-30 15:15:23 +00:00
Nico Weber 432a38838d IWYU for llvm-config.h in llvm, additions.
See r331124 for how I made a list of files missing the include.
I then ran this Python script:

    for f in open('filelist.txt'):
        f = f.strip()
        fl = open(f).readlines()

        found = False
        for i in xrange(len(fl)):
            p = '#include "llvm/'
            if not fl[i].startswith(p):
                continue
            if fl[i][len(p):] > 'Config':
                fl.insert(i, '#include "llvm/Config/llvm-config.h"\n')
                found = True
                break
        if not found:
            print 'not found', f
        else:
            open(f, 'w').write(''.join(fl))

and then looked through everything with `svn diff | diffstat -l | xargs -n 1000 gvim -p`
and tried to fix include ordering and whatnot.

No intended behavior change.

llvm-svn: 331184
2018-04-30 14:59:11 +00:00
Bjorn Pettersson 9a8483a4b2 [BranchFolding] Salvage DBG_VALUE instructions from empty blocks
Summary:
This patch will introduce copying of DBG_VALUE instructions
from an otherwise empty basic block to predecessor/successor
blocks in case the empty block is eliminated/bypassed. It
is currently only done in one identified situation in the
BranchFolding pass, before optimizing on empty block.
It can be seen as a light variant of the propagation done
by the LiveDebugValues pass, which unfortunately is executed
after the BranchFolding pass.

We only propagate (copy) DBG_VALUE instructions in a limited
number of situations:
 a) If the empty BB is the only predecessor of a successor
    we can copy the DBG_VALUE instruction to the beginning of
    the successor (because the DBG_VALUE instruction is always
    part of the flow between the blocks).
 b) If the empty BB is the only successor of a predecessor
    we can copy the DBG_VALUE instruction to the end of the
    predecessor (because the DBG_VALUE instruction is always
    part of the flow between the blocks). In this case we add
    the DBG_VALUE just before the first terminator (assuming
    that the terminators do not impact the DBG_VALUE).

A future solution, to handle more situations, could perhaps
be to run the LiveDebugValues pass before branch folding?

This fix is related to PR37234. It is expected to resolve
the problem seen, when applied together with the fix in
SelectionDAG from here: https://reviews.llvm.org/D46129

Reviewers: #debug-info, aprantl, rnk

Reviewed By: #debug-info, aprantl

Subscribers: ormris, gbedwell, llvm-commits

Differential Revision: https://reviews.llvm.org/D46184

llvm-svn: 331183
2018-04-30 14:37:46 +00:00
Bjorn Pettersson abafca619b [SelectionDAG] Improve selection of DBG_VALUE using a PHI node result
Summary:
When building the selection DAG at ISel all PHI nodes are
selected and lowered to Machine Instruction PHI nodes before
we start to create any SDNodes. So there are no SDNodes for
values produced by the PHI nodes.

In the past when selecting a dbg.value intrinsic that uses
the value produced by a PHI node we have been handling such
dbg.value intrinsics as "dangling debug info". I.e. we have
not created a SDDbgValue node directly, because there is
no existing SDNode for the PHI result, instead we deferred
the creationg of a SDDbgValue until we found the first use
of the PHI result.

The old solution had a couple of flaws. The position of the
selected DBG_VALUE instruction would end up quite late in a
basic block, and for example not directly after the PHI node
as in the LLVM IR input. And in case there were no use at all
in the basic block the dbg.value could be dropped completely.

This patch introduces a new VREG kind of SDDbgValue nodes.
It is similar to a SDNODE kind of node, but it refers directly
to a virtual register and not a SDNode. When we do selection
for a dbg.value that is using the result of a PHI node we
can do a lookup of the virtual register directly (as it already
is determined for the PHI node) and create a SDDbgValue node
immediately instead of delaying the selection until we find a
use.

This should fix a problem with losing debug info at ISel
as seen in PR37234 (https://bugs.llvm.org/show_bug.cgi?id=37234).
It does not resolve PR37234 completely, because the debug info
is dropped later on in the BranchFolder (see D46184).

Reviewers: #debug-info, aprantl

Reviewed By: #debug-info, aprantl

Subscribers: rnk, gbedwell, aprantl, JDevlieghere, llvm-commits

Differential Revision: https://reviews.llvm.org/D46129

llvm-svn: 331182
2018-04-30 14:37:39 +00:00
Gabor Buella ad9a04295e NFC, Avoid a warning on pointer casting in PassPlugin.cpp
llvm-svn: 331179
2018-04-30 14:21:28 +00:00
Simon Dardis 5a512d63c9 Revert "[mips] Fix the predicates of jump and branch and link instructions"
That commit broke one of the LLD builders, reverting while I investigate.

This patch reverts r331175.

llvm-svn: 331178
2018-04-30 14:03:35 +00:00
Simon Dardis cc95a9c557 [mips] Fix the predicates of jump and branch and link instructions
Reviewers: smaksimovic, atanasyan, abeserminji

Differential Revision: https://reviews.llvm.org/D46114

llvm-svn: 331175
2018-04-30 13:37:42 +00:00
Florian Hahn deb01ea126 [LV] Use BB::instructionsWithoutDebug to skip DbgInfo (NFC).
This patch updates some code responsible the skip debug info to use
BasicBlock::instructionsWithoutDebug. I think this makes things
slightly simpler and more direct.

Reviewers: mkuper, rengolin, dcaballe, aprantl, vsk

Reviewed By: rengolin

Differential Revision: https://reviews.llvm.org/D46254

llvm-svn: 331174
2018-04-30 13:28:08 +00:00
Benjamin Kramer 4aace8a3e0 [bindings] Fix dibuilder go bindings after r331114.
llvm-svn: 331171
2018-04-30 12:48:45 +00:00
Andrea Di Biagio 77bd1c748a [llvm-mca] Regenerate test Atom/resources-sse3.s. NFC
Before this change, it wrongly specified -mcpu=slm instead of -mcpu=atom.

llvm-svn: 331170
2018-04-30 12:13:04 +00:00
Andrea Di Biagio e9384eb13b [llvm-mca] Support for in-order CPU for -instruction-tables testing.
Added Intel Atom tests to verify that the tool correctly generates instruction
tables even if the CPU is in-order.

Fixes PR37282.

llvm-svn: 331169
2018-04-30 12:05:34 +00:00
Simon Pilgrim 318f816f49 [X86] Fix typo in skylake-avx512 model for PMAXSD/PMINSD instructions
The PMAXSD/PMINSD instregexs had been written as PMAX(C?)SD - looks like this was a search+replace error when matching float MAXSD/MINSD commutative instructions.

llvm-svn: 331167
2018-04-30 10:46:35 +00:00
Gabor Buella 61ff2864cb NFC - Typo fixes lib/VMCore -> lib/IR
llvm-svn: 331166
2018-04-30 10:18:11 +00:00
Simon Dardis 57c2095d1b [mips] Fix microMIPS loads and stores.
Previously these instructions were unselectable and instead were generated
through the instruction mapping tables.

Reviewers: atanasyan, smaksimovic, abeserminji

Differential Revision: https://reviews.llvm.org/D46055

llvm-svn: 331165
2018-04-30 09:44:44 +00:00
Sander de Smalen 5861c263e0 [AArch64][SVE] Asm: Improve diagnostics for gather loads.
This patch extends the 'isSVEVectorRegWithShiftExtend' function to 
improve diagnostics for SVE's gather load (scalar + vector) addressing 
modes. Instead of always suggesting the 'unscaled' addressing mode, 
the use of DiagnosticPredicate enables a more specific error message
in the context where the scaling is incorrect. For example:

  ld1h z0.d, p0/z, [x0, z0.d, lsl #2]
                                   ^ 
           shift amount should be '1'

Instead of suggesting the packed, unscaled addressing mode:
  expected 'z[0..31].d, (uxtw|sxtw)'

the assembler now suggests using the proper scaling:
  expected 'z[0..31].d, (lsl|uxtw|sxtw) #1'

Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, javed.absar

Reviewed By: fhahn

Differential Revision: https://reviews.llvm.org/D46124

llvm-svn: 331162
2018-04-30 07:24:38 +00:00
Craig Topper 5a4c88005c [X86] Add a Requires<[In64BitMode]> to FARJMP64
Otherwise we can try to assemble it in 32-bit mode and throw an assert in the encoder.

llvm-svn: 331161
2018-04-30 06:21:24 +00:00
Craig Topper d94002c414 [X86] Hide another instruction from the assembly matcher table to avoid a duplicate entry. NFC
llvm-svn: 331160
2018-04-30 06:21:23 +00:00
Craig Topper cda7690976 [X86] Remove some InstAliases aren't needed because a MnemonicAlias makes them unreachable.
llvm-svn: 331159
2018-04-30 06:21:22 +00:00
Craig Topper 429ae3d775 [X86] Remove some instructions from the Intel assembly matcher table as there are equivalent mode aware InstAliases that conflict.
The instructions have predicates of Not64BitMode, but there are identical strings in InstAliases that have Mode32Bit and Mode16Bit. But the ordering is uncontrolled and the less specific Not64BitMode was ordered first.

This patch hides the Not64BitMode from the table so there is no conflict anymore.

llvm-svn: 331158
2018-04-30 06:21:21 +00:00
Craig Topper ebc7de07ee [X86] Use a MnemonicAlias instead of an InstAlias.
llvm-svn: 331157
2018-04-30 06:21:19 +00:00
Craig Topper 64e7a16fe4 [X86] Remove support for accepting 'fnstsw %eax' and 'fnstsw %al'.
I assume this was done because gas accepted it at one point, but current versions of gas don't.

llvm-svn: 331154
2018-04-30 01:53:12 +00:00
Craig Topper b2bf3da152 [X86] Mark some more InstAliases as 'att' syntax only.
These aliases are used to default the memory forms of call and jmp to the size of the operating mode. This doesn't work for Intel syntax. We have a different hack in the AsmParser code itself to force a size on unsized memory operands.

llvm-svn: 331153
2018-04-30 01:53:10 +00:00
Nico Weber e7c4af32c6 Remove a dead #ifdef.
Unix/Threading.inc should never be included on _WIN32. See also
https://reviews.llvm.org/D30526#1082292

llvm-svn: 331151
2018-04-30 00:08:06 +00:00
Craig Topper 5731558979 [X86] Make 64-bit sysret/sysexit not ambiguous in Intel assembly syntax.
This also makes it default to the 32-bit non REX.W version in 64-bit mode. This seems to be more consistent with gas.

llvm-svn: 331149
2018-04-29 22:55:54 +00:00
Simon Pilgrim 288c73e7be [X86] Remove unnecessary BT InstRW overrides.
llvm-svn: 331147
2018-04-29 18:18:51 +00:00
Sander de Smalen afe1ee2180 [AArch64][AsmParser] NFC: Cleanup of addOperands functions
Most of the add<operandname>Operands() functions are the same
and can be replaced by using a single 'RenderMethod' in
the AArch64InstrFormats.td file. Since many of the scaled
immediates (with different scaling/bits) are the same, most of
these can reuse the same AsmOperandClass.

Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, javed.absar

Reviewed By: samparker

Differential Revision: https://reviews.llvm.org/D46122

llvm-svn: 331146
2018-04-29 18:18:21 +00:00
Sander de Smalen 50ded90072 [AArch64][SVE] Asm: Support for gather LD1/LDFF1 (vector + imm) load instructions.
Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, javed.absar

Reviewed By: SjoerdMeijer

Differential Revision: https://reviews.llvm.org/D46120

llvm-svn: 331145
2018-04-29 17:33:38 +00:00
Simon Pilgrim 8962c344f9 [llvm-mca][X86] Add BT resource tests to all models
llvm-svn: 331144
2018-04-29 15:45:31 +00:00
Simon Pilgrim d5ada498db [X86] Merge more instregex single matches to reduce InstrRW compile time.
llvm-svn: 331143
2018-04-29 15:33:15 +00:00
Simon Pilgrim 684a719270 [X86] Remove unnecessary add/adc+sub/sbb InstRW overrides.
llvm-svn: 331142
2018-04-29 14:16:17 +00:00
Simon Pilgrim 2d569361fc [llvm-mca][X86] Add add/adc + sub/sbb resource tests to all models
llvm-svn: 331140
2018-04-29 11:03:25 +00:00
Hideki Saito f2ec16ccc2 [NFC][LV][LoopUtil] Move LoopVectorizationLegality to its own file
Summary:
This is a follow up to D45420 (included here since it is still under review and this change is dependent on that) and D45072 (committed).
Actual change for this patch is LoopVectorize* and cmakefile. All others are all from D45420.

LoopVectorizationLegality is an analysis and thus really belongs to Analysis tree. It is modular enough and it is reusable enough ---- we can further improve those aspects once uses outside of LV picks up.

Hopefully, this will make it easier for people familiar with vectorization theory, but not necessarily LV itself to contribute, by lowering the volume of code they should deal with. We probably should start adding some code in LV to check its own capability (i.e., vectorization is legal but LV is not ready to handle it) and then bail out.


Reviewers: rengolin, fhahn, hfinkel, mkuper, aemerson, mssimpso, dcaballe, sguggill

Reviewed By: rengolin, dcaballe

Subscribers: egarcia, rogfer01, mgorny, llvm-commits

Differential Revision: https://reviews.llvm.org/D45552

llvm-svn: 331139
2018-04-29 07:26:18 +00:00
Craig Topper 18c4c8efaf [X86] Add suffixes to the LGDT/LIDT/SGDT/SIDT mnemonics in Intel syntax. Add aliases based on 16/32-bit mode to choose the default.
This allows the instruction selection to follow mode in Intel syntax. And allows a suffix to be used to change size.

This matches gas behavior from what I could tell.

llvm-svn: 331138
2018-04-29 06:24:09 +00:00
Craig Topper ebd3e4a69c [X86] Remove SLDT64m instruction.
It doesn't really exist. The instruction always writes 16-bits of memory. Putting a REX.w on it won't change anything.

While I was touching the encoding tests to remove it, I added some other missing register form test cases.

llvm-svn: 331135
2018-04-29 04:50:53 +00:00
Craig Topper 8e3dbfd725 [X86] Remove unnecessary InstAliases. NFCI
These used to disambiguate MOV16ms/MOV16sm from other size instructions that no longer exist.

llvm-svn: 331134
2018-04-29 04:06:02 +00:00
whitequark b18cd6d1d1 [LLVM-C] Eliminate an unused variable in a test.
This was introduced in r331123 and broke -Werror bots.

llvm-svn: 331132
2018-04-29 02:01:34 +00:00
Rafael Espindola ab0f3fddc8 Update my email address and description.
llvm-svn: 331131
2018-04-29 01:13:57 +00:00
Craig Topper a3f52aaa19 [X86] Use getX86SubSuperRegister in addGR32orGR64Operands in the AsmParser instead of duplicating its functionality. NFC
llvm-svn: 331128
2018-04-29 00:53:10 +00:00
Nico Weber 712e8d29c4 s/LLVM_ON_WIN32/_WIN32/, llvm
LLVM_ON_WIN32 is set exactly with MSVC and MinGW (but not Cygwin) in
HandleLLVMOptions.cmake, which is where _WIN32 defined too.  Just use the
default macro instead of a reinvented one.

See thread "Replacing LLVM_ON_WIN32 with just _WIN32" on llvm-dev and cfe-dev.
No intended behavior change.

This moves over all uses of the macro, but doesn't remove the definition
of it in (llvm-)config.h yet.

llvm-svn: 331127
2018-04-29 00:45:03 +00:00
Robert Widmann aec494f3c4 [LLVM-C] Add DIBuilder bindings to create import declarations
Summary: Add bindings to create import declarations for modules, functions, types, and other entities.  This wraps the conveniences available in the existing DIBuilder API, but these seem C++-specific.

Reviewers: whitequark, harlanhaskins, deadalnix

Reviewed By: whitequark

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D46167

llvm-svn: 331123
2018-04-28 22:32:07 +00:00
Craig Topper 06624e1a93 [X86] Restrict many of the InstAliases to either to only att or intel syntax. NFCI
Many of these aliases exist to give one syntax or the other a slightly different mnemonic and the other variant gets a duplicate of its normal mnemonic

This patch restricts a lot of these to only one variant so we don't get the duplication.

This removes a lot of duplicate entries from the matcher table. It also reduces the number of warnings printed when you enable the ambiguous match warning in tablegen.

llvm-svn: 331117
2018-04-28 18:46:11 +00:00
Simon Pilgrim badf63e95c [X86] Remove unnecessary rotate-carry folded InstRW overrides.
Merge some remaining instregex entries.

llvm-svn: 331116
2018-04-28 18:45:16 +00:00
Daniel Sanders 5eb9f581b6 [globalisel][legalizerinfo] Introduce dedicated extending loads and add lowerings for them
Summary:
Previously, a extending load was represented at (G_*EXT (G_LOAD x)).
This had a few drawbacks:
* G_LOAD had to be legal for all sizes you could extend from, even if
  registers didn't naturally hold those sizes.
* All sizes you could extend from had to be allocatable just in case the
  extend went missing (e.g. by optimization).
* At minimum, G_*EXT and G_TRUNC had to be legal for these sizes. As we
  improve optimization of extends and truncates, this legality requirement
  would spread without considerable care w.r.t when certain combines were
  permitted.
* The SelectionDAG importer required some ugly and fragile pattern
  rewriting to translate patterns into this style.

This patch begins changing the representation to:
* (G_[SZ]EXTLOAD x)
* (G_LOAD x) any-extends when MMO.getSize() * 8 < ResultTy.getSizeInBits()
which resolves these issues by allowing targets to work entirely in their
native register sizes, and by having a more direct translation from
SelectionDAG patterns.

This patch introduces the new generic instructions and new variation on
G_LOAD and adds lowering for them to convert back to the existing
representations.

Depends on D45466

Reviewers: ab, aditya_nandakumar, bogner, rtereshin, volkan, rovka, aemerson, javed.absar

Reviewed By: aemerson

Subscribers: aemerson, kristof.beyls, javed.absar, llvm-commits

Differential Revision: https://reviews.llvm.org/D45540

llvm-svn: 331115
2018-04-28 18:14:50 +00:00
Robert Widmann 2d2698c69c [LLVM-C] Miscellaneous Cleanups in DIBuilder Bindings
Summary:
* rL328953 does not include bindings for LLVMDIBuilderCreateClassType and LLVMDIBuilderCreateBitFieldMemberType despite declaring their prototypes.  Provide these bindings now.
* Switch to more precise types with specific numeric limits matching the DIBuilder's C++ API.

Reviewers: harlanhaskins, whitequark, deadalnix

Reviewed By: whitequark

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D46168

llvm-svn: 331114
2018-04-28 18:13:39 +00:00
Roman Lebedev 136867931a [InstCombine] Canonicalize variable mask in masked merge
Summary:
Masked merge has a pattern of: `((x ^ y) & M) ^ y`.
But, there is no difference between `((x ^ y) & M) ^ y` and `((x ^ y) & ~M) ^ x`,
We should canonicalize the pattern to non-inverted mask.

https://rise4fun.com/Alive/Yol

Reviewers: spatel, craig.topper

Reviewed By: spatel

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D45664

llvm-svn: 331112
2018-04-28 15:45:07 +00:00
Roman Lebedev 6b1e66b188 [InstCombine][NFC] Add tests for variable mask canonicalization in masked merge
Summary:
Masked merge has a pattern of: `((x ^ y) & M) ^ y`.
But, there is no difference between `((x ^ y) & M) ^ y` and `((x ^ y) & ~M) ^ x`,
We should canonicalize the pattern to non-inverted mask.

Differential Revision: https://reviews.llvm.org/D45663

llvm-svn: 331111
2018-04-28 15:45:00 +00:00
Simon Pilgrim 39d7720354 [X86] Remove unnecessary shift/rotate folded InstRW overrides.
llvm-svn: 331110
2018-04-28 15:32:19 +00:00
Simon Pilgrim 318e9d39ab [llvm-mca][X86] Add double shift resource tests to all relevant models
llvm-svn: 331109
2018-04-28 15:18:49 +00:00
Simon Pilgrim 4d0187c893 [llvm-mca][X86] Add shift/rotate resource tests to all relevant models
I intend to add further instruction tests to the resources-x86_64.s test file as required, but this initial commit is to help remove a load of unnecessary InstRW overrides in a future patch

llvm-svn: 331108
2018-04-28 14:56:18 +00:00
Simon Pilgrim 9f561dd54a [X86][SSE] Stop hard coding some instruction scheduler classes.
Make these arguments to the multiclass to allow easier specialization.

llvm-svn: 331107
2018-04-28 14:08:51 +00:00
Simon Pilgrim c2fa056a2d [X86][HW] Cleanup Haswell model. NFCI.
Moved LAHF/SAHF to instrs instead of instregex.

Removed some unnecessary instregex entries.

llvm-svn: 331106
2018-04-28 14:06:28 +00:00
Craig Topper 9e11f96df6 [X86] Remove mayLoad flag from BNDMK/BNDCL/BNDCN/BNDCU.
The instruction documentation specifically says that these instruction don't access memory.

llvm-svn: 331105
2018-04-28 06:58:27 +00:00
Craig Topper 6d6b2b9503 [X86] Change memory operand of BNDMK/BNDCL/BNDCU/BNDCN/BNDST to anymem.
These instruction don't use their memory operands as normal memory operands. They're just used as addresses. They don't have a size because they aren't directly representing a load or store.

llvm-svn: 331104
2018-04-28 06:58:26 +00:00
Serguei Katkov f4c681eb65 [SCEV] Touch the unsused stats variables for product build.
This is a fix by elimination compiler warnings considered as errors.

llvm-svn: 331103
2018-04-28 06:41:35 +00:00
Craig Topper ef3866a859 [X86] Remove REX.W from 64-bit mode BND instructions.
As far as I can tell from the docs, the instructions are automatically 64-bit in 64-bit mode. We don't need REX.W.

llvm-svn: 331102
2018-04-28 06:02:40 +00:00
Craig Topper 8a6532ae84 [X86] Rename BNDMOV instructions and hide redundant instruction encoding from the assembler.
Favor the 0x1a encoding for register/register move to match gas.

The instructions used RM and MR in their name along with rr/rm/mr at the end. To make more consistent with other instructions remove the RM/MR and use rr/rm/mr/rr_REV.

Hide the _REV encoding from the assembler but leave it for the disassembler.

llvm-svn: 331101
2018-04-28 06:02:39 +00:00
Max Kazantsev 303572f3df [NFC] Add some tests that demonstrate unrecognized three-way comparison patterns
llvm-svn: 331100
2018-04-28 04:38:21 +00:00
Serguei Katkov 6c6b40b330 [SCEV] Reduce the number of invocation to non trivial getExact function
The invocation of getExact in ScalarEvolution::getBackedgeTakenInfo is used
only for getting statistic and for assert. 
Even if statistics is disabled, the code related to it will be eliminated
the invocation to getExact itself will not be eliminated
because it may have side-effects like creation of new SCEVs.

So do invocation only when we collect statistics or executes asserts.

Reviewers: mkazantsev, sanjoy, javed.absar
Reviewed By: javed.absar
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D46178

llvm-svn: 331099
2018-04-28 03:53:36 +00:00
Jessica Paquette 0b6724917a [MachineOutliner] Add defs to calls + don't track liveness on outlined functions
This commit makes it so that if you outline a def of some register, then the
call instruction created by the outliner actually reflects that the register
is defined by the call. It also makes it so that outlined functions don't
have the TracksLiveness property.

Outlined calls shouldn't break liveness assumptions that someone might make.

This also un-XFAILs the noredzone test, and updates the calls test.

llvm-svn: 331095
2018-04-27 23:36:35 +00:00
Philip Reames 502d4481d4 [LoopGuardWidening] Make PostDomTree optional
The effect of doing so is not disrupting the LoopPassManager when mixing this pass with other loop passes.  This should help locality of access substaintially and avoids the cost of computing PostDom.

The assumption here is that the full GuardWidening (which does use PostDom) is run as a canonicalization before loop opts and that this version is just catching cases exposed by other loop passes.  (i.e. LoopPredication, IndVarSimplify, LoopUnswitch, etc..)

llvm-svn: 331094
2018-04-27 23:15:56 +00:00
Heejin Ahn d20d0648ed [DAGCombiner] Fix a case of 1 in non-splat vector pow2 divisor
Summary:
D42479 (rL329525) enabled SDIV combine for pow2 non-splat vector
dividers. But when there is a 1 in a vector, the instruction sequence to
be generated involves shifting a value by the number of its bit widths,
which is undefined
(c64f4dbfe3/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (L6000-L6006)).

Especially, in architectures that do not support vector instructions,
each of element in a vector will be computed separately using scalar
operations, and then the resulting value will be undef for '1' values
in a vector.

(All 1's vector is fine; only vectors mixed with 1 and others will be
affected.)

Reviewers: RKSimon, jgravelle-google

Subscribers: jfb, dschuff, sbc100, jgravelle-google, llvm-commits

Differential Revision: https://reviews.llvm.org/D46161

llvm-svn: 331092
2018-04-27 22:23:11 +00:00
Craig Topper d656410293 [X86] Make the STTNI flag intrinsics use the flags from pcmpestrm/pcmpistrm if the mask instrinsics are also used in the same basic block.
Summary:
Previously the flag intrinsics always used the index instructions even if a mask instruction also exists.

To fix fix this I've created a single ISD node type that returns index, mask, and flags. The SelectionDAG CSE process will merge all flavors of intrinsics with the same inputs to a s ingle node. Then during isel we just have to look at which results are used to know what instruction to generate. If both mask and index are used we'll need to emit two instructions. But for all other cases we can emit a single instruction.

Since I had to do manual isel anyway, I've removed the pseudo instructions and custom inserter code that was working around tablegen limitations with multiple implicit defs.

I've also renamed the recently added sse42.ll test case to sttni.ll since it focuses on that subset of the sse4.2 instructions.

Reviewers: chandlerc, RKSimon, spatel

Reviewed By: chandlerc

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D46202

llvm-svn: 331091
2018-04-27 22:15:33 +00:00
Adrian Prantl 4b542c6e64 Fix a bug that prevents global variables from having a DW_OP_deref.
For local variables the first DW_OP_deref is consumed by turning the
location kind into a memeory location, but that only makes sense for
values that are in a register to begin with, which cannot happen for
global variables that are attached to a symbol.

rdar://problem/39741860

This reapplies r330970 after fixing an uncovered bug in r331086 and
working around the situation caused by it.

llvm-svn: 331090
2018-04-27 22:05:31 +00:00
Reid Kleckner efc0f8cbdc [FastISel] Actually enable local value sinking by default
llvm-svn: 331088
2018-04-27 21:51:25 +00:00
Reid Kleckner a28e767f06 [FastISel] Fix local value sinking algorithmic complexity
Now local value sinking only scans and numbers instructions added
between the current flush point and the last flush point. This ensures
that ISel is overall linear in the size of the BB.

Fixes PR37010 and re-enables local value sinking by default.

llvm-svn: 331087
2018-04-27 21:48:51 +00:00
Adrian Prantl 210a29de7b Fix a bug in GlobalOpt's handling of DIExpressions.
This patch adds support for fragment expressions
TryToShrinkGlobalToBoolean() which were previously just dropped.

Thanks to Reid Kleckner for providing me a reproducer!

llvm-svn: 331086
2018-04-27 21:41:36 +00:00
Roman Lebedev 6959b8e76f [PatternMatch] Stabilize the matching order of commutative matchers
Summary:
Currently, we
1. match `LHS` matcher to the `first` operand of binary operator,
2. and then match `RHS` matcher to the `second` operand of binary operator.
If that does not match, we swap the `LHS` and `RHS` matchers:
1. match `RHS` matcher to the `first` operand of binary operator,
2. and then match `LHS` matcher to the `second` operand of binary operator.

This works ok.
But it complicates writing of commutative matchers, where one would like to match
(`m_Value()`) the value on one side, and use (`m_Specific()`) it on the other side.

This is additionally complicated by the fact that `m_Specific()` stores the `Value *`,
not `Value **`, so it won't work at all out of the box.

The last problem is trivially solved by adding a new `m_c_Specific()` that stores the
`Value **`, not `Value *`. I'm choosing to add a new matcher, not change the existing
one because i guess all the current users are ok with existing behavior,
and this additional pointer indirection may have performance drawbacks.
Also, i'm storing pointer, not reference, because for some mysterious-to-me reason
it did not work with the reference.

The first one appears trivial, too.
Currently, we
1. match `LHS` matcher to the `first` operand of binary operator,
2. and then match `RHS` matcher to the `second` operand of binary operator.
If that does not match, we swap the ~~`LHS` and `RHS` matchers~~ **operands**:
1. match ~~`RHS`~~ **`LHS`** matcher to the ~~`first`~~ **`second`** operand of binary operator,
2. and then match ~~`LHS`~~ **`RHS`** matcher to the ~~`second`~ **`first`** operand of binary operator.

Surprisingly, `$ ninja check-llvm` still passes with this.
But i expect the bots will disagree..

The motivational unittest is included.
I'd like to use this in D45664.

Reviewers: spatel, craig.topper, arsenm, RKSimon

Reviewed By: craig.topper

Subscribers: xbolva00, wdng, llvm-commits

Differential Revision: https://reviews.llvm.org/D45828

llvm-svn: 331085
2018-04-27 21:23:20 +00:00
Simon Pilgrim 8ee7d01dcf [X86] Merge some x87 instruction instregex single matches. NFCI.
llvm-svn: 331084
2018-04-27 21:14:19 +00:00
Sanjay Patel 2677038cc0 [Reassociate] add a test with debug info; NFC
As suggested in D45842 
(although still not sure if we're going to advance that),
we must invalidate references to instructions that have
been recycled (operands were changed, so result is different).

llvm-svn: 331083
2018-04-27 21:14:15 +00:00
Daniel Sanders 4f246999d9 Attempt to fix remaining build failures after r331071 by changing the tuple to a struct
Some of the bots were failing in a different way to the others. These were
unable to compare tuples. Fix this by changing to a struct, thereby avoiding
the quirks of tuples.

llvm-svn: 331081
2018-04-27 21:03:27 +00:00
Philip Reames 5a6482450a [LICM] Reduce nesting with an early return [NFC]
llvm-svn: 331080
2018-04-27 20:58:30 +00:00
Philip Reames e4ec473b3f [MustExecute/LICM] Special case first instruction in throwing header
We currently have a hard to solve analysis problem around the order of instructions within a potentially throwing block.  We can't cheaply determine whether a given instruction is before the first potential throw in the block.  While we're working on that in the background, special case the first instruction within the header.

why this particular special case?  Well, headers are guaranteed to execute if the loop does, and it turns out we tend to produce this form in practice.

In a follow on patch, I tend to extend LICM with an alternate approach which works for any instruction in the header before the first throw, but this is the best I can come up with other users of the analysis (such as store promotion.)

Note: I can't show the difference in the analysis result since we're ORing in the expensive instruction walk used by SCEV.  Using the full walk is not suitable for a general solution.
llvm-svn: 331079
2018-04-27 20:44:01 +00:00
Vlad Tsyrklevich 201a1086cf ELFObjectWriter: Allow one unique symver per symbol
Summary:
Only allow a single unique .symver alias per symbol. This matches the
behavior of gas. I noticed that we ignored multiple mismatched symver
directives looking at https://reviews.llvm.org/D45798

Reviewers: pcc, tejohnson, espindola

Reviewed By: pcc

Subscribers: emaste, arichardson, llvm-commits, kcc

Differential Revision: https://reviews.llvm.org/D45845

llvm-svn: 331078
2018-04-27 20:32:34 +00:00
Daniel Neilson a19ee7d7b6 [LV] Common duplicate vector load/store address calculation (NFC)
Summary:
Commoning some obviously copy/paste code in
InnerLoopVectorizer::vectorizeMemoryInstruction

llvm-svn: 331076
2018-04-27 20:29:18 +00:00
Daniel Sanders a05e8d3e68 Attempt to fix build failure after r331071 using std::make_tuple
llvm-svn: 331074
2018-04-27 20:17:44 +00:00
Jun Bum Lim 9e3e14b5f9 [PostRASink] extend the live-in check for all aliased registers
Extend the live-in check for all aliased registers so that we can
allow sinking Copy instructions when only implicit def is in successor's
live-in.

llvm-svn: 331072
2018-04-27 19:59:20 +00:00
Daniel Sanders 27fe8a5011 [globalisel][legalizerinfo] Add support for legalization based on the MachineMemOperand
Summary:
Currently only the memory size is supported but others can be added as
needed.

narrowScalar for G_LOAD and G_STORE now correctly update the
MachineMemOperand and will refuse to legalize atomics since those need more
careful expansions to maintain atomicity.

Reviewers: ab, aditya_nandakumar, bogner, rtereshin, aemerson, javed.absar

Reviewed By: aemerson

Subscribers: aemerson, rovka, kristof.beyls, javed.absar, llvm-commits

Differential Revision: https://reviews.llvm.org/D45466

llvm-svn: 331071
2018-04-27 19:48:53 +00:00
Paul Semel 3a8a56b8b7 [llvm-objcopy] Add --weaken-symbol (-W) option
llvm-svn: 331070
2018-04-27 19:16:27 +00:00
Paul Semel ee5be798da [llvm-objcopy] Add --globalize-symbol option
llvm-svn: 331068
2018-04-27 19:09:44 +00:00
Jun Bum Lim 47aece1344 [CodeGen] Use RegUnits to track register aliases (NFC)
Summary: Use RegUnits to track register aliases in PostRASink and AArch64LoadStoreOptimizer.

Reviewers: thegameg, mcrosier, gberry, qcolombet, sebpop, MatzeB, t.p.northover, javed.absar

Reviewed By: thegameg, sebpop

Subscribers: javed.absar, llvm-commits, kristof.beyls

Differential Revision: https://reviews.llvm.org/D45695

llvm-svn: 331066
2018-04-27 18:44:37 +00:00
Simon Pilgrim 8a937e00d8 [X86] Split WriteFBlend/WriteFVarBlend/WriteFVarShuffle into XMM and YMM/ZMM scheduler classes
This removes all the WriteFBlend/WriteFVarBlend InstRW overrides - some WriteFVarShuffle remain to be fixed.

llvm-svn: 331065
2018-04-27 18:19:48 +00:00
Mark Searles a6322924e6 [AMDGPU][Waitcnt] Update a few tests to use default waitcnt pass (si-insert-waitcnts) rather than old pass (si-insert-waits); this is a small step towards the overall goal of removing the old waitcnt pass, which is no longer maintained.
Differential Revision: https://reviews.llvm.org/D46154

llvm-svn: 331062
2018-04-27 17:59:15 +00:00
Philip Reames de5a1da2d2 [GuardWidening] Add some clarifying comments about heuristics [NFC]
llvm-svn: 331061
2018-04-27 17:41:37 +00:00
Philip Reames 9258e9d190 [LoopGuardWidening] Split out a loop pass version of GuardWidening
The idea is to have a pass which performs the same transformation as GuardWidening, but can be run within a loop pass manager without disrupting the pass manager structure.  As demonstrated by the test case, this doesn't quite get there because of issues with post dom, but it gives a good step in the right direction.  the motivation is purely to reduce compile time since we can now preserve locality during the loop walk.

This patch only includes a legacy pass.  A follow up will add a new style pass as well.

llvm-svn: 331060
2018-04-27 17:29:10 +00:00
Sanjay Patel f6d595bd44 [docs] add fp-cast-overflow-workaround options to release notes
llvm-svn: 331059
2018-04-27 16:33:35 +00:00
Nirav Dave 6b01b88012 [MC] Undo spurious commit added into r331052.
llvm-svn: 331055
2018-04-27 16:16:06 +00:00
Simon Pilgrim c3c767bf50 [X86] Split WriteFHadd into XMM and YMM/ZMM scheduler classes
This removes all the HADD/HSUB PS/PD InstRW overrides.

llvm-svn: 331054
2018-04-27 16:11:57 +00:00
Nirav Dave 38b4b54a2c [MC] Provide default value for IsResolved.
llvm-svn: 331052
2018-04-27 16:11:24 +00:00
Simon Pilgrim b2aa89c909 [X86][AVX] Split WriteFLogic into XMM and YMM/ZMM scheduler classes
This removes all the AND/ANDN/OR/XOR PS/PD InstRW overrides.

llvm-svn: 331051
2018-04-27 15:50:33 +00:00
Simon Dardis e3c3c5a7a7 [mips] Analyze and provide selection patterns microMIPSR6 branches
These branches were previously unanalyzable and unselectable. Add them and
recognize how to generate their inverses.

Reviewers: smaksimovic, atanasyan, abeserminji

Differential Revision: https://reviews.llvm.org/D46113

llvm-svn: 331050
2018-04-27 15:49:49 +00:00
Nirav Dave 1b5533c9e8 [MC] Modify MCAsmStreamer to always build MCAssembler. NFCI.
llvm-svn: 331048
2018-04-27 15:45:54 +00:00
Nirav Dave 8728e097df [MC] Allow MCAssembler to be constructed without all subcomponents. NFCI.
llvm-svn: 331047
2018-04-27 15:45:27 +00:00
Francis Visoiu Mistrih c855e92ca9 [AArch64] Place the first ldp at the end when ReverseCSRRestoreSeq is true
Put the first ldp at the end, so that the load-store optimizer can run
and merge the ldp and the add into a post-index ldp.

This didn't work in case no frame was needed and resulted in code size
regressions.

llvm-svn: 331044
2018-04-27 15:30:54 +00:00
Kostya Kortchinsky 03b7c4dabb [CMake] Enable warnings for runtimes
Summary:
`HandleLLVMOptions` adds `-w` to the cflags if `LLVM_ENABLE_WARNINGS` is not on.
With `-w`, `check_cxx_compiler_flag` doesn't error out for unsupported flags
(for example `-mcrc` on x86_64), and those flags end up being detected as
working - and really they aren't.

I am not entirely sure what the best way to solve this is, but setting
`LLVM_ENABLE_WARNINGS` prior to including `HandleLLVMOptions` does the job.

Reviewers: phosek, beanz

Reviewed By: phosek

Subscribers: mgorny, llvm-commits

Differential Revision: https://reviews.llvm.org/D46079

llvm-svn: 331042
2018-04-27 15:10:50 +00:00
Jonas Paulsson 9a485985cd [SystemZ] Remove scheduling info from some Pseudo instructions (NFC).
If the MachineInstr uses a custom inserter and is then erased after
instruction selection, there is no use for mapping it to a sched class.

Review: Ulrich Weigand
llvm-svn: 331040
2018-04-27 14:09:03 +00:00
Florian Hahn f3fea0f11f [LoopInterchange] Allow some loops with PHI nodes in the exit block.
We currently support LCSSA PHI nodes in the outer loop exit, if their
incoming values do not come from the outer loop latch or if the
outer loop latch has a single predecessor. In that case, the outer loop latch
will be executed only if the inner loop gets executed. If we have multiple
predecessors for the outer loop latch, it may be executed even if the inner
loop does not get executed.

This is a first step to support the case described in
https://bugs.llvm.org/show_bug.cgi?id=30472

Reviewers: efriedma, karthikthecool, mcrosier

Reviewed By: efriedma

Differential Revision: https://reviews.llvm.org/D43237

llvm-svn: 331037
2018-04-27 13:52:51 +00:00
Oliver Stannard 76088a5929 [AArch64] Codegen for v8.2A dot product intrinsics
This adds IR intrinsics for the AArch64 dot-product instructions introduced in
v8.2-A.

Differential revisioon: https://reviews.llvm.org/D46107

llvm-svn: 331036
2018-04-27 13:45:32 +00:00
Benjamin Kramer 733c7fc55d [NVPTX] Turn on Loop/SLP vectorization
Since PTX has grown a <2 x half> datatype vectorization has become more
important. The late LoadStoreVectorizer intentionally only does loads
and stores, but now arithmetic has to be vectorized for optimal
throughput too.

This is still very limited, SLP vectorization happily creates <2 x half>
if it's a legal type but there's still a lot of register moving
happening to get that fed into a vectorized store. Overall it's a small
performance win by reducing the amount of arithmetic instructions.

I haven't really checked what the loop vectorizer does to PTX code, the
cost model there might need some more tweaks. I didn't see it causing
harm though.

Differential Revision: https://reviews.llvm.org/D46130

llvm-svn: 331035
2018-04-27 13:36:05 +00:00
Simon Pilgrim aef5ca7299 [X86] Replace some system instruction instregex single matches with instrs entry. NFCI.
llvm-svn: 331034
2018-04-27 13:32:42 +00:00
Aleksandar Beserminji 3546c1603a [mips] Fix how compiler fuse instructions to fmadd/fmsub
This patch makes compiler does not fuse fmul and fadd/fsub into
fmadd/fmsub by default. Instead, -fp-contract=fast option can
be used when such behavior is desired.

Differential Revision: https://reviews.llvm.org/D46057

llvm-svn: 331033
2018-04-27 13:30:27 +00:00
Oliver Stannard f3632143da [ARM] Codegen for v8.2A dot product intrinsics
This adds IR intrinsics for the ARM dot-product instructions introduced in
v8.2-A.

Differential revision: https://reviews.llvm.org/D46106

llvm-svn: 331032
2018-04-27 12:50:40 +00:00
Alex Bradbury f5800a2aa0 [RISCV] Add remat.ll test case
This test case demonstrates suboptimal codegen due to the fact that simple 
constants aren't recognised as rematerialisable.

llvm-svn: 331028
2018-04-27 11:50:30 +00:00
David Green c4cccea4c9 [ARM] Enable misched for R52.
Back when the R52 schedule was added in rL286949, there was no way
to enable machine schedules in ARM for specific cores. Since then a
target feature has been added. This enables the feature for R52,
removing the need to manually specify compiler flags.

llvm-svn: 331027
2018-04-27 11:29:49 +00:00
Mikhail Maltsev ffaa8a8781 [IR] Do not assume that function pointers are aligned
Summary:
The value tracking analysis uses function alignment to infer that the
least significant bits of function pointers are known to be zero.
Unfortunately, this is not correct for ARM targets: the least
significant bit of a function pointer stores the ARM/Thumb state
information (i.e., the LSB is set for Thumb functions and cleared for
ARM functions).

The original approach (https://reviews.llvm.org/D44781) introduced a
new field for function pointer alignment in the DataLayout structure
to address this. But it seems unlikely that optimizations based on
function pointer alignment would bring much benefit in practice to
justify the additional maintenance burden, so this patch simply
assumes that function pointer alignment is always unknown.

Reviewers: javed.absar, efriedma

Reviewed By: efriedma

Subscribers: kristof.beyls, llvm-commits, hfinkel, rogfer01

Differential Revision: https://reviews.llvm.org/D46110

llvm-svn: 331025
2018-04-27 09:12:12 +00:00
Petar Jovanovic d4349f3bf6 [mips] Add support for Virtualization ASE
This includes

  Instructions: tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr, hypcall
                mfgc0, mtgc0, mfhgc0, mthgc0, dmfgc0, dmtgc0,

  Assembler directives: .set virt, .set novirt, .module virt, .module novirt

  Attribute: virt

  .MIPS.abiflags: VZ (0x100)

Patch by Vladimir Stefanovic.

Differential Revision: https://reviews.llvm.org/D44905

llvm-svn: 331024
2018-04-27 09:12:08 +00:00
Serguei Katkov 1956a48d27 [SCEV] Add trivial case handling for umin utilities. NFC.
Reviewers: sanjoy, mkazantsev
Reviewed By: mkazantsev
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D46175

llvm-svn: 331022
2018-04-27 08:02:50 +00:00
Serguei Katkov fa7fd13cf8 [SCEV] Introduce bulk umin creation utilities
Add new umin creation method which accepts a list of operands.

SCEV does not represents umin which is required in getExact, so
it transforms umin to umax with not. As a result the transformation of
tree of max to max with several operands does not work.
We just use the new introduced method for creation umin from several operands.

Reviewers: sanjoy, mkazantsev
Reviewed By: sanjoy
Subscribers: javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D46047

llvm-svn: 331015
2018-04-27 03:56:53 +00:00
Matt Morehouse 1ae1febfde Revert "[SimplifyLibcalls] Replace locked IO with unlocked IO"
This reverts r331002 due to sanitizer bot breakage.

llvm-svn: 331011
2018-04-27 01:48:09 +00:00
Eli Friedman e06539456c [LowerTypeTests] Mark .cfi.jumptable nounwind.
It doesn't unwind, and the wrong marking leads to the creation of an
.eh_frame section when it isn't necessary.

Differential Revision: https://reviews.llvm.org/D46082

llvm-svn: 331008
2018-04-27 00:32:24 +00:00
Eli Friedman da018e5687 [MachineOutliner] Don't outline from functions with a section marking.
The program might have unusual expectations for functions; for example,
the Linux kernel's build system warns if it finds references from .text
to .init.data.

I'm not sure this is something we actually want to make any guarantees
about (there isn't any explicit rule that would disallow outlining
in this case), but we might want to be conservative anyway.

Differential Revision: https://reviews.llvm.org/D46091

llvm-svn: 331007
2018-04-27 00:21:34 +00:00
Sam Clegg e0658119ba typo
llvm-svn: 331006
2018-04-27 00:17:24 +00:00
Sam Clegg d5504a0a62 [WebAssembly] Section symbols must have local binding
Summary: Also test for symbols information in test/MC/WebAssembly/debug-info.ll.

Subscribers: jfb, dschuff, jgravelle-google, aheejin, sunfish, JDevlieghere, llvm-commits

Differential Revision: https://reviews.llvm.org/D46160

llvm-svn: 331005
2018-04-27 00:17:21 +00:00
David Bolvansky 2c9cc9c731 [SimplifyLibcalls] Replace locked IO with unlocked IO
Summary: If file stream arg is not captured and source is fopen, we could replace IO calls by unlocked IO ("_unlocked" function variants) to gain better speed,

Reviewers: efriedma, RKSimon, spatel, sanjoy, hfinkel, majnemer

Subscribers: lebedev.ri, llvm-commits

Differential Revision: https://reviews.llvm.org/D45736

llvm-svn: 331002
2018-04-26 22:31:43 +00:00
Matt Davis ad78e6673c [MCA] [NFC] Remove unused Index formal from ResourceManager::issueInstruction
Summary: The instruction index was never referenced in the body.  Just a minor cleanup.

Reviewers: andreadb

Reviewed By: andreadb

Subscribers: javed.absar, gbedwell, llvm-commits

Differential Revision: https://reviews.llvm.org/D46142

llvm-svn: 331001
2018-04-26 22:30:40 +00:00
Matt Davis 3e790840a9 [Docs] Escape the @ symbol, so that it appears in documentation output. [NFC]
Summary:
The '@' character is a special character in Doxygen.  In a handful of cases we were not escaping this character which resulted in llvm intrinsics not being rendered properly.  Specifically, the @llvm part was removed.  

For example, see https://llvm.org/doxygen/classllvm_1_1AssumptionCache.html.  There are a few references to '.assume' without the @llvm. prefix.  This patch corrects this.

Reviewers: sanjoy

Reviewed By: sanjoy

Subscribers: llvm-commits, sanjoy

Differential Revision: https://reviews.llvm.org/D45981

llvm-svn: 330998
2018-04-26 21:55:45 +00:00
Chandler Carruth 16429acacb [x86] Revert r330322 (& r330323): Lowering x86 adds/addus/subs/subus intrinsics
The LLVM commit introduces a crash in LLVM's instruction selection.

I filed http://llvm.org/PR37260 with the test case.

llvm-svn: 330997
2018-04-26 21:46:01 +00:00
Roman Lebedev 33095e3610 [InstCombine][NFC] Regenerate checks in or-xor.ll
llvm-svn: 330996
2018-04-26 21:41:56 +00:00
Reid Kleckner 584cb9628e Fix WAsm dwarfdump.ll test on Windows
llvm-svn: 330995
2018-04-26 21:13:59 +00:00
Roman Lebedev cabaeac29c [InstCombine][NFC] Regenerate checks in and-or-not.ll
llvm-svn: 330994
2018-04-26 21:13:09 +00:00
Adrian Prantl 855b91022d Revert "Fix a bug that prevents global variables from having a DW_OP_deref."
This reverts commit r3309704 while investigating bot breakage.

llvm-svn: 330993
2018-04-26 20:59:58 +00:00
Sanjoy Das 6f1937b10f [InstCombine] Simplify Add with remainder expressions as operands.
Summary:
Simplify integer add expression X % C0 + (( X / C0 ) % C1) * C0 to
X % (C0 * C1).  This is a common pattern seen in code generated by the XLA
GPU backend.

Add test cases for this new optimization.

Patch by Bixia Zheng!

Reviewers: sanjoy

Reviewed By: sanjoy

Subscribers: efriedma, craig.topper, lebedev.ri, llvm-commits, jlebar

Differential Revision: https://reviews.llvm.org/D45976

llvm-svn: 330992
2018-04-26 20:52:28 +00:00
Sanjoy Das 0e643db48f Add test cases to prepare for the optimization that simplifies Add with
remainder expressions as operands.

Summary:
Add test cases to prepare for the new optimization that Simplifies integer add
expression X % C0 + (( X / C0 ) % C1) * C0 to X % (C0 * C1).

Patch by Bixia Zheng!

Reviewers: sanjoy

Reviewed By: sanjoy

Subscribers: jlebar, llvm-commits

Differential Revision: https://reviews.llvm.org/D46017

llvm-svn: 330991
2018-04-26 20:52:27 +00:00
Roman Tereshin 38489ed416 [GlobalISel] Reporting rules covered as part of the InstructionSelect's debug-only printing
The main goal of this change is to make it much easier to track which
rules are actually covered by Testgen'erated regression tests.

Reviewers: aemerson, dsanders

Differential Revision: https://reviews.llvm.org/D46095

llvm-svn: 330988
2018-04-26 20:22:17 +00:00
Roman Lebedev 7cc56f1599 [InstCombine][NFC] add2.ll: add a few commutative checks.
Fixes some missing test coverage in InstCombineAddSub.cpp, visitAdd()

llvm-svn: 330986
2018-04-26 20:07:17 +00:00
Roman Lebedev 1efe879641 [InstCombine][NFC] Autogenerate checks in add2.ll
llvm-svn: 330985
2018-04-26 20:07:12 +00:00
Simon Atanasyan d4d892ff9f [mips] Accept 32-bit offsets for lb and lbu commands
`lb` and `lbu` commands accepts 16-bit signed offsets. But GAS accepts
larger offsets for these commands. If an offset does not fit in 16-bit
range, `lb` command is translated into lui/lb or lui/addu/lb series.
It's interesting that initially LLVM assembler supported this feature,
but later it was broken.

This patch restores support for 32-bit offsets. It replaces `mem_simm16`
operand for `LB` and `LBu` definitions by the new `mem_simmptr` operand.
This operand is intended to check that offset fits to the same size as
using for pointers. Later we will be able to extend this rule and
accepts 64-bit offsets when it is possible.

Some issues remain:
- The regression also affects LD, SD, LH, LHU commands. I'm going
  to fix them by a separate patch.

- GAS accepts any 32-bit values as an offset. Now LLVM accepts signed
  16-bit values and this patch extends the range to signed 32-bit offsets.
  In other words, the following code accepted by GAS and still triggers
  an error by LLVM:
```
  lb      $4, 0x80000004

  # gas
  lui     a0, 0x8000
    lb      a0, 4(a0)
```

- In case of 64-bit pointers GAS accepts a 64-bit offset and translates
  it to the li/dsll/lb series of commands. LLVM still rejects it.
  Probably this feature has never been implemented in LLVM. This issue
  is for a separate patch.
```
  lb      $4, 0x800000001

  # gas
  li      a0, 0x8000
  dsll    a0, a0, 0x14
  lb      a0, 4(a0)
```

Differential Revision: https://reviews.llvm.org/D45020

llvm-svn: 330983
2018-04-26 19:55:28 +00:00
Sam Clegg 6a31a0d694 [WebAssembly] Write DWARF data into wasm object file
- Writes ".debug_XXX" into corresponding custom sections.
- Writes relocation records into "reloc.debug_XXX" sections.

Patch by Yury Delendik!

Differential Revision: https://reviews.llvm.org/D44184

llvm-svn: 330982
2018-04-26 19:27:28 +00:00
Matt Arsenault 540512c297 DAG: Fix not legalizing vector fcanonicalizes
If an fcanoncialize was done on a vector type that was legal,

llvm-svn: 330981
2018-04-26 19:21:37 +00:00
Matt Arsenault fcc5ba46b7 AMDGPU: Extend extract_vector_elt fneg combine to fabs
Fixes a regression in a future commit.

llvm-svn: 330980
2018-04-26 19:21:32 +00:00
Matt Arsenault 8474803c7c AMDGPU: Consolidate SubtargetPredicate definitions
llvm-svn: 330979
2018-04-26 19:21:26 +00:00
Justin Bogner 65c9e3dd17 Specify REQUIRES: default_triple in a few tests
These were all failing when specifying LLVM_DEFAULT_TARGET_TRIPLE=''.

llvm-svn: 330977
2018-04-26 19:15:25 +00:00
Geoff Berry 08ab8c9544 [AArch64] Fix scavenged spill slot base when stack realignment required.
Summary:
Use the FP for scavenged spill slot accesses to prevent corruption of
the callee-save region when the SP is re-aligned.

Based on problem and patch reported by @paulwalker-arm

This is an alternative to solution proposed in D45770

Reviewers: t.p.northover, paulwalker-arm, thegameg, javed.absar

Subscribers: qcolombet, mcrosier, paulwalker-arm, kristof.beyls, rengolin, javed.absar, llvm-commits

Differential Revision: https://reviews.llvm.org/D46063

llvm-svn: 330976
2018-04-26 18:50:45 +00:00
Roman Lebedev 3d7b22621c [NFC][InstCombine] rem.ll: add a few commutative tests.
This closes a gap in missing test coverage in
isKnownToBeAPowerOfTwo() from ValueTracking.cpp

llvm-svn: 330975
2018-04-26 18:44:37 +00:00
Roman Lebedev e117e1a440 [NFC][InstCombine] Regenerate rem.ll test
llvm-svn: 330974
2018-04-26 18:44:32 +00:00
Alexander Shaposhnikov 40e9bdf9af [llvm-objcopy] Implement --redefine-sym option
This diff implements --redefine-sym option 
for changing the name of a symbol.

Test plan: make check-all

Differential revision: https://reviews.llvm.org/D46029

llvm-svn: 330973
2018-04-26 18:28:17 +00:00
Michael Berg 15c0515a21 augmenting description for fcmp fmf - NFC
llvm-svn: 330972
2018-04-26 18:17:58 +00:00
Adrian Prantl e42805d07c Fix a bug that prevents global variables from having a DW_OP_deref.
For local variables the first DW_OP_deref is consumed by turning the
location kind into a memeory location, but that only makes sense for
values that are in a register to begin with, which cannot happen for
global variables that are attached to a symbol.

rdar://problem/39741860

llvm-svn: 330970
2018-04-26 18:17:04 +00:00
Sam Clegg 6bb5a41f99 [WebAssembly] Add version to object file metadata
Summary: See https://github.com/WebAssembly/tool-conventions/issues/54

Subscribers: jfb, dschuff, jgravelle-google, aheejin, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D46069

llvm-svn: 330969
2018-04-26 18:15:32 +00:00
Andrea Di Biagio b31f918979 [Tablegen] SubtargetEmitter: move the logic that prints predicates for variant scheduling classes to helper functions. NFC
llvm-svn: 330968
2018-04-26 18:03:24 +00:00
Haicheng Wu b09308d82a [GlobalMerge] Fix a typo
now => know

llvm-svn: 330965
2018-04-26 17:56:50 +00:00
Vlad Tsyrklevich b768d235a9 Revert "Enable EliminateAvailableExternally pass for -O1"
This reverts commit r330961 because it breaks a handful of clang tests.

llvm-svn: 330964
2018-04-26 17:54:53 +00:00
Paul Semel b492494c0f [llvm-objcopy] Add --localize-symbol option
llvm-svn: 330963
2018-04-26 17:44:43 +00:00
Vlad Tsyrklevich 3b59a8aba0 Update stale comment in AsmWriter.cpp
Summary:
The old comment referred to llvm/IR/Writer.h which doesn't longer exist.
This patch replaces it with an up-to-date description of AsmWriter library.

Patch by Alex Yursha.

Reviewers: gribozavr, vlad.tsyrklevich

Reviewed By: vlad.tsyrklevich

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D45895

llvm-svn: 330962
2018-04-26 17:34:51 +00:00
Vlad Tsyrklevich 42c5a9c29a Enable EliminateAvailableExternally pass for -O1
Summary:
Follow-up to D43690, the EliminateAvailableExternally pass currently
runs under -O0 and -O2 and up. Under -O1 we would still want to drop
available_externally symbols to reduce space without inlining having
run.

Reviewers: tejohnson

Reviewed By: tejohnson

Subscribers: mehdi_amini, llvm-commits, kcc

Differential Revision: https://reviews.llvm.org/D46093

llvm-svn: 330961
2018-04-26 17:33:24 +00:00
Sam Clegg 8c4b0ce2b1 [WebAssembly] objdump: Don't assume all relocations have symbols
Subscribers: jfb, dschuff, jgravelle-google, aheejin, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D46134

llvm-svn: 330959
2018-04-26 17:05:04 +00:00
Sanjay Patel c5ded68077 [docs] provide the specific sanitizer option to detect junk-in-the-ftrunc
llvm-svn: 330958
2018-04-26 17:04:07 +00:00
Sam Clegg f676cdd515 [WebAssembly] Implement getRelocationValueString()
And use it in llvm-objdump.

Differential Revision: https://reviews.llvm.org/D46092

llvm-svn: 330957
2018-04-26 16:41:51 +00:00
Simon Dardis f760b2c087 [mips] Fix a test case which is keeping the expensive checks bot win red (NFC)
llvm-svn: 330956
2018-04-26 16:22:47 +00:00
Mark Searles 2a19af6e17 [AMDGPU][Waitcnt] As of gfx7, VMEM operations do not increment the export counter and the input registers are available in the next instruction; update the waitcnt pass to take this into account.
Differential Revision: https://reviews.llvm.org/D46067

llvm-svn: 330954
2018-04-26 16:11:19 +00:00
Simon Dardis 8086b9db3d [mips] Correct the definitions of some control instructions
Correct the definitions of ei, di, eret, deret, wait, syscall and break.
Also provide microMIPS specific aliases to match the MIPS aliases.

Additionally correct the definition of the wait instruction so that
it is present in the instruction mapping tables.

Reviewers: smaksimovic, abeserminji, atanasyan

Differential Revision: https://reviews.llvm.org/D45939

llvm-svn: 330952
2018-04-26 16:06:34 +00:00
Sanjay Patel 5a90285bd9 [DAGCombiner] limit ftrunc optimizations with function attribute
As noted, the attribute name is subject to change once we have
the clang side implemented, but it's clear that we need some
kind of attribute-based predication here based on the discussion
for:
rL330437

llvm-svn: 330951
2018-04-26 16:04:44 +00:00
Sanjay Patel 99a5f396d4 [x86] add tests to show potential opt-out of ftrunc optimization; NFC
This is another preliminary step for disabling this transform as 
discussed in the post-commit thread for:
rL330437
I'm using one of the names suggested there for the attribute, but 
we can fix that up as needed once the clang side of this is sorted 
out. 

llvm-svn: 330950
2018-04-26 15:36:15 +00:00
Alex Bradbury fda6037e98 [RISCV] Implement isLoadFromStackSlot and isStoreToStackSlot
This causes some slight shuffling but no meaningful codegen differences on the 
corpus I used for testing, but it has a larger impact when combined with e.g. 
rematerialisation. Regardless, it makes sense to report as accurate 
target-specific information as possible.

llvm-svn: 330949
2018-04-26 15:34:27 +00:00
Benjamin Kramer 7dd437710e [NVPTX] Make the legalizer expand shufflevector of <2 x half>
There's no direct instruction for this, but it's trivially implemented
with two movs. Without this the code generator just dies when
encountering a shufflevector.

Differential Revision: https://reviews.llvm.org/D46116

llvm-svn: 330948
2018-04-26 15:26:29 +00:00
Sanjay Patel a5da086386 [DAGCombiner] refactor FP->int->FP folds; NFC
As discussed in the post-review comments for rL330437,
we need to guard this fold to allow existing code to
keep working with the undefined behavior that they've
come to rely on.

That would mean duplicating more code than we already 
have, so let's fix that first. 

llvm-svn: 330947
2018-04-26 15:20:18 +00:00