Commit Graph

27 Commits

Author SHA1 Message Date
David Green d96161a179 [ARM/AArch64] Move REQUIRES after update_cc_test_checks line. NFC
c17d9b4b12 added REQUIRES lines to a lot of Arm and AArch64
test, but added them to the very beginning, before the existing
update_cc_test_checks lines. This just moves them later so as to not
mess up the existing ordering when the checks are regenerated.
2021-11-13 19:09:01 +00:00
Saleem Abdulrasool c17d9b4b12 headers: optionalise some generated resource headers
This splits out the generated headers and conditonalises them upon the
target being enabled.

The motivation here is that the RISCV header alone added 10MB to the
resource directory, which was previously at 10MB, increasing the build
size and time. This header is contributing ~50% of the size of the
resource headers (~10MB).

The ARM generated headers are contributing about ~10% or 1MB.

This could be extended further adding only the static resource headers
for the targets that the LLVM build supports.

The changes to the tests for ARM mirror what the RISCV target already
did and rnk identified as a possible issue.

Testing:
  cmake -G Ninja -D LLVM_TARGETS_TO_BUILD=X86 -D LLVM_ENABLE_PROJECTS="clang;lld" ../clang
  ninja check-clang

Differential Revision: https://reviews.llvm.org/D112890
Reviewed By: craig.topper
2021-11-09 22:30:29 +00:00
Irina Dobrescu 50511df32e [AArch64] Lower bitreverse in ISel
Adding lowering support for bitreverse.

Previously, lowering bitreverse would expand it into a series of other instructions. This patch makes it so this produces a single rbit instruction instead.

Reviewed By: dmgreen

Differential Revision: https://reviews.llvm.org/D102397
2021-05-17 13:35:27 +01:00
Bradley Smith cf0da91ba5 [AArch64][SVE/NEON] Add support for FROUNDEVEN for both NEON and fixed length SVE
Previously NEON used a target specific intrinsic for frintn, given that
the FROUNDEVEN ISD node now exists, move over to that instead and add
codegen support for that node for both NEON and fixed length SVE.

Differential Revision: https://reviews.llvm.org/D98487
2021-03-17 11:41:22 +00:00
JinGu Kang 394a4d0433 [AArch64] Add missing intrinsics for vcls
Differential Revision: https://reviews.llvm.org/D97775
2021-03-03 10:17:56 +00:00
Joe Ellis 5a2a8369e8 [AArch64][NEON] Remove undocumented vceqz{,q}_p16, vml{a,s}q_n_f64 intrinsics
Prior to this patch, Clang supported the following C/C++ intrinsics:

    vceqz_p16
    vceqzq_p16
    vmlaq_n_f64
    vmlsq_n_f64

... exposed through arm_neon.h. However, these intrinsics are not part
of the ACLE, allowing developers to write code that is not compatible
with other toolchains.

This patch removes these intrinsics.

There is a bug report capturing this issue here:

    https://bugs.llvm.org/show_bug.cgi?id=47471

Reviewed By: bsmith

Differential Revision: https://reviews.llvm.org/D93206
2020-12-15 17:19:16 +00:00
David Spickett 349af80542 [clang][AArch64] Correct return type of Neon vqmovun intrinsics
Neon intrinsics vqmovunh_s16, vqmovuns_s32, vqmovund_s64
should have unsigned return types.

See https://developer.arm.com/architectures/instruction-sets/simd-isas/neon/intrinsics?search=vqmovun

Fixes https://bugs.llvm.org/show_bug.cgi?id=46840

Reviewed By: efriedma

Differential Revision: https://reviews.llvm.org/D85118
2020-09-21 09:21:51 +01:00
Eli Friedman 8dfb5d767e [clang codegen][AArch64] Use llvm.aarch64.neon.fcvtzs/u where it's necessary
fptosi/fptoui have similar, but not identical, semantics.  In
particular, the behavior on overflow is different.

Fixes https://bugs.llvm.org/show_bug.cgi?id=46844 for 64-bit.  (The
corresponding patch for 32-bit is more involved because the equivalent
intrinsics don't exist, as far as I can tell.)

Differential Revision: https://reviews.llvm.org/D84703
2020-07-30 15:41:54 -07:00
Cameron McInally 20b8ed2c2b [IRBuilder] Update IRBuilder::CreateFNeg(...) to return a UnaryOperator
Reapply r374240 with fix for Ocaml test, namely Bindings/OCaml/core.ml.

Differential Revision: https://reviews.llvm.org/D61675

llvm-svn: 374782
2019-10-14 15:35:01 +00:00
Dmitri Gribenko eaf6dd482b Revert "[IRBuilder] Update IRBuilder::CreateFNeg(...) to return a UnaryOperator"
This reverts commit r374240. It broke OCaml tests:
http://lab.llvm.org:8011/builders/clang-x86_64-debian-fast/builds/19014

llvm-svn: 374354
2019-10-10 14:13:54 +00:00
Cameron McInally 47363a148f [IRBuilder] Update IRBuilder::CreateFNeg(...) to return a UnaryOperator
Also update Clang to call Builder.CreateFNeg(...) for UnaryMinus.

Differential Revision: https://reviews.llvm.org/D61675

llvm-svn: 374240
2019-10-09 21:52:15 +00:00
Ivan A. Kosarev 8264bb8d34 [NEON] Fix support for vrndi_f32(), vrndiq_f32() and vrndns_f32() intrinsics
This patch adds support for vrndi_f32() and vrndiq_f32()
intrinsics in AArch32 mode and for vrndns_f32() intrinsic in
AArch64 mode.

Differential Revision: https://reviews.llvm.org/D48829

llvm-svn: 337690
2018-07-23 13:26:37 +00:00
Mehdi Amini 6aa9e9b41a IRGen: Add optnone attribute on function during O0
Amongst other, this will help LTO to correctly handle/honor files
compiled with O0, helping debugging failures.
It also seems in line with how we handle other options, like how
-fnoinline adds the appropriate attribute as well.

Differential Revision: https://reviews.llvm.org/D28404

llvm-svn: 304127
2017-05-29 05:38:20 +00:00
Matt Arsenault 7c4c1cb2f5 Fix tests after speculatable intrinsics patch
These were relying on the attribute group numbering

llvm-svn: 301996
2017-05-03 03:04:40 +00:00
David Majnemer 12b9e76b62 Update for LLVM changes
InstSimplify has gained the ability to remove needless bitcasts which
perturbed some clang codegen tests.

llvm-svn: 276728
2016-07-26 05:52:37 +00:00
Tim Northover 58672974a9 ARM & AArch64: convert asm tests to LLVM IR and restrict optimizations.
This is mostly a one-time autoconversion of tests that checked assembly after
"-Owhatever" compiles to only run "opt -mem2reg" and check the assembly. This
should make them much more stable to changes in LLVM so they won't break on
unrelated changes.

"opt -mem2reg" is a compromise designed to increase the readability of tests
that check dataflow, while minimizing dependency on LLVM. Hopefully mem2reg is
stable enough that no surpises will come along.

Should address http://llvm.org/PR26815.

llvm-svn: 263048
2016-03-09 18:54:42 +00:00
Tim Northover 831d728f9a AArch64: re-enable tests that were looking for a non-existent backend.
In the final phase of the merge, I managed to disable a bunch of Clang
tests accidentally. Fortunately none of them seem to have broken in
the interim.

llvm-svn: 211149
2014-06-18 08:37:28 +00:00
Tim Northover 25e8a6754e AArch64/ARM64: update Clang after AArch64 removal.
A few (mostly CodeGen) parts of Clang were tightly coupled to the
AArch64 backend. Now that it's gone, they will not even compile.

I've also deduplicated RUN lines in many of the AArch64 tests. This
might improve "make check-all" time noticably: some of those NEON
tests were monsters.

llvm-svn: 209578
2014-05-24 12:51:25 +00:00
Tim Northover fb33438115 ARM64: update tests now that we print "mov" & "mvn".
llvm-svn: 208875
2014-05-15 12:11:10 +00:00
James Molloy 75f5f9e629 [ARM64] Allow the disabling of NEON and crypto instructions. Update tests to pass -target-feature +neon.
llvm-svn: 206394
2014-04-16 15:33:48 +00:00
Tim Northover a2ee433c8d ARM64: initial clang support commit.
This adds Clang support for the ARM64 backend. There are definitely
still some rough edges, so please bring up any issues you see with
this patch.

As with the LLVM commit though, we think it'll be more useful for
merging with AArch64 from within the tree.

llvm-svn: 205100
2014-03-29 15:09:45 +00:00
Tim Northover 926a235fea AArch64: convert NEON tests to use CHECK-LABEL.
llvm-svn: 202703
2014-03-03 11:34:36 +00:00
Hao Liu f96fd37888 [AArch64]The compare to zero intrinsics should be implemented by 'icmp/fcmp' and 'sext' not 'zext'. Modify the implementation by replacing zext with sext.
llvm-svn: 197898
2013-12-23 02:44:00 +00:00
Chad Rosier 75df5680fe [AArch64] Fix v1fx patterns for Floating-point Multiply Extend and Floating-point Compare to Zero.
llvm-svn: 197403
2013-12-16 18:29:54 +00:00
Kevin Qin ad53b87c70 [AArch64 NEON] Add ACLE intrinsic vceqz_f64.
llvm-svn: 196361
2013-12-04 08:02:11 +00:00
Kevin Qin 8903f8df4b [AArch64 NEON] Add missing compare intrinsics.
llvm-svn: 196359
2013-12-04 07:53:09 +00:00
Kevin Qin 9e255dd532 Add test cases for AArch64 NEON instruction set misc.
llvm-svn: 194672
2013-11-14 06:44:42 +00:00