llvm-project

Commit Graph

Author	SHA1	Message	Date
Stefan Pintilie	cc330daa5b	[PowerPC] Add missing record form instructions to the P9 Scheduling Model A number of record form instructions were missing from the P9 scheduling model. Added those instructions and marked the P9 model as complete. Differential Revision: https://reviews.llvm.org/D38560 llvm-svn: 315313	2017-10-10 13:45:35 +00:00
Stefan Pintilie	e1d7547237	[PowerPC] Revert P9 scheduling model to incomplete Partially revert a previous change from commit: https://llvm.org/svn/llvm-project/llvm/trunk@314026 The previous change caused regressions on Power 9. llvm-svn: 314835	2017-10-03 20:27:30 +00:00
Stefan Pintilie	590eb2755d	[PowerPC] Mark P9 scheduling model complete This patch just adds the missing information to the P9 scheduling model to allow the model to be marked as complete. The model has been verified against P9 documentation. The model was verified with utils/schedcover.py. Differential Revision: https://reviews.llvm.org/D35695 llvm-svn: 314026	2017-09-22 20:17:25 +00:00
Hiroshi Inoue	4ba87d01bc	fix formatting; NFC llvm-svn: 307662	2017-07-11 15:41:31 +00:00
Hiroshi Inoue	df6a0fb8a7	[PowerPC] fix latency for simple integer instructions in POWER9 scheduler In the POWER9 instruction scheduler, SchedWriteRes for the simple integer instructions are misconfigured to use that of (costly) DFU instructions. This results in surprisingly long instruction latency estimation and causes misbehavior in some optimizers such as if-conversion. Differential Revision: https://reviews.llvm.org/D34869 llvm-svn: 307624	2017-07-11 05:37:16 +00:00
Ehsan Amiri	6c17bb0eb7	[Power9] Processor Model for Scheduling PWR9 processor model for instruction scheduling. A subsequent patch will migrate PWR9 to Post RA MIScheduler. https://reviews.llvm.org/D24525 llvm-svn: 290102	2016-12-19 13:35:45 +00:00

6 Commits