Commit Graph

22843 Commits

Author SHA1 Message Date
Krzysztof Parzyszek f9d01a12d1 [Hexagon] Add patterns for truncating HVX vector types
Only non-bool vectors.

llvm-svn: 321895
2018-01-05 20:48:03 +00:00
Krzysztof Parzyszek 9d0c6355a0 [Hexagon] Add patterns for sext_inreg of HVX vector types
llvm-svn: 321894
2018-01-05 20:46:41 +00:00
Krzysztof Parzyszek 0f5d976aa0 [Hexagon] Add a bitcast to required type in LowerHvxMul
llvm-svn: 321893
2018-01-05 20:45:34 +00:00
Krzysztof Parzyszek 66ee123d61 [Hexagon] Add pattern for vsplat to v8i8
llvm-svn: 321892
2018-01-05 20:43:56 +00:00
Simon Pilgrim 15fcbe2d4a [X86] Regenerate illegal move test
Recommitting after fixing case-sensitive issue in the RUN command

llvm-svn: 321868
2018-01-05 14:24:03 +00:00
Florian Hahn e970d64ec5 [AArch64] Fix -mcpu option in aarch64-combine-fmul-fsub.mir (NFC)
llvm-svn: 321865
2018-01-05 11:17:48 +00:00
Sam Parker 1ad085b808 [DAGCombine] Fix for PR37563
While searching for loads to be narrowed, equal sized loads were not
added to the list, resulting in anyext loads not being converted to
zext loads.

https://bugs.llvm.org/show_bug.cgi?id=35763

Differential Revision: https://reviews.llvm.org/D41628

llvm-svn: 321862
2018-01-05 08:47:23 +00:00
Aditya Nandakumar 5710c44eee [GISel]: Don't create G_MUL with 1 during translation of GEP
When element size is 1, it's just wasteful to create MUL with 1.
https://reviews.llvm.org/D41738

llvm-svn: 321857
2018-01-05 02:56:28 +00:00
Simon Pilgrim ab84a9a65d [X86] Add srem/udiv/urem by one combine tests
llvm-svn: 321826
2018-01-04 22:08:36 +00:00
Evandro Menezes 6161a0b3b0 [AArch64] Improve code generation of vector build
Instead of using, for example, `dup v0.4s, wzr`, which transfers between
register files, use the more efficient `movi v0.4s, #0` instead.

Differential revision: https://reviews.llvm.org/D41515

llvm-svn: 321824
2018-01-04 21:43:12 +00:00
Simon Pilgrim e7c06423c1 [X86] Add scalar undef sdiv/srem/udiv/urem combine tests
llvm-svn: 321823
2018-01-04 21:33:19 +00:00
Alexey Bataev 7212b6e4b9 [DEBUG] Add initial tests for debug info for NVPTX target, NFC.
llvm-svn: 321822
2018-01-04 21:07:07 +00:00
Craig Topper dffb98e03d [X86] Correct the execution domain for AVX1 VBROADCASTF128 to be FP instead of integer.
llvm-svn: 321821
2018-01-04 20:56:21 +00:00
Amara Emerson 83e852f30d Revert "[X86] Regenerate test"
This reverts r321814 as it was failing make check.

llvm-svn: 321819
2018-01-04 20:20:44 +00:00
Simon Pilgrim a47289a2ee [X86] Regenerate test
llvm-svn: 321814
2018-01-04 18:48:42 +00:00
Simon Pilgrim 208fab193b [X86] Add common CHECK prefix for tests without SSE/AVX codegen
llvm-svn: 321810
2018-01-04 18:23:46 +00:00
Simon Pilgrim d6923083ba Regenerate broadcast constant comment
llvm-svn: 321808
2018-01-04 18:21:33 +00:00
Simon Pilgrim 5643b40d91 [X86] Show missed combine for X/X for SDIV/UDIV and X%X for SREM/UREM
llvm-svn: 321807
2018-01-04 18:20:46 +00:00
Diana Picus 865f7fecb2 [ARM GlobalISel] Select G_PHI
Select G_PHI to PHI and manually constrain the result register. This is
very similar to how COPY is handled, so extract and reuse some of that
code.

llvm-svn: 321797
2018-01-04 13:09:25 +00:00
Diana Picus bcabda43e4 [ARM GlobalISel] Add RegBankSelect tests for G_PHI
RegBankSelect already handles G_PHI with some generic code. Add a couple
of tests for it.

llvm-svn: 321796
2018-01-04 13:09:20 +00:00
Diana Picus c768bbe2e7 [ARM GlobalISel] Legalize scalar G_PHI
Mark G_PHI as Legal for s32 and p0, and also for s64 if we have hard
float. Widen any smaller types.

llvm-svn: 321795
2018-01-04 13:09:14 +00:00
Diana Picus 37ae9f68a4 [ARM GlobalISel] Fix selection of pointer constants
We used to handle G_CONSTANT with pointer type by forcing the type of
the result register to s32 and then letting TableGen handle it.
Unfortunately, setting the type only works for generic virtual
registers, that haven't yet been constrained to a register class (e.g.
those used only by a COPY later on). If the result register has already
been constrained as a use of a previously selected instruction, then
setting the type will assert.

It would be nice to be able to teach TableGen to select pointer
constants the same as integer constants, but since it's such an edge
case (at the moment the only pointer constant that we're generally
interested in is 0, and that is mostly used for comparisons and selects,
which are also not supported by TableGen) it's probably not worth the
effort right now. Instead, handle pointer constants with some trivial
handwritten code.

llvm-svn: 321793
2018-01-04 10:54:57 +00:00
Sam Parker 4e70c2fac8 [X86] Codegen test for PR37563
Adding test to ease review of D41628.

llvm-svn: 321791
2018-01-04 09:42:27 +00:00
Simon Pilgrim ec0a2fb703 [DAGCombine] Handle out of range EXTRACT_VECTOR_ELT indices
Handle this in DAGCombiner::visitEXTRACT_VECTOR_ELT the same as we already do in SelectionDAG::getNode and use APInt instead of getZExtValue.

This should also fix oss-fuzz #4910

llvm-svn: 321767
2018-01-03 22:42:33 +00:00
Matt Arsenault 8070882b4e StructurizeCFG: Fix broken backedge detection
The work order was changed in r228186 from SCC order
to RPO with an arbitrary sorting function. The sorting
function attempted to move inner loop nodes earlier. This
was was apparently relying on an assumption that every block
in a given loop / the same loop depth would be seen before
visiting another loop. In the broken testcase, a block
outside of the loop was encountered before moving onto
another block in the same loop. The testcase would then
structurize such that one blocks unconditional successor
could never be reached.

Revert to plain RPO for the analysis phase. This fixes
detecting edges as backedges that aren't really.

The processing phase does use another visited set, and
I'm unclear on whether the order there is as important.
An arbitrary order doesn't work, and triggers some infinite
loops. The reversed RPO list seems to work and is closer
to the order that was used before, minus the arbitary
custom sorting.

A few of the changed tests now produce smaller code,
and a few are slightly worse looking.

llvm-svn: 321751
2018-01-03 18:45:37 +00:00
Craig Topper cc6637b707 [X86] Use ANY_EXTEND instead of SIGN_EXTEND in lowerMasksToReg
Currently we use SIGN_EXTEND in lowerMasksToReg as part of calling convention setup, but we don't require a specific value for the upper bits.

This patch changes it to ANY_EXTEND which will be lowered as SIGN_EXTEND if it ends up sticking around.

llvm-svn: 321746
2018-01-03 18:11:01 +00:00
Amara Emerson 9de62130fd [GlobalISel][Legalizer] Fix legalization of llvm.smul.with.overflow
Previously the code for handling G_SMULO didn't properly check for the signed
multiply overflow, instead treating it the same as the unsigned G_UMULO.

Fixes PR35800.

llvm-svn: 321690
2018-01-03 04:56:56 +00:00
Andrew Kaylor e12e08c680 Handle the case of live 16-bit subregisters in X86FixupBWInsts
Differential Revision: https://reviews.llvm.org/D40524

Change-Id: Ie3a405b28503ceae999f5f3ba07a68fa733a2400
llvm-svn: 321674
2018-01-02 21:04:38 +00:00
Sanjay Patel 24e6a8bde0 [AArch64] fix typos in comments; NFC
llvm-svn: 321673
2018-01-02 21:04:08 +00:00
Sanjay Patel 7811430588 [ValueTracking] recognize min/max of min/max patterns
This is part of solving PR35717:
https://bugs.llvm.org/show_bug.cgi?id=35717

The larger IR optimization is proposed in D41603, but we can show 
the improvement in ValueTracking using codegen tests because 
SelectionDAG creates min/max nodes based on ValueTracking. 

Any target with min/max ops should show wins here. I chose AArch64
vector ops because they're clean and uniform.

Some Alive proofs for the tests (can't put more than 2 tests in 1 
page currently because the web app says it's too long):
https://rise4fun.com/Alive/WRN
https://rise4fun.com/Alive/iPm
https://rise4fun.com/Alive/HmY
https://rise4fun.com/Alive/CNm
https://rise4fun.com/Alive/LYf

llvm-svn: 321672
2018-01-02 20:56:45 +00:00
Sanjay Patel 35a6ee86af [AArch64] add tests for min/max of min/max (PR35717); NFC
llvm-svn: 321668
2018-01-02 20:16:45 +00:00
Amara Emerson 913918cbef [AArch64][GlobalISel] Fix assert fail with unknown intrinsic.
A call may have an intrinsic name but not have a valid intrinsic ID,
for example with llvm.invariant.group.barrier. If so, treat it as a
normal call like FastISel does.

llvm-svn: 321662
2018-01-02 18:56:39 +00:00
Sanjay Patel 9a80871ffe [x86] allow pairs of PCMPEQ for vector-sized integer equality comparisons (PR33325)
This is an extension of D31156 with the goal that we'll allow memcmp() == 0 expansion 
for x86 to use 2 pairs of loads per block.

The memcmp expansion pass (formerly part of CGP) will generate this kind of pattern 
with oversized integer compares, so we want to transform these into x86-specific vector
nodes before legalization splits things into scalar chunks.

See PR33325 for more details:
https://bugs.llvm.org/show_bug.cgi?id=33325

Differential Revision: https://reviews.llvm.org/D41618

llvm-svn: 321656
2018-01-02 16:38:29 +00:00
Amara Emerson 854d10d10b [AArch64][GlobalISel] Enable GlobalISel at -O0 by default
Tests updated to explicitly use fast-isel at -O0 instead of implicitly.

This change also allows an explicit -fast-isel option to override an
implicitly enabled global-isel. Otherwise -fast-isel would have no effect at -O0.

Differential Revision: https://reviews.llvm.org/D41362

llvm-svn: 321655
2018-01-02 16:30:47 +00:00
Krzysztof Parzyszek cfe4a3616f [Hexagon] Fix generation of vector sign extensions
llvm-svn: 321650
2018-01-02 15:28:49 +00:00
Daniel Jasper cc4903e2ba Revert r321089: "[DAG] Elide overlapping store" (and subsequent fix in r321204)
Our internal testing has revealed has discovered bugs in PPC builds.
I have forward reproduction instructions to the original author (Nirav).

llvm-svn: 321649
2018-01-02 14:38:52 +00:00
Sam Parker 3570c554b5 [DAGCombine] Fix for PR35765
Remove the acceptance of ANY_EXTEND nodes while trying to move and
nodes back to loads.

Bugzilla: https://bugs.llvm.org/show_bug.cgi?id=35765

Differential Revision: https://reviews.llvm.org/D41625

llvm-svn: 321641
2018-01-02 10:19:01 +00:00
Sam Parker 2dea5e0f3c [X86] Codegen test for pr35765
Committing reproducer test for pr35765, fix to follow.

llvm-svn: 321640
2018-01-02 10:14:00 +00:00
Craig Topper e3b6bd337a [SelectionDAG] Teach WidenVecOp_Convert to widen the operation if a widened result type would still be legal.
llvm-svn: 321638
2018-01-02 07:30:53 +00:00
Craig Topper c8898b3640 [X86] Promote vXi1 fp_to_uint/fp_to_sint to vXi32 to avoid scalarization.
llvm-svn: 321632
2018-01-01 21:12:18 +00:00
Craig Topper bb8b79b0a0 [X86] Add test cases for vXi1 fptosi/fptoui.
Currently we do a lot of scalarization in these test cases.

llvm-svn: 321631
2018-01-01 21:12:10 +00:00
Sanjay Patel 18962dabb7 [x86] add runs for more vector variants; NFC
Preliminary step to see what the effects of D41618 look like.

llvm-svn: 321624
2018-01-01 16:36:47 +00:00
Simon Pilgrim e337268df7 [X86][SSE] Add test case from PR32160
llvm-svn: 321620
2018-01-01 13:04:04 +00:00
Uriel Korach c06596ced4 [X86] Regenerate test checks in sse-intrinsics-x86-upgrade with update-llc
Removing outdated checks.
NFC

llvm-svn: 321619
2018-01-01 09:00:13 +00:00
Uriel Korach e87d240699 [X86] Regenerate test checks in sse2-intrinsics-x86-upgrade with update-llc
Removing outdated checks.
NFC

llvm-svn: 321618
2018-01-01 08:47:50 +00:00
Craig Topper 0d35edda90 [X86] In LowerTruncateVecI1, don't add SHL if the input is known to be all sign bits.
If the input is all sign bits then the LSB through MSB are all the same so we don't need to be move the LSB to the MSB.

llvm-svn: 321617
2018-01-01 04:52:58 +00:00
Craig Topper fc3ce4993c [X86] Add patterns for using zmm registers for v8i32/v8f32 vselect with the false input being zero.
We can use zmm move with zero masking for this. We already had patterns for using a masked move, but we didn't check for the zero masking case separately.

llvm-svn: 321612
2018-01-01 01:11:29 +00:00
Craig Topper f78b75fb59 [X86] Use CONCAT_VECTORS instead of INSERT_SUBVECTOR for padding v4i1/v2i1 vector to v8i1 pre-legalize.
The CONCAT_VECTORS will be lowered to INSERT_SUBVECTOR later. In the modified cases this seems to be enough to trick a later DAG combine into running in a different order than allows the ANDs to be removed.

I'll admit this is a bit of a hack that happens to work, but using CONCAT_VECTORS is more consistent with other legalization code anyway.

llvm-svn: 321611
2017-12-31 19:17:52 +00:00
Simon Pilgrim b000675374 [X86][AVX2] Combine extract(broadcast(scalar_value)) --> scalar_value
As it has a scalar source we don't treat it as a target shuffle so needs special handling.

llvm-svn: 321610
2017-12-31 18:59:30 +00:00
Simon Pilgrim e940b86c5f [X86][AVX] Add test case from PR33740
llvm-svn: 321608
2017-12-31 17:16:48 +00:00