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502 Commits

Author SHA1 Message Date
Akira Hatanaka b9ebf8d644 Define Mips specific unaligned load/store nodes. 
llvm-svn: 157863
 2012-06-02 00:03:12 +00:00
Akira Hatanaka 4e76bf8282 Expand unaligned i16 loads/stores for the Mips backend. 
This is the first of a series of patches which make changes to the backend to
emit unaligned load/store instructions (lwl,lwr,swl,swr) during instruction
selection.

llvm-svn: 157862
 2012-06-02 00:02:45 +00:00
Akira Hatanaka bff8e31d3c Cleanup and factoring of mips16 tablegen classes. Make register classes 
CPU16RegsRegClass and CPURARegRegClass available. Add definition of mips16
jalr instruction.

Patch by Reed Kotler.

llvm-svn: 157730
 2012-05-31 02:59:44 +00:00
Justin Holewinski aa58397b3c Change interface for TargetLowering::LowerCallTo and TargetLowering::LowerCall 
to pass around a struct instead of a large set of individual values.  This
cleans up the interface and allows more information to be added to the struct
for future targets without requiring changes to each and every target.

NV_CONTRIB

llvm-svn: 157479
 2012-05-25 16:35:28 +00:00
Akira Hatanaka f542ebd958 Make the following changes in MipsISelLowering.cpp: 
- Stop creating stack frame objects needed for saving $gp.
- Insert a node that copies the global pointer register to register $gp
  before the call node. This will ensure $gp is valid at the entry of the
  called function.

llvm-svn: 156692
 2012-05-12 03:19:04 +00:00
Akira Hatanaka 0a8ab718cb Expand 64-bit shifts if target ABI is O32. 
llvm-svn: 156457
 2012-05-09 00:55:21 +00:00
Eric Christopher 0d8c15d20f Add support for the 'x' constraint. 
Patch by Jack Carter.

llvm-svn: 156295
 2012-05-07 06:25:19 +00:00
Eric Christopher 9c492e6ebf Add support for the 'l' constraint. 
Patch by Jack Carter.

llvm-svn: 156294
 2012-05-07 06:25:15 +00:00
Eric Christopher e3c494de82 Add support for the 'c' constraint. 
Patch by Jack Carter.

llvm-svn: 156293
 2012-05-07 06:25:10 +00:00
Eric Christopher c18ae4a3b1 Add support for the 'P' constraint. 
Patch by Jack Carter.

llvm-svn: 156292
 2012-05-07 06:25:02 +00:00
Eric Christopher 470578a91b Add support for the 'O' constraint. 
Patch by Jack Carter.

llvm-svn: 156285
 2012-05-07 05:46:48 +00:00
Eric Christopher e07aa430b8 Add support for the 'N' inline asm constraint. 
Patch by Jack Carter.

llvm-svn: 156284
 2012-05-07 05:46:43 +00:00
Eric Christopher 1109b3406d Add support for the 'L' inline asm constraint. 
Patch by Jack Carter.

llvm-svn: 156283
 2012-05-07 05:46:37 +00:00
Eric Christopher 3ff88a05b7 Add support for the inline asm constraint 'K'. 
llvm-svn: 156282
 2012-05-07 05:46:29 +00:00
Eric Christopher 7201e1b4b9 Support the 'J' constraint. 
Patch by Jack Carter.

llvm-svn: 156280
 2012-05-07 03:13:42 +00:00
Eric Christopher 1d6c89eea1 Add support for the 'I' inline asm constraint. Also add tests 
from the previous 2 patches.

Patch by Jack Carter.

llvm-svn: 156279
 2012-05-07 03:13:32 +00:00
Eric Christopher 58daf04681 Allow 64 bit integer values in gpu registers if arch and abi are 64 bit. 
Patch by Jack Carter.

llvm-svn: 156278
 2012-05-07 03:13:22 +00:00
Eric Christopher cfcd77b0bc When using inline asm constraints representing 
non-floating point general registers allow 8 and 16-bit
elements.

Patch by Jack Carter.

llvm-svn: 156277
 2012-05-07 03:13:16 +00:00
Hans Wennborg aea412008e Make ARM and Mips use TargetMachine::getTLSModel() 
This moves the logic for selecting a TLS model to a single place,
instead of the previous three (ARM, Mips, and X86 which already
uses this function).

llvm-svn: 156162
 2012-05-04 09:40:39 +00:00
NAKAMURA Takumi e30303fa86 llvm/lib/Target: [PR12611] Add "llvm/Support/raw_ostream.h" for Debug build on MSVC. 
Thanks to Andy Gibbs, to report the issue.

llvm-svn: 155287
 2012-04-21 15:31:45 +00:00
Craig Topper c7242e054d Convert more uses of XXXRegisterClass to &XXXRegClass. No functional change since they are equivalent. 
llvm-svn: 155188
 2012-04-20 07:30:17 +00:00
Akira Hatanaka 47ad674f67 Emit neg.s or neg.d only if -enable-no-nans-fp-math is supplied by user, 
otherwise expand FNEG during legalization.

llvm-svn: 154546
 2012-04-11 22:59:08 +00:00
Akira Hatanaka 7f4c9d1429 Emit abs.s or abs.d only if -enable-no-nans-fp-math is supplied by user. 
Invalid operation is signaled if the operand of these instructions is NaN.

llvm-svn: 154545
 2012-04-11 22:49:04 +00:00
Akira Hatanaka 4f5c8421b3 Fix bugs in lowering of FCOPYSIGN nodes. 
- FCOPYSIGN nodes that have operands of different types were not handled.
- Different code was generated depending on the endianness of the target.

Additionally, code is added that emits INS and EXT instructions, if they are
supported by target (they are R2 instructions).

llvm-svn: 154540
 2012-04-11 22:13:04 +00:00
Akira Hatanaka 121342fcc2 Reapply 154038 without the failing test. 
llvm-svn: 154062
 2012-04-04 22:16:36 +00:00
Owen Anderson 4743c6e159 Revert r154038. It was causing make check failures. 
llvm-svn: 154054
 2012-04-04 21:18:58 +00:00
Akira Hatanaka 9705c865d9 Fix LowerGlobalAddress to produce instructions with the correct relocation 
types for N32 ABI. Add new test case and update existing ones.

llvm-svn: 154038
 2012-04-04 19:02:38 +00:00
Akira Hatanaka 591ecdd7c1 Fix LowerJumpTable to produce instructions with the correct relocation 
types for N32 ABI. Test case will be updated after the patch that fixes
TargetLowering::getPICJumpTableRelocBase is checked in.

llvm-svn: 154036
 2012-04-04 18:31:32 +00:00
Akira Hatanaka b3a2b8c199 Fix LowerConstantPool to produce instructions with the correct relocation 
types for N32 ABI and update test case.

llvm-svn: 154034
 2012-04-04 18:26:12 +00:00
Akira Hatanaka aeff24e424 Fix LowerBlockAddress to produce instructions with the correct relocation 
types for N32 ABI and update test case.

llvm-svn: 154031
 2012-04-04 18:22:53 +00:00
Akira Hatanaka 0603ad8c65 Expand FREM. 
llvm-svn: 153671
 2012-03-29 18:43:11 +00:00
Akira Hatanaka 8a7633c74e Pass the llvm IR pointer value and offset to the constructor of 
MachinePointerInfo when getStore is called to create a node that stores an
argument passed in register to the stack. Without this change, the post RA 
scheduler will fail to discover the dependencies between the stores
instructions and the instructions that load from a structure passed by value. 

The link to the related discussion is here:
http://lists.cs.uiuc.edu/pipermail/llvmdev/2012-March/048055.html

llvm-svn: 153499
 2012-03-27 03:13:56 +00:00
Akira Hatanaka 769f69f9b6 Fix bug in LowerConstantPool. 
llvm-svn: 153498
 2012-03-27 02:55:31 +00:00
Craig Topper b25fda95f6 Reorder includes in Target backends to following coding standards. Remove some superfluous forward declarations. 
llvm-svn: 152997
 2012-03-17 18:46:09 +00:00
Craig Topper bef78fc2ee Convert more static tables of registers used by calling convention to uint16_t to reduce space. 
llvm-svn: 152538
 2012-03-11 07:57:25 +00:00
Akira Hatanaka da00aa80b6 Do not custom lower i64 nodes if i64 is not a legal type. Move lines that set 
operation action of nodes.

llvm-svn: 152452
 2012-03-10 00:03:50 +00:00
Akira Hatanaka b7f78592e2 Lower SETCC nodes during legalization. Previously, it was lowered in DAG combine pass. 
llvm-svn: 152450
 2012-03-09 23:46:03 +00:00
Akira Hatanaka 5e152182a4 Invoke setTargetDAGCombine for SELECT. 
llvm-svn: 152290
 2012-03-08 03:26:37 +00:00
Akira Hatanaka 7dd7c08419 Swap the operands of a select node if the false (the second) operand is 0. 
For example, this pattern 
(select (setcc lhs, rhs, cc), true, 0)
is transformed to this one:
(select (setcc lhs, rhs, inverse(cc)), 0, true)

This enables MipsDAGToDAGISel::ReplaceUsesWithZeroReg (added in r152280) to
replace 0 with $zero.

llvm-svn: 152285
 2012-03-08 02:14:24 +00:00
Akira Hatanaka 956dd2261e Set minimum function alignment to 3 if target is Mips64. 
llvm-svn: 152282
 2012-03-08 01:59:33 +00:00
Akira Hatanaka 5350c24509 Changes for migrating to using register mask operands. 
llvm-svn: 151847
 2012-03-01 22:27:29 +00:00
Akira Hatanaka 6bbe1f0d10 Fix bugs which were introduced when support for base+index floating point loads 
and stores was added.

- SelectAddr should return false if Parent is an unaligned f32 load or store.
- Only aligned load and store nodes should be matched to select reg+imm
  floating point instructions.
- MIPS does not have support for f64 unaligned load or store instructions.

llvm-svn: 151843
 2012-03-01 22:12:30 +00:00
Evan Cheng 65f9d19c4f Re-commit r151623 with fix. Only issue special no-return calls if it's a direct call. 
llvm-svn: 151645
 2012-02-28 18:51:51 +00:00
Daniel Dunbar ee7b899343 Revert r151623 "Some ARM implementaions, e.g. A-series, does return stack prediction. ...", it is breaking the Clang build during the Compiler-RT part. 
llvm-svn: 151630
 2012-02-28 15:36:07 +00:00
Jia Liu f54f60f3ce remove blanks, and some code format 
llvm-svn: 151625
 2012-02-28 07:46:26 +00:00
Evan Cheng 87c7b09d8d Some ARM implementaions, e.g. A-series, does return stack prediction. That is, 
the processor keeps a return addresses stack (RAS) which stores the address
and the instruction execution state of the instruction after a function-call
type branch instruction.

Calling a "noreturn" function with normal call instructions (e.g. bl) can
corrupt RAS and causes 100% return misprediction so LLVM should use a
unconditional branch instead. i.e.
mov lr, pc
b _foo
The "mov lr, pc" is issued in order to get proper backtrace.

rdar://8979299

llvm-svn: 151623
 2012-02-28 06:42:03 +00:00
Akira Hatanaka 330d901ce3 Add support for floating point base register + offset register addressing mode 
load and store instructions.

llvm-svn: 151611
 2012-02-28 02:55:02 +00:00
Akira Hatanaka b049aef2d1 Add an option to use a virtual register as the global base register instead of 
reserving a physical register ($gp or $28) for that purpose.

This will completely eliminate loads that restore the value of $gp after every
function call, if the register allocator assigns a callee-saved register, or
eliminate unnecessary loads if it assigns a temporary register. 

example:

.cpload $25       // set $gp.
...
.cprestore 16     // store $gp to stack slot 16($sp).
...
jalr $25          // function call. clobbers $gp.
lw $gp, 16($sp)   // not emitted if callee-saved reg is chosen.
...
lw $2, 4($gp)
...
jalr $25          // function call.
lw $gp, 16($sp)   // not emitted if $gp is not live after this instruction.
...

llvm-svn: 151402
 2012-02-24 22:34:47 +00:00
Craig Topper 760b134ffa Make all pointers to TargetRegisterClass const since they are all pointers to static data that should not be modified. 
llvm-svn: 151134
 2012-02-22 05:59:10 +00:00
Jia Liu 9f6101191b remove Emacs-tag form .cpp files in Mips Backend, and fix some typo. 
llvm-svn: 150805
 2012-02-17 08:55:11 +00:00
Akira Hatanaka d608bac682 Do not promote i32 arguments to i64. This was causing unnecessary sign extension 
instructions to be emitted.

llvm-svn: 150782
 2012-02-17 02:20:26 +00:00
Jia Liu dd6c1cd4e8 add Emacs tag and fix some comment error in file headers 
llvm-svn: 150775
 2012-02-17 01:23:50 +00:00
Craig Topper e55c556a24 Convert assert(0) to llvm_unreachable 
llvm-svn: 149961
 2012-02-07 02:50:20 +00:00
Akira Hatanaka f0b08445f6 Add a new MachineJumpTableInfo entry type, EK_GPRel64BlockAddress, which is 
needed to emit a 64-bit gp-relative relocation entry. Make changes necessary
for emitting jump tables which have entries with directive .gpdword. This patch
does not implement the parts needed for direct object emission or JIT.

llvm-svn: 149668
 2012-02-03 04:33:00 +00:00
Akira Hatanaka 961883c1cf Set the correct stack pointer register. 
llvm-svn: 149585
 2012-02-02 03:17:04 +00:00
Akira Hatanaka f029537e68 Expand EHSELECTION and EHSELECTION nodes. Set the correct exception pointer and 
selector registers.
 

llvm-svn: 149584
 2012-02-02 03:13:40 +00:00
Akira Hatanaka d7970f9e4b Sign-extend 32-bit integer arguments when they are passed in 64-bit registers, 
which is what N32/64 does.

llvm-svn: 148875
 2012-01-24 23:18:43 +00:00
Akira Hatanaka 7e6c195c11 Pass CCState by reference. 
llvm-svn: 148871
 2012-01-24 22:07:36 +00:00
David Blaikie 46a9f016c5 More dead code removal (using -Wunreachable-code) 
llvm-svn: 148578
 2012-01-20 21:51:11 +00:00
Akira Hatanaka aac3e06bf7 Enable -soft-float for MIPS. 
llvm-svn: 147541
 2012-01-04 19:29:11 +00:00
Akira Hatanaka c669d7a6db Have getRegForInlineAsmConstraint return the correct register class when target 
is Mips64.

llvm-svn: 147516
 2012-01-04 02:45:01 +00:00
Akira Hatanaka 1d8efaba7e Expand 64-bit CTLZ nodes if target architecture does not support it. Add test 
case for DCLO and DCLZ.

llvm-svn: 147022
 2011-12-21 00:20:27 +00:00
Akira Hatanaka 410ce9cb44 Expand 64-bit CTPOP and CTTZ. 
llvm-svn: 147021
 2011-12-21 00:14:05 +00:00
Akira Hatanaka 91c052c4d8 Expand 64-bit atomic load and store. 
llvm-svn: 147019
 2011-12-21 00:02:58 +00:00
Akira Hatanaka 4706ac9715 Add definition of DSBH (Double Swap Bytes within Halfwords) and 
DSHD (Double Swap Halfwords within Doublewords). Add a pattern which replaces
64-bit bswap with a DSBH and DSHD pair.

llvm-svn: 147017
 2011-12-20 23:56:43 +00:00
Akira Hatanaka 79aed157e7 64-bit uint-fp conversion nodes are expanded. 
llvm-svn: 147014
 2011-12-20 23:40:56 +00:00
Akira Hatanaka 2bb8d068f5 Enable custom lowering DYNAMIC_STACKALLOC nodes. 
llvm-svn: 147013
 2011-12-20 23:35:46 +00:00
Akira Hatanaka 8e2c02e2d6 Set the correct stack pointer register that should be saved or restored. 
llvm-svn: 147012
 2011-12-20 23:28:36 +00:00
Akira Hatanaka 9e1d369e3c Tidy up. Simplify logic. No functional change intended. 
llvm-svn: 146896
 2011-12-19 19:52:25 +00:00
Akira Hatanaka bff84e1914 Add support for local dynamic TLS model in LowerGlobalTLSAddress. Direct object 
emission is not supported yet, but a patch that adds the support should follow
soon.

llvm-svn: 146572
 2011-12-14 18:26:41 +00:00
Chandler Carruth 637cc6a8aa Initial CodeGen support for CTTZ/CTLZ where a zero input produces an 
undefined result. This adds new ISD nodes for the new semantics,
selecting them when the LLVM intrinsic indicates that the undef behavior
is desired. The new nodes expand trivially to the old nodes, so targets
don't actually need to do anything to support these new nodes besides
indicating that they should be expanded. I've done this for all the
operand types that I could figure out for all the targets. Owners of
various targets, please review and let me know if any of these are
incorrect.

Note that the expand behavior is *conservatively correct*, and exactly
matches LLVM's current behavior with these operations. Ideally this
patch will not change behavior in any way. For example the regtest suite
finds the exact same instruction sequences coming out of the code
generator. That's why there are no new tests here -- all of this is
being exercised by the existing test suite.

Thanks to Duncan Sands for reviewing the various bits of this patch and
helping me get the wrinkles ironed out with expanding for each target.
Also thanks to Chris for clarifying through all the discussions that
this is indeed the approach he was looking for. That said, there are
likely still rough spots. Further review much appreciated.

llvm-svn: 146466
 2011-12-13 01:56:10 +00:00
Akira Hatanaka faa88c0add Fix indentation. 
llvm-svn: 146431
 2011-12-12 22:38:19 +00:00
Benjamin Kramer 64ba50a972 Mips: Don't create a dangling IR function just to get the address of a symbol. 
llvm-svn: 146340
 2011-12-11 12:21:34 +00:00
Akira Hatanaka 5ee8464e48 Rename WrapperPIC. It is now used for both pic and static. 
llvm-svn: 146232
 2011-12-09 01:53:17 +00:00
Akira Hatanaka 8e16aac534 jalr should use t9 ($25) for indirect calls regardless of the relocation model 
specified.

llvm-svn: 146229
 2011-12-09 01:45:12 +00:00
Akira Hatanaka f10ee84956 Pass a GlobalAddress instead of an ExternalSymbol to LowerCallTo in 
MipsTargetLowering::LowerGlobalTLSAddress. This is necessary to have
call16(__tls_get_addr) emitted instead of got_disp(__tls_get_addr) when the
target is Mips64.

llvm-svn: 146183
 2011-12-08 21:05:38 +00:00
Akira Hatanaka dee6c8275c Implement 64-bit support for thread local storage handling. 
- Modify lowering of global TLS address nodes.
- Modify isel of ThreadPointer.
- Wrap target global TLS address nodes that are operands of loads with WrapperPIC. 
- Remove Mips-specific DAG nodes TlsGd, TprelHi and TprelLo, which can be
  substituted with other existing nodes.

llvm-svn: 146175
 2011-12-08 20:34:32 +00:00
Akira Hatanaka c5b5a8d8b1 Modify LowerFCOPYSIGN to handle Mips64. 
llvm-svn: 146080
 2011-12-07 21:48:50 +00:00
Bruno Cardoso Lopes 61e6d987bf Add a few moreLocal/Global R_MIPS_GOT related fixups and 
make the addend fixup code a bit more generic

Patch by Jack Carter.

llvm-svn: 145998
 2011-12-07 00:28:57 +00:00
Akira Hatanaka 20cee2eba1 Add definitions of 64-bit extract and insert instrucions and make 
PerformANDCombine and PerformOrCombine aware of them. Test cases are included
too.

llvm-svn: 145853
 2011-12-05 21:26:34 +00:00
Akira Hatanaka 34e3df76f9 Have LowerJumpTable support Mips64. Modify 2010-07-20-Switch.ll to test N64 and 
O32 with relocation-model=pic too.

llvm-svn: 145850
 2011-12-05 21:03:03 +00:00
Akira Hatanaka b31abde0f3 Lower 64-bit constant pool node. 
llvm-svn: 144849
 2011-11-16 22:44:38 +00:00
Akira Hatanaka eb42071721 Lower 64-bit block address. 
llvm-svn: 144847
 2011-11-16 22:42:10 +00:00
Akira Hatanaka 66a14c0650 Simplify function PassByValArg64. 
llvm-svn: 144664
 2011-11-15 18:42:25 +00:00
Benjamin Kramer 319904cc7e Unbreak Release builds. 
llvm-svn: 144560
 2011-11-14 19:51:48 +00:00
Akira Hatanaka 0b8bc00424 AnalyzeCallOperands function for N32/64. 
N32/64 places all variable arguments in integer registers (or on stack),
regardless of their types, but follows calling convention of non-vaarg function
when it handles fixed arguments.

llvm-svn: 144553
 2011-11-14 19:02:54 +00:00
Akira Hatanaka 52359363f2 Modify LowerFormalArguments to correctly handle vaarg arguments for Mips64. 
llvm-svn: 144552
 2011-11-14 19:01:09 +00:00
Akira Hatanaka d673cfe027 Remove variable that keeps the size of area used to save byval or variable 
argument registers on the callee's stack frame, along with functions that set
and get it.
    
It is not necessary to add the size of this area when computing stack size in
emitPrologue, since it has already been accounted for in
PEI::calculateFrameObjectOffsets.

llvm-svn: 144549
 2011-11-14 18:56:20 +00:00
Akira Hatanaka 77733535eb Fix typo. 
llvm-svn: 144453
 2011-11-12 02:38:12 +00:00
Akira Hatanaka 19891f843c Implement Mips64's handling of byval arguments in LowerCall. 
llvm-svn: 144452
 2011-11-12 02:34:50 +00:00
Akira Hatanaka fb9bae34da Implement Mips64's handling of byval arguments in LowerFormalArguments. 
llvm-svn: 144449
 2011-11-12 02:29:58 +00:00
Akira Hatanaka 202f6400ef Function for handling byval arguments. 
llvm-svn: 144447
 2011-11-12 02:20:46 +00:00
Bruno Cardoso Lopes c85e3ff334 Mips MC object code emission improvements: 
"With this patch we can now generate runnable Mips code through LLVM
direct object emission. We have run numerous simple programs, both C
and C++ and with -O0 and -O3 from the output. The code is not production
ready, but quite useful for experimentation." Patch and message by
Jack Carter

llvm-svn: 144414
 2011-11-11 22:58:42 +00:00
Akira Hatanaka 4a63d1c0f0 Do not try to detect DAG combine patterns for integer multiply-add/sub if value 
type is not i32. MIPS does not have 64-bit integer multiply-add/sub
instructions.

llvm-svn: 144373
 2011-11-11 04:18:21 +00:00
Akira Hatanaka 21cbc25bbb 64-bit atomic instructions. 
llvm-svn: 144372
 2011-11-11 04:14:30 +00:00
Akira Hatanaka 9189d7127f Modify LowerFRAMEADDR. Use 64-bit register FP_64 when ABI is N64. 
llvm-svn: 144371
 2011-11-11 04:11:56 +00:00
Akira Hatanaka 4bdfec57ba Add 64-bit versions of LEA_ADDiu and DynAlloc. Modify LowerDYNAMIC_STACKALLOC. 
llvm-svn: 144370
 2011-11-11 04:06:38 +00:00
Pete Cooper 82cd9e81fc Added invariant field to the DAG.getLoad method and changed all calls. 
When this field is true it means that the load is from constant (runt-time or compile-time) and so can be hoisted from loops or moved around other memory accesses

llvm-svn: 144100
 2011-11-08 18:42:53 +00:00
Akira Hatanaka 104b7e3f2c Make changes necessary in LowerFormalArguments to support Mips64. 
llvm-svn: 143218
 2011-10-28 19:55:48 +00:00
Akira Hatanaka b20a325baf Make changes necessary in LowerCall to support Mips64. 
llvm-svn: 143217
 2011-10-28 19:49:00 +00:00
Akira Hatanaka 7989f15d37 Add variable IsO32 to MipsTargetLowering. 
llvm-svn: 143213
 2011-10-28 18:47:24 +00:00
Eli Friedman 4c42be5b32 Fix misc warnings. Patch by Joe Abbey. 
llvm-svn: 142332
 2011-10-18 03:17:34 +00:00
Akira Hatanaka a7e0b90897 Add definitions of conditional moves with 64-bit operands. Comment out code for 
expanding conditional moves, which is not needed since architectures that lack
support for conditional moves have been removed. 

llvm-svn: 142226
 2011-10-17 18:53:29 +00:00
Akira Hatanaka 09b23eb7bc Modify lowering of GlobalAddress so that correct code is emitted when target is 
Mips64.

llvm-svn: 141618
 2011-10-11 00:55:05 +00:00
Akira Hatanaka be68f3c348 Add definitions of 64-bit loads and stores. Add a patterns for unaligned 
zextloadi32 for which there is no corresponding pseudo or real instruction. 

llvm-svn: 141608
 2011-10-11 00:27:28 +00:00
Akira Hatanaka b1538f91dc Add support for 64-bit divide instructions. 
llvm-svn: 141024
 2011-10-03 21:06:13 +00:00
Akira Hatanaka 7ba8a8d656 Add definitions of Mips64 rotate instructions. 
llvm-svn: 140870
 2011-09-30 18:51:46 +00:00
Akira Hatanaka a6a9c20c23 Set register class of a register according to value of HasMips64. 
llvm-svn: 140570
 2011-09-26 21:55:17 +00:00
Akira Hatanaka 7b502920ef Define variable HasMips64 in MipsTargetLowering. 
llvm-svn: 140569
 2011-09-26 21:47:02 +00:00
Akira Hatanaka e5ce709022 In single float mode, double precision FP arguments are passed in integer 
registers, so there is no need to check here.

llvm-svn: 140568
 2011-09-26 21:37:50 +00:00
Akira Hatanaka e96273e75d Preparation for adding simple Mips64 instructions. 
llvm-svn: 140443
 2011-09-24 01:34:44 +00:00
Akira Hatanaka ceb55e72de Make FGR64RegisterClass available if target is Mips64. 
llvm-svn: 140397
 2011-09-23 18:28:39 +00:00
Akira Hatanaka 61bbcce84a Do not rely on the enum values of argument registers A0-A3 being consecutive. 
Define function getNextIntArgReg, which takes a register as a parameter and
returns the next O32 argument integer register. Use this function when double
precision floating point arguments are passed in two integer registers.

llvm-svn: 140363
 2011-09-23 00:58:33 +00:00
Akira Hatanaka 6a5f8b2fd4 Remove unnecessary condition check. 
llvm-svn: 140291
 2011-09-22 02:41:29 +00:00
Akira Hatanaka bb49e721b8 Change the names of functions isMips* to hasMips*. 
llvm-svn: 140214
 2011-09-20 23:53:09 +00:00
Akira Hatanaka 79738336a8 Make changes to avoid creating nested CALLSEQ_START/END constructs, which aren't 
yet legal according to comments in LegalizeDAG.cpp:227. 

Memcpy nodes created for copying byval arguments are inserted before
CALLSEQ_START.

The two failing tests reported in PR10876 pass after applying this patch.  

llvm-svn: 140046
 2011-09-19 20:26:02 +00:00
Duncan Sands f2641e1bc1 Add codegen support for vector select (in the IR this means a select 
with a vector condition); such selects become VSELECT codegen nodes.
This patch also removes VSETCC codegen nodes, unifying them with SETCC
nodes (codegen was actually often using SETCC for vector SETCC already).
This ensures that various DAG combiner optimizations kick in for vector
comparisons.  Passes dragonegg bootstrap with no testsuite regressions
(nightly testsuite as well as "make check-all").  Patch mostly by
Nadav Rotem.

llvm-svn: 139159
 2011-09-06 19:07:46 +00:00
Eli Friedman 7dfa791f4f Expand ATOMIC_LOAD and ATOMIC_STORE for architectures I don't know well enough to fix properly. 
llvm-svn: 138751
 2011-08-29 18:23:02 +00:00
Akira Hatanaka 419fd4f315 Fix bug in function IsShiftedMask. Remove parameter SizeInBits, which is not 
needed for Mips32.

llvm-svn: 138132
 2011-08-19 22:59:00 +00:00
Akira Hatanaka fb4161ae88 Use subword loads instead of a 4-byte load when the size of a structure (or a 
piece of it) that is being passed by value is smaller than a word.

llvm-svn: 138007
 2011-08-18 23:39:37 +00:00
Akira Hatanaka 73d78b7ab1 Make IsShiftedMask a static function rather than defining it in an 
anonymous namespace.

llvm-svn: 137975
 2011-08-18 20:07:42 +00:00
Akira Hatanaka eea541ce4e Changed definition of EXT and INS per Bruno's comments. 
llvm-svn: 137892
 2011-08-17 22:59:46 +00:00
Akira Hatanaka b2e7558c40 Add support for half-word unaligned loads and stores. 
llvm-svn: 137848
 2011-08-17 18:49:18 +00:00
Akira Hatanaka 184b63d09c Move pattern matching for EXT and INS to post-legalization DAGCombine per Bruno's comment. 
llvm-svn: 137831
 2011-08-17 17:45:08 +00:00
Akira Hatanaka 5360f88355 Add support for ext and ins. 
llvm-svn: 137804
 2011-08-17 02:05:42 +00:00
Akira Hatanaka 2fcc1cfdce Define unaligned load and store. 
llvm-svn: 137515
 2011-08-12 21:30:06 +00:00
Eli Friedman 30a49e93e3 New approach to r136737: insert the necessary fences for atomic ops in platform-independent code, since a bunch of platforms (ARM, Mips, PPC, Alpha are the relevant targets here) need to do essentially the same thing. 
I think this completes the basic CodeGen for atomicrmw and cmpxchg.

llvm-svn: 136813
 2011-08-03 21:06:02 +00:00
Eli Friedman 26a484852e Code generation for 'fence' instruction. 
llvm-svn: 136283
 2011-07-27 22:21:52 +00:00
Akira Hatanaka a4c09bce9b Lower memory barriers to sync instructions. 
llvm-svn: 135537
 2011-07-19 23:30:50 +00:00
Akira Hatanaka 9663dd3f00 Change variable name. 
llvm-svn: 135522
 2011-07-19 20:56:53 +00:00
Akira Hatanaka f3b29992d5 Use the correct opcodes: SLLV/SRLV or AND must be used instead of SLL/SRL or 
ANDi, when the instruction does not have any immediate operands.

llvm-svn: 135520
 2011-07-19 20:34:00 +00:00
Akira Hatanaka 0e01959327 Use descriptive variable names. 
llvm-svn: 135514
 2011-07-19 20:11:17 +00:00
Akira Hatanaka db2ccdcfd2 Fix comments. 
llvm-svn: 135496
 2011-07-19 18:19:40 +00:00
Akira Hatanaka e450358a21 Remove redundant instructions. 
- In EmitAtomicBinaryPartword, mask incr in loopMBB only if atomic.swap is the
  instruction being expanded, instead of masking it in thisMBB. 
- Remove redundant Or in EmitAtomicCmpSwap. 

llvm-svn: 135495
 2011-07-19 18:14:26 +00:00
Akira Hatanaka 08636b4633 Separate code that modifies control flow from code that adds instruction to 
basic blocks.

llvm-svn: 135490
 2011-07-19 17:09:53 +00:00
Akira Hatanaka e4e9a590d2 Make EmitAtomic functions return the correct MachineBasicBlocks so that 
ExpandISelPseudos::runOnMachineFunction does not visit instructions that have
just been added.

llvm-svn: 135465
 2011-07-19 03:42:13 +00:00
Akira Hatanaka e97bd81f07 Do not insert instructions in reverse order. 
llvm-svn: 135464
 2011-07-19 03:14:58 +00:00
Akira Hatanaka 338879a7f4 Do not treat atomic.load.sub differently than other atomic binary intrinsics. 
llvm-svn: 135418
 2011-07-18 19:58:59 +00:00
Akira Hatanaka 27292638bd Set mayLoad or mayStore flags for SC and LL in order to prevent LICM from 
moving them out of the loop. Previously, stores and loads to a stack frame
object were inserted to accomplish this. Remove the code that was needed to do
this. Patch by Sasa Stankovic.

llvm-svn: 135415
 2011-07-18 18:52:12 +00:00
Akira Hatanaka 8b98515c29 Change destination register operands of SC instructions so that unique 
virtual registers are used. 

llvm-svn: 135403
 2011-07-18 17:44:27 +00:00
Chris Lattner 229907cd11 land David Blaikie's patch to de-constify Type, with a few tweaks. 
llvm-svn: 135375
 2011-07-18 04:54:35 +00:00
Cameron Zwarich f03fa189ca Add an intrinsic and codegen support for fused multiply-accumulate. The intent 
is to use this for architectures that have a native FMA instruction.

llvm-svn: 134742
 2011-07-08 21:39:21 +00:00
Akira Hatanaka 9c6028f98e Lower MachineInstr to MC Inst and print to .s files. 
llvm-svn: 134661
 2011-07-07 23:56:50 +00:00
Akira Hatanaka 2e766ed2f8 Reverse order of operands of address operand mem so that the base operand comes 
before the offset. This change will enable simplification of function
MipsRegisterInfo::eliminateFrameIndex.

llvm-svn: 134625
 2011-07-07 18:57:00 +00:00
Eric Christopher eaf77dc2bd Update comment for getRegForInlineAsmConstraint for Mips. 
llvm-svn: 134087
 2011-06-29 19:33:04 +00:00
Eric Christopher 9519c08a43 Remove getRegClassForInlineAsmConstraint for Mips. 
Part of rdar://9643582

llvm-svn: 134084
 2011-06-29 19:04:31 +00:00
Akira Hatanaka 35792089e7 Change the chain input of nodes that load the address of a function. This change 
enables SelectionDAG::getLoad at MipsISelLowering.cpp:1914 to return a
pre-existing node instead of redundantly create a new node every time it is
called.

llvm-svn: 133811
 2011-06-24 19:01:25 +00:00
Akira Hatanaka 5b350be79d Coding style fixes. 
llvm-svn: 133496
 2011-06-21 01:02:03 +00:00
Akira Hatanaka 4c406e7457 Re-apply 132758 and 132768 which were speculatively reverted in 132777. 
llvm-svn: 133494
 2011-06-21 00:40:49 +00:00
Bruno Cardoso Lopes 5444a7b4cd Silence warnings in non assert builds. Patch by David Blaikie 
llvm-svn: 133118
 2011-06-16 00:40:02 +00:00
Eric Christopher f15601f19a Speculatively revert 132758 and 132768 to try to fix the Windows buildbots. 
llvm-svn: 132777
 2011-06-09 16:03:19 +00:00
Eric Christopher 0713a9d8fc Add a parameter to CCState so that it can access the MachineFunction. 
No functional change.

Part of PR6965

llvm-svn: 132763
 2011-06-08 23:55:35 +00:00
Akira Hatanaka 4e9af454f7 Fix bug in lowering of DYNAMIC_STACKALLOC nodes. The correct offset of the 
dynamically allocated stack area was not set.

llvm-svn: 132758
 2011-06-08 21:28:09 +00:00
Akira Hatanaka 195a1e2184 Reorganize code in MipsTargetLowering::LowerCall to improve readability. 
llvm-svn: 132756
 2011-06-08 17:39:33 +00:00
Akira Hatanaka 41956cf6e3 Refactor MipsTargetLowering::EmitInstrWithCustomInserter. 
llvm-svn: 132726
 2011-06-07 19:28:39 +00:00
Akira Hatanaka 1550678765 Coding style fixes. 
- Fix indentation.
- Move comments.
- Fit lines in 80 columns.
- Remove dead code.

llvm-svn: 132724
 2011-06-07 18:58:42 +00:00
Akira Hatanaka 6627752050 Custom-lower FRAMEADDR. Patch by Sasa Stankovic. 
llvm-svn: 132444
 2011-06-02 00:24:44 +00:00
Bruno Cardoso Lopes f771a0f490 Fix uninitialized variables and silence warnings 
llvm-svn: 132355
 2011-05-31 20:25:26 +00:00
Bruno Cardoso Lopes 98fc4c8bbc This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, 
nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions.
The intrinsics are implemented by creating pseudo-instructions, which are
then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter.

Patch by Sasa Stankovic.

llvm-svn: 132323
 2011-05-31 02:54:07 +00:00
Bruno Cardoso Lopes bf3c1251e0 This patch implements the thread local storage. Implemented are General 
Dynamic, Initial Exec and Local Exec TLS models.

Patch by Sasa Stankovic

llvm-svn: 132322
 2011-05-31 02:53:58 +00:00
Akira Hatanaka b406843fe5 Define a wrapper node for target constant nodes (tglobaladdr, etc.). 
Need this to prevent emitting illegal conditional move instructions. 

llvm-svn: 132240
 2011-05-28 01:07:07 +00:00
Akira Hatanaka 077964a03c Use MachineFrameInfo::hasCalls instead of MipsFunctionInfo::hasCall to check if 
a function has any function calls.

llvm-svn: 132140
 2011-05-26 20:30:31 +00:00
Akira Hatanaka aa560006ed Add support for C++ exception handling. 
llvm-svn: 132131
 2011-05-26 18:59:03 +00:00
Akira Hatanaka f1412e4d2f Remove MipsTargetLowering::LowerFP_TO_SINT. Patterns for fp_to_sint have already 
been defined in MipsInstrFPU.td.

llvm-svn: 132076
 2011-05-25 20:08:05 +00:00
Akira Hatanaka 44eba3ac49 Custom-lower FCOPYSIGN nodes. 
llvm-svn: 132074
 2011-05-25 19:32:07 +00:00
Akira Hatanaka d72cc55fcc Update MaxCallFrameSize regardless of the relocation model selected. 
llvm-svn: 132070
 2011-05-25 18:08:32 +00:00
Akira Hatanaka 92a26d4e18 Change initial value of MaxCallFrameSize. MipsFI::getMaxCallFrameSize() should 
return 0 if there are no function calls made. 

llvm-svn: 132065
 2011-05-25 17:52:48 +00:00
Akira Hatanaka 46662e0f91 Coding style fixes. Added comments. 
llvm-svn: 132063
 2011-05-25 17:32:06 +00:00
Akira Hatanaka aac670c1c8 Fix lowering of DYNAMIC_STACKALLOC nodes. 
llvm-svn: 132030
 2011-05-25 02:20:00 +00:00
Akira Hatanaka 5e16c6a9b2 Implement byval structure argument passing. The following limitations or 
deficiencies exist:

- Works only if ABI is o32.
- Zero-sized structures cannot be passed.
- There is a lot of redundancy in generated code.

llvm-svn: 131986
 2011-05-24 19:18:33 +00:00
Akira Hatanaka cb4a1a8d3f Simplify offset calculation of stack frame objects for $gp restore location and 
variable arguments in LowerCall and LowerFormalArguments. This should also fix
the bug in which handling of variable arguments is incorrect when the front-end
optimizes away unused fixed arguments.

llvm-svn: 131942
 2011-05-24 00:23:52 +00:00
Akira Hatanaka dfb8cda11f Expand f64 FPOW. 
llvm-svn: 131928
 2011-05-23 22:23:58 +00:00
Akira Hatanaka 9dbb45b596 Fixes related to coding style. 
llvm-svn: 131922
 2011-05-23 21:13:59 +00:00
Akira Hatanaka f9e5750fc8 Change StackDirection from StackGrowsUp to StackGrowsDown. 
The following improvements are accomplished as a result of applying this patch:
- Fixed frame objects' offsets (relative to either the virtual frame pointer or
  the stack pointer) are set before instruction selection is completed. There is
  no need to wait until Prologue/Epilogue Insertion is run to set them.
- Calculation of final offsets of fixed frame objects is straightforward. It is
  no longer necessary to assign negative offsets to fixed objects for incoming
  arguments in order to distinguish them from the others.
- Since a fixed object has its relative offset set during instruction
  selection, there is no need to conservatively set its alignment to 4.
- It is no longer necessary to reorder non-fixed frame objects in 
  MipsFrameLowering::adjustMipsStackFrame.

llvm-svn: 131915
 2011-05-23 20:16:59 +00:00
Akira Hatanaka 0837692ac6 Change the order fixed objects are created in MipsTargetLowering::LowerCall in 
preparation for reversing StackDirection.

Fixed objects are created in the following order:  
 1. Incoming arguments passed on stack.
 2. va_arg objects (include both arguments that are passed in registers and
    pointer to the location of the first va_arg argument).
 3. $gp restore slot.
 4. Outgoing arguments passed on stack.
 5. Pointer to alloca'd space.

llvm-svn: 131767
 2011-05-20 23:22:14 +00:00
Akira Hatanaka 7c619f174a In CC_MipsO32, allocate a stack space regardless of whether the argument is 
passed in register or on the stack.

llvm-svn: 131758
 2011-05-20 21:39:54 +00:00
Akira Hatanaka 43407fe633 Make $fp and $ra callee-saved registers and let PrologEpilogInserter handle 
saving and restoring them.

llvm-svn: 131745
 2011-05-20 18:39:33 +00:00
Akira Hatanaka fe4f9d5977 Fix bug in which nodes that write to argument registers do not get glued with the JALR node. Patch by Sasa Stankovic 
llvm-svn: 131714
 2011-05-20 02:30:51 +00:00
Akira Hatanaka 7489faa0c1 Remove code that creates unnecessary frame objects. 
llvm-svn: 131711
 2011-05-20 01:45:06 +00:00
Akira Hatanaka 9e6a8cca5d Align i64 arguments to 64 bit boundaries. 
llvm-svn: 131668
 2011-05-19 20:29:48 +00:00
Akira Hatanaka 92ab6db6c8 Simplify CC_MipsO32 and merge it with CC_MipsO32_VarArgs. Patch by Sasa Stankovic. 
llvm-svn: 131657
 2011-05-19 18:06:05 +00:00
Eli Friedman 2518f8376d Make the logic for determining function alignment more explicit. No functionality change. 
llvm-svn: 131012
 2011-05-06 20:34:06 +00:00
Akira Hatanaka 23e8ecf125 Prevent instructions using $gp from being placed between a jalr and the instruction that restores the clobbered $gp. 
llvm-svn: 130847
 2011-05-04 17:54:27 +00:00
Akira Hatanaka 0e7ee666b7 Lower BlockAddress node when relocation-model is static. 
llvm-svn: 130131
 2011-04-25 17:10:45 +00:00
Akira Hatanaka e24891251c Reverse unnecessary changes made in r129606 and r129608. There is no change in functionality. 
llvm-svn: 129612
 2011-04-15 21:51:11 +00:00
Akira Hatanaka aef55c8801 Fix lines that have incorrect indentation or exceed 80 columns. There is no change in functionality. 
llvm-svn: 129606
 2011-04-15 21:00:26 +00:00
Akira Hatanaka 279169771b Add pass that expands pseudo instructions into target instructions after register allocation. Define pseudos that get expanded into mtc1 or mfc1 instructions. 
llvm-svn: 129594
 2011-04-15 19:52:08 +00:00
Chris Lattner 0ab5e2cded Fix a ton of comment typos found by codespell. Patch by 
Luis Felipe Strano Moraes!

llvm-svn: 129558
 2011-04-15 05:18:47 +00:00
Akira Hatanaka d6f1c58914 Fix handling of functions with internal linkage. 
llvm-svn: 129099
 2011-04-07 19:51:44 +00:00
Akira Hatanaka 5ec2ead9b0 Move transformation of JmpLink and related nodes done during instruction selection to Legalize phase. 
llvm-svn: 128830
 2011-04-04 17:11:07 +00:00
Akira Hatanaka 4111db6575 Undo changes mistakenly made in revision 128750. 
llvm-svn: 128751
 2011-04-02 00:26:12 +00:00
Akira Hatanaka 977f555a76 Insert space before ';' to prevent warnings. 
llvm-svn: 128750
 2011-04-02 00:15:58 +00:00
Akira Hatanaka 56d9ef53a2 Simplifies logic for printing target flags. 
llvm-svn: 128741
 2011-04-01 21:41:06 +00:00
Akira Hatanaka a535270d91 Added support for FP conditional move instructions and fixed bugs in handling of FP comparisons. 
llvm-svn: 128650
 2011-03-31 18:26:17 +00:00
Akira Hatanaka 4e9ca1b3ba fixed typo 
llvm-svn: 128574
 2011-03-30 21:15:35 +00:00
Chris Lattner 05a23b1e61 silence a conditional assignment -Wuninitialized warning. 
llvm-svn: 127453
 2011-03-11 02:12:51 +00:00
Bruno Cardoso Lopes 048ffabe78 Improve varags handling, with testcases. Patch by Sasa Stankovic 
llvm-svn: 127349
 2011-03-09 19:22:22 +00:00
Bruno Cardoso Lopes 434248a62c Improve div/rem node handling on mips. Patch by Akira Hatanaka 
llvm-svn: 127034
 2011-03-04 21:03:24 +00:00
Bruno Cardoso Lopes 8887d6593f Rewrite and simplify o32 vaarg passing, no functional changes. Patch by Sasa Stankovic 
llvm-svn: 127029
 2011-03-04 20:27:44 +00:00
Bruno Cardoso Lopes f8198e4311 Lowers block address. Currently asserts when relocation model is not PIC. Patch by Akira Hatanaka 
llvm-svn: 127027
 2011-03-04 20:01:52 +00:00