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12 Commits

Author SHA1 Message Date
Hrvoje Varga dbe4d96b4f [mips][microMIPS] Implement DBITSWAP, DLSA and LWUPC and add tests for AUI instructions 
Differential Revision: https://reviews.llvm.org/D16452

llvm-svn: 280909
 2016-09-08 07:41:43 +00:00
Hrvoje Varga 24b975dc66 [mips][micromips] Implement LD, LLD, LWU, SD, DSRL, DSRL32 and DSRLV instructions 
Differential Revision: http://reviews.llvm.org/D16625

llvm-svn: 273850
 2016-06-27 08:23:28 +00:00
Hrvoje Varga f1e0a03d08 [mips][micromips] Implement DCLO, DCLZ, DROTR, DROTR32 and DROTRV instructions 
Differential Revision: http://reviews.llvm.org/D16917

llvm-svn: 272876
 2016-06-16 07:06:25 +00:00
Hrvoje Varga aeb1fe8f20 [mips][micromips] Implement DSBH, DSHD, DSLL, DSLL32, DSLLV, DSRA, DSRA32 and DSRAV instructions 
Differential Revision: http://reviews.llvm.org/D16800

llvm-svn: 269169
 2016-05-11 11:17:04 +00:00
Zoran Jovanovic 9360c10a88 [mips][microMIPS] Implement ldpc instruction 
Differential Revision: http://reviews.llvm.org/D15009

llvm-svn: 266990
 2016-04-21 14:32:12 +00:00
Zlatko Buljan 58d6a959be [mips][microMIPS] Add CodeGen support for DIV, MOD, DIVU, MODU, DDIV, DMOD, DDIVU and DMODU instructions 
Differential Revision: http://reviews.llvm.org/D17137

This patch was reverted after the revertion of dependant patch http://reviews.llvm.org/D17068.
There was the problem with test-suite failure.
The problem is hopefully solved with dependant patch so this patch is commited again.

llvm-svn: 266179
 2016-04-13 08:02:26 +00:00
Zlatko Buljan 53a037f5cc [mips][microMIPS] Add CodeGen support for ADD, ADDIU*, ADDU* and DADD* instructions 
Differential Revision: http://reviews.llvm.org/D16454

llvm-svn: 265772
 2016-04-08 07:27:26 +00:00
Zoran Jovanovic 2b7cc5a4ae [mips][microMIPS] Revert commits r264245 and r264248. 
Commit r264245 was the reason for failing tests in LLVM test suite.
Commit r264248 depends on the first one.

llvm-svn: 265249
 2016-04-02 23:06:13 +00:00
Zlatko Buljan 94af4cbcf4 [mips][microMIPS] Add CodeGen support for DIV, MOD, DIVU, MODU, DDIV, DMOD, DDIVU and DMODU instructions 
Differential Revision: http://reviews.llvm.org/D17137

llvm-svn: 264248
 2016-03-24 09:22:45 +00:00
Hrvoje Varga 2cb74ac3c3 [mips][microMIPS] Implement MTC*, MTHC* and DMTC* instructions 
Differential Revision: http://reviews.llvm.org/D17328

llvm-svn: 264246
 2016-03-24 08:02:09 +00:00
Zoran Jovanovic 2fe8466f6e [mips][microMIPS] Implement DDIV, DMOD, DDIVU and DMODU instructions 
Differential Revision: http://reviews.llvm.org/D10953

llvm-svn: 245297
 2015-08-18 14:40:43 +00:00
Zoran Jovanovic 366783e14c [mips][microMIPS] Create microMIPS64r6 subtarget and implement DALIGN, DAUI, DAHI, DATI, DEXT, DEXTM and DEXTU instructions 
Differential Revision: http://reviews.llvm.org/D10923

llvm-svn: 244744
 2015-08-12 12:45:16 +00:00