Commit Graph

374834 Commits

Author SHA1 Message Date
Raul Tambre 33b740f8dc [CMake][compiler-rt][AArch64] Avoid preprocessing LSE builtins separately
Invoking the preprocessor ourselves is fragile and would require us to replicate CMake's handling of definitions, compiler flags, etc for proper compatibility.
In my toolchain builds this notably resulted in a bunch of warnings from unused flags as my CMAKE_C_FLAGS includes CPU-specific optimization options.
Notably this part was already duplicating the logic for VISIBILITY_HIDDEN define.

Instead, symlink the files and set the proper set of defines on each.
This should also be faster as we avoid invoking the compiler multiple times.

Fixes https://llvm.org/PR48494

Reviewed By: ilinpv

Differential Revision: https://reviews.llvm.org/D93178
2020-12-14 09:20:30 +02:00
Richard Smith 7de9c61f31 Fix test expectation to cope with custom version namespaces. 2020-12-13 22:43:24 -08:00
Richard Smith 05cdf4acf4 Consider reference, pointer, and pointer-to-member TemplateArguments to be different if they have different types.
For the Itanium ABI, this implements the mangling rule suggested in
https://github.com/itanium-cxx-abi/cxx-abi/issues/47, namely mangling
such template arguments as being cast to the parameter type in the case
where the template name is overloadable. This can cause a mangling
change for rare cases, where

 * the template argument declaration is converted from its declared type
   to the type of the template parameter, and
 * the template parameter either has a deduced type or is a parameter of
   a function template.

However, such changes are necessary to avoid mangling collisions. The
ABI changes can be reversed with -fclang-abi-compat=11 or earlier.

Re-commit with a fix for the regression introduced last time: don't
expect parameters and arguments to line up inside an <unresolved-name>
mangling.

Differential Revision: https://reviews.llvm.org/D91488
2020-12-13 22:43:24 -08:00
Richard Smith abbd57e558 Factor out and centralize repeated 'getExpandedPackSize'. 2020-12-13 22:43:23 -08:00
Anton Afanasyev b8c847ee73 [SLP][Test] Precommit test for D93192
This test shows failure of combined stores chains vectorization
2020-12-14 09:23:47 +03:00
Chen Zheng 4830d458dd [MachineCombiner][NFC] Add MustReduceRegisterPressure goal
add a new goal MustReduceRegisterPressure for machine combiner pass.

PowerPC will use this new goal to do some register pressure related optimization.

Reviewed By: spatel

Differential Revision: https://reviews.llvm.org/D92068
2020-12-14 00:02:42 -05:00
Kazu Hirata ee5b5b7a35 [CodeGen] Use llvm::erase_value (NFC) 2020-12-13 20:05:48 -08:00
Kazu Hirata 913515e465 [Target] Use llvm::is_contained (NFC) 2020-12-13 19:35:10 -08:00
Arthur Eubanks 655011c713 [opt][NPM] Pin -lower-amx-type to legacy PM
This is part of the codegen pipeline.
2020-12-13 19:16:20 -08:00
Lang Hames 04795ab836 Re-apply 8904ee8ac7 with missing header included this time. 2020-12-14 13:39:33 +11:00
Nico Weber 5b112bcc0d Revert "[JITLink] Add JITLinkDylib type, thread through JITLinkMemoryManager APIs."
This reverts commit 8904ee8ac7.
Didn't `git add` llvm/ExecutionEngine/JITLink/JITLinkDylib.h and hence doesn't
build anywhere.
2020-12-13 21:30:38 -05:00
Lang Hames 8904ee8ac7 [JITLink] Add JITLinkDylib type, thread through JITLinkMemoryManager APIs.
JITLinkDylib represents a target dylib for a JITLink link. By representing this
explicitly we can:
  - Enable JITLinkMemoryManagers to manage allocations on a per-dylib basis
    (e.g by maintaining a seperate allocation pool for each JITLinkDylib).
  - Enable new features and diagnostics that require information about the
    target dylib (not implemented in this patch).
2020-12-14 12:29:16 +11:00
Lang Hames 77bb3c1ac2 [JITLink] Fix include guard end comment. 2020-12-14 12:00:21 +11:00
Lang Hames 0207de0bfe [ORC] Prefer preincrement on iterator. 2020-12-14 12:00:21 +11:00
Nathan Ridge fef242c32e [clangd] Fix locateMacroAt() for macro definition outside preamble
Fixes https://github.com/clangd/clangd/issues/577

Differential Revision: https://reviews.llvm.org/D91025
2020-12-13 18:33:33 -05:00
Tony 5ad202ce89 [NFC][AMDGPU] Reformat AMD GPU targets in cuda.cpp
Differential Revision: https://reviews.llvm.org/D93181
2020-12-13 23:02:59 +00:00
Craig Topper 0261ce9e17 [X86] Add ExeDomain = SSEPackedSingle to cvtss2sd and cvtsd2ss instrutions.
Prep for D92993
2020-12-13 12:35:33 -08:00
Craig Topper fa31f337a2 [X86] Add isel patterns to form VPDPWSSD from (add (vpmaddwd X, Y), Z) when AVXVNNI is enabled.
We already have these patterns for AVX512VNNI.
2020-12-13 12:02:07 -08:00
Nikita Popov 22dba707b0 [AC] Handle (X+C1)<C2 assumes (PR48408)
InstCombine canonicalizes X>C && X<C' style comparisons into
(X+C1)<C2. This type of expression is recognized by some analyses
like LVI, but currently not when used inside assumptions, because
AssumptionCache does not track affected values for it.
2020-12-13 21:00:32 +01:00
Harald van Dijk f99b4f5241
[X86] Extend varargs test
This extends the existing x86-64-varargs test by passing enough
arguments that they need to be passed in memory, and by passing them in
reverse order, using va_arg for each argument to retrieve them and
restoring them to the correct order, and by using va_copy to have two
va_lists to use with va_arg.
2020-12-13 18:33:10 +00:00
Kazu Hirata 0a4e028d13 [Analysis] Remove unused declaration replaceEdgeKey (NFC)
The declaration was introduced without a corresponding definition on
Feb 9, 2017 in commit aaad9f84be.
2020-12-13 10:03:45 -08:00
Kazu Hirata 5891ad4e22 [Transforms] Use llvm::erase_value (NFC) 2020-12-13 09:48:47 -08:00
Tony 828602c772 [NFC]{AMDGPU] Update AMDGPUUsage with AMD RDNA 2 reference
Differential Revision: https://reviews.llvm.org/D93172
2020-12-13 17:21:02 +00:00
Simon Pilgrim d5c434d7dd [X86][SSE] combineX86ShufflesRecursively - add basic handling for combining shuffles of different widths (PR45974)
If a faux shuffle uses smaller shuffle inputs, try to recursively combine with those inputs directly instead of widening them immediately. Then widen all smaller inputs at the bottom of the recursion.

This will still mean we're generating nodes on the fly (PR45974) even if we don't combine to a new shuffle but it does help AVX2+ targets combine across xmm/ymm/zmm types, mainly as variable shuffles.
2020-12-13 17:18:07 +00:00
Simon Pilgrim 8bdfc1222f [X86][AVX] Add additional X86ISD::SUBV_BROADCAST_LOAD test case for D92645
Suggested by @yubing - to check whether we can reuse a single subvector broadcast for 128/256/512-bit vectors.
2020-12-13 16:43:33 +00:00
Florian Hahn 533f85767c
[VPlan] Use interleaveComma in printOperands() (NFC). 2020-12-13 16:29:16 +00:00
Florian Hahn 46bc40e502
Recommit "[AArch64] Lower calls with rv_marker attribute."
This recommits a87fccb3ff with a fix to mark the destination operand
of the marker instruction as def, to fix a machine verifier failure.

This reverts the revert commit c0f2cea7c0.
2020-12-13 16:20:39 +00:00
Simon Pilgrim 4855a1004d [X86] Convert fadd/fmul _mm_reduce_* intrinsics to emit llvm.reduction intrinsics (PR47506)
Followup to D87604, having confirmed on PR47506 that we can use the llvm codegen expansion for fadd/fmul as well.

Differential Revision: https://reviews.llvm.org/D92940
2020-12-13 15:37:35 +00:00
Simon Pilgrim 47321c311b [X86][SSE] combineReductionToHorizontal - add vXi8 ISD::MUL reduction handling (PR39709)
Default expansion leads to repeated extensions/truncations to/from vXi16 which shuffle combining and demanded elts can't completely unravel.

Better just to promote (any_extend) the input and perform a vXi16 reduction.

We'll be able to remove a lot of this if we ever get decent legalization support for reduction intrinsics in SelectionDAG.
2020-12-13 15:22:54 +00:00
Jacques Pienaar 9c3fa3d84d Don't emit on op diagnostic in reproducer emission
This avoids dumping the module post emitting a reproducer, which results in
many MB logs where a reproducer has already been neatly generated.

Differential Revision: https://reviews.llvm.org/D93165
2020-12-13 07:21:32 -08:00
ergawy 076f87a867 [MLIR][SPIRV] Add support for GLSL F/U/SClamp.
Adds support for 3 ternary ops from SPIR-V extended instructions for
GLSL. Namely, adds support for FClamp, UClamp, and SClamp.

Reviewed By: antiagainst

Differential Revision: https://reviews.llvm.org/D92859
2020-12-13 09:56:46 -05:00
Simon Pilgrim 0ee73bb24a [X86] Regenerate vector-reduce-mul.ll with common check prefixes. NFC.
Try to merge AVX1/AVX2/AVX512 codegen checks where possible
2020-12-13 14:25:42 +00:00
Björn Schäpers 36306403d4 [clang-format] Remove double trim
Lines[i] is already trimmed 3 lines before

Differential Revision: https://reviews.llvm.org/D91996
2020-12-13 14:16:54 +01:00
Nikita Popov bb939ebfd7 [BasicAA] Handle known non-zero variable index
BasicAA currently handles cases like Scale*V0 + (-Scale)*V1 where
V0 != V1, but does not handle the simpler case of Scale*V with
V != 0. Add it based on an isKnownNonZero() call.

I'm not passing a context instruction for now, because the existing
approach of always using GEP1 for context could result in symmetry
issues.

Differential Revision: https://reviews.llvm.org/D93162
2020-12-13 13:20:05 +01:00
Kazushi (Jam) Marukawa 05d1729232 [VE] Optimize toolchain regression test
Optimize toolchain regression test for VE by removing not a useful test
(-fuse-init-array test) and merge several tests to one test which checks
default behavior of driver.  Also add sysroot to reduce conflicts.

These are suggested in https://reviews.llvm.org/D92996.
Thank you so much.

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D93084
2020-12-13 20:26:05 +09:00
Michał Górny 0cd8686043 [lldb] [Process/FreeBSD] Add more 'override' keywords 2020-12-13 09:59:32 +01:00
Christian Sigg 1ffc1aaa09 [mlir] Use mlir::OpState::operator->() to get to methods of mlir::Operation.
This is a preparation step to remove those methods from OpState.

Reviewed By: mehdi_amini

Differential Revision: https://reviews.llvm.org/D93098
2020-12-13 09:58:16 +01:00
Chris Lattner a44e630353 [AsmParser] Fix support for zero bit integer types.
Zero bit integer types are supported by IntegerType for consistency,
but the asmparser never got updated. Allow them to be parsed, as
required to fix CIRCT issue #316

Differential Revision: https://reviews.llvm.org/D93089
2020-12-12 21:24:18 -08:00
kweisamx c84b53ca9b [mlir] Add Python binding for MLIR Dict Attribute
Reviewed By: mehdi_amini

Differential Revision: https://reviews.llvm.org/D93004
2020-12-13 04:30:35 +00:00
Nico Weber ba3bc2fd41 [mac/arm] Deflake 3 check-llvm tests
On macOS/arm, signature verification has kill semantics by default.
Signature verification is cached with a file's inode (actually, vnode),
and if a new executable is copied over an existing file (which reuses
the inode), the cache isn't invalidated. So when the new executable
is executed, the kernel still has the old content's signature cached
and the kills the executable because the old signatue doesn't match
the new contents (https://openradar.appspot.com/FB8914243).

As workaround, rm the desitnation files first, to ensure they have
a fresh vnode (and hence no stale cached signature) after the copy.

Part of PR46647. See also e0e334a9c1 for a similar change.
2020-12-12 21:14:45 -05:00
Chris Sears 36a23b33aa X86: Correcting X86OutgoingValueHandler typo (NFC)
https://reviews.llvm.org/D92631
2020-12-12 20:28:37 -05:00
Nico Weber cf16437e05 fix typos to cycle bots 2020-12-12 20:19:33 -05:00
Nico Weber 9c6a884f67 fix typo to cycle bots 2020-12-12 20:16:14 -05:00
Nico Weber de1bca4b36 mac/arm: XFAIL the last 2 failing check-llvm tests
We should fix them, but let's XFAIL them for now so that we can start
running check-llvm on bots and lock in the passing tests.

Part of PR46647.
2020-12-12 20:12:02 -05:00
Fangrui Song 5d1c723b73 [ELF][test] Rewrite st_value=0 copy relocation tests
The original tests have unneeded symbols and copy-relocation-zero-abs-addr.s
does not actually test anything.

Rewrite them and add copy-relocation-zero-addr.s instead.

Add --soname=b so that the address 0x203400 will be stable.  (When linking an
executable with %t.so, the path %t.so will be recorded in the DT_NEEDED entry if
%t.so doesn't have DT_SONAME. .dynstr will have varying lengths on different
systems.)
2020-12-12 16:50:25 -08:00
Nico Weber eaa0982334 [mac/arm] skip MappedMemoryTest that try to map w+x
macOS/arm is w^x, so these tests don't work. Fixes these failures:

  LLVM-Unit :: Support/./SupportTests/AllocationTests/MappedMemoryTest.AllocAndRelease/5
  LLVM-Unit :: Support/./SupportTests/AllocationTests/MappedMemoryTest.AllocAndReleaseHuge/5
  LLVM-Unit :: Support/./SupportTests/AllocationTests/MappedMemoryTest.BasicWrite/5
  LLVM-Unit :: Support/./SupportTests/AllocationTests/MappedMemoryTest.DuplicateNear/5
  LLVM-Unit :: Support/./SupportTests/AllocationTests/MappedMemoryTest.EnabledWrite/3
  LLVM-Unit :: Support/./SupportTests/AllocationTests/MappedMemoryTest.EnabledWrite/4
  LLVM-Unit :: Support/./SupportTests/AllocationTests/MappedMemoryTest.EnabledWrite/5
  LLVM-Unit :: Support/./SupportTests/AllocationTests/MappedMemoryTest.MultipleAllocAndRelease/5
  LLVM-Unit :: Support/./SupportTests/AllocationTests/MappedMemoryTest.MultipleWrite/5
  LLVM-Unit :: Support/./SupportTests/AllocationTests/MappedMemoryTest.SuccessiveNear/5
  LLVM-Unit :: Support/./SupportTests/AllocationTests/MappedMemoryTest.UnalignedNear/5
  LLVM-Unit :: Support/./SupportTests/AllocationTests/MappedMemoryTest.ZeroNear/5
  LLVM-Unit :: Support/./SupportTests/AllocationTests/MappedMemoryTest.ZeroSizeNear/5

Part of PR46647.
2020-12-12 19:46:32 -05:00
Craig Topper 7977fee43c [X86] Autogenerate complete checks. NFC 2020-12-12 16:37:28 -08:00
Amara Emerson 21de99d43c [[GlobalISel][IRTranslator] Fix a crash when the use of an extractvalue is a non-dominated metadata use.
We don't expect uses to come before defs in the CFG, so allocateVRegs() asserted.

Fixes PR48211
2020-12-12 14:58:54 -08:00
Roman Lebedev d38205144f
[SimplifyCFG] FoldBranchToCommonDest(): bonus instrns must only be used by PHI nodes in successors (PR48450)
In particular, if the successor block, which is about to get a new
predecessor block, currently only has a single predecessor,
then the bonus instructions will be directly used within said successor,
which is fine, since the block with bonus instructions dominates that
successor. But once there's a new predecessor, the IR is no longer valid,
and we don't fix it, because we only update PHI nodes.

Which means, the live-out bonus instructions must be exclusively used
by the PHI nodes in successor blocks. So we have to form trivial PHI nodes.
which will then be successfully updated to recieve cloned bonus instns.

This all works fine, except for the fact that we don't have access to
the dominator tree, and we don't ignore unreachable code,
so we sometimes do end up having to deal with some weird IR.

Fixes https://bugs.llvm.org/show_bug.cgi?id=48450
2020-12-13 00:06:57 +03:00
Zarko Todorovski ce4040a43d [PPC] Check for PPC64 when emitting 64bit specific VSX nodes when pattern matching built vectors
Some of the pattern matching in PPCInstrVSX.td and node lowering involving vectors assumes 64bit mode.  This patch disables some of the unsafe pattern matching and lowering of BUILD_VECTOR in 32bit mode.

Reviewed By: Xiangling_L

Differential Revision: https://reviews.llvm.org/D92789
2020-12-12 15:28:28 -05:00