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51 Commits

Author SHA1 Message Date
Craig Topper 9b6a65b9ef [X86] Reduce number of OpPrefix bits in TSFlags to 2. NFCI 
TSFlag doesn't need to disambiguate NoPrfx from PS. So shift the encodings so PS is NoPrfx|0x4.

llvm-svn: 329049
 2018-04-03 06:37:04 +00:00
Craig Topper e865641aea [X86] Merge the Has3DNow0F0FOpcode TSFlag into the OpMap encoding. NFC 
The 3DNow instructions are encoded a little weird, but we can still represent it as an opcode map.

llvm-svn: 328410
 2018-03-24 06:04:12 +00:00
Rafael Auler de9ad4ba84 [X86][3DNOW] Teach decoder about AMD 3DNow! instrs 
Summary:
This patch makes the decoder understand old AMD 3DNow!
instructions that have never been properly supported in the X86
disassembler, despite being supported in other subsystems. Hopefully
this should make the X86 decoder more complete with respect to binaries
containing legacy code.

Reviewers: craig.topper

Reviewed By: craig.topper

Subscribers: llvm-commits, maksfb, bruno

Differential Revision: https://reviews.llvm.org/D43311

llvm-svn: 325295
 2018-02-15 21:20:31 +00:00
Craig Topper 326008c615 [X86] Fix disassembly of EVEX rounding control and SAE instructions. 
Fixes PR31955.

llvm-svn: 316308
 2017-10-23 02:26:24 +00:00
Hiroshi Inoue 2344b7611a fix trivial typos in comments; NFC 
llvm-svn: 307075
 2017-07-04 13:09:29 +00:00
Ayman Musa 3c18f19008 [X86] Moving X86Local namespace from .cpp to .h file to use it in memory folding TableGen backend. 
Differential Revision: https://reviews.llvm.org/D32797

llvm-svn: 302791
 2017-05-11 11:51:12 +00:00
Ayman Musa 51ffeab8c8 [X86][AVX] Extend hasVEX_WPrefix bit to accept WIG value (W Ignore) + update all AVX instructions with the new value. 
Add WIG value to all of AVX instructions which ignore the W-bit in their encoding, instead of giving them the default value of 0.
This patch is needed for a follow up work on EVEX2VEX pass (replacing EVEX encoded instructions with their corresponding VEX version when possible).

Differential Revision: https://reviews.llvm.org/D29876

llvm-svn: 295643
 2017-02-20 08:27:54 +00:00
Craig Topper 5f8419da34 [X86] Create a new instruction format to handle 4VOp3 encoding. This saves one bit in TSFlags and simplifies MRMSrcMem/MRMSrcReg format handling. 
llvm-svn: 279424
 2016-08-22 07:38:50 +00:00
Craig Topper 9b20fece81 [X86] Create a new instruction format to handle MemOp4 encoding. This saves one bit in TSFlags and simplifies MRMSrcMem/MRMSrcReg format handling. 
llvm-svn: 279423
 2016-08-22 07:38:45 +00:00
Mehdi Amini b550cb1750 [NFC] Header cleanup 
Removed some unused headers, replaced some headers with forward class declarations.

Found using simple scripts like this one:
clear && ack --cpp -l '#include "llvm/ADT/IndexedMap.h"' | xargs grep -L 'IndexedMap[<]' | xargs grep -n --color=auto 'IndexedMap'

Patch by Eugene Kosov <claprix@yandex.ru>

Differential Revision: http://reviews.llvm.org/D19219

From: Mehdi Amini <mehdi.amini@apple.com>
llvm-svn: 266595
 2016-04-18 09:17:29 +00:00
Craig Topper 983be941bf [TableGen] Stop passing by reference an integer that doesn't get modified. NFC 
llvm-svn: 260934
 2016-02-16 04:24:56 +00:00
Craig Topper b89d189d37 [TableGen] Remove unused member variable. NFC 
llvm-svn: 260933
 2016-02-16 04:24:54 +00:00
Craig Topper b86338f7b2 [X86] Remove the single AdSize indicator and replace it with separate AdSize16/32/64 flags. 
This removes a hardcoded list of instructions in the CodeEmitter. Eventually I intend to remove the predicates on the affected instructions since in any given mode two of them are valid if we supported addr32/addr16 prefixes in the assembler.

llvm-svn: 224809
 2014-12-24 06:05:22 +00:00
Benjamin Kramer a7c40ef022 Canonicalize header guards into a common format. 
Add header guards to files that were missing guards. Remove #endif comments
as they don't seem common in LLVM (we can easily add them back if we decide
they're useful)

Changes made by clang-tidy with minor tweaks.

llvm-svn: 215558
 2014-08-13 16:26:38 +00:00
Adam Nemet 5933c2f824 [X86] AVX512: Add disassembler support for compressed displacement 
There are two parts here.  First is to modify tablegen to adjust the encoding
type ENCODING_RM with the scaling factor.

The second is to use the new encoding types to compute the correct
displacement in the decoder.

Fixes <rdar://problem/17608489>

llvm-svn: 213281
 2014-07-17 17:04:56 +00:00
Craig Topper e2347df24d [x86] Switch PAUSE instruction to use XS prefix instead of HasREPPrefix. Remove HasREPPrefix support from disassembler table generator since its now only used by CodeGenOnly instructions. 
llvm-svn: 201767
 2014-02-20 07:59:43 +00:00
Craig Topper 7aaa0c2ddb Remove unused method declaration. 
llvm-svn: 201301
 2014-02-13 07:12:40 +00:00
Craig Topper 69e245c01d Remove filtering concept from X86 disassembler table generation. It's no longer necessary. 
llvm-svn: 201299
 2014-02-13 07:07:16 +00:00
Craig Topper 5b3a6bd370 Remove special case filtering for instructions with lock prefix as they are all marked with isCodeGenOnly already. 
llvm-svn: 201216
 2014-02-12 08:09:20 +00:00
NAKAMURA Takumi d8dd194f03 TableGen/X86RecognizableInstr.h: Prune out-of-date "@param isSSE". [-Wdocumentation] 
llvm-svn: 200628
 2014-02-02 10:53:36 +00:00
Craig Topper fa6298a162 Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. 
llvm-svn: 200626
 2014-02-02 09:25:09 +00:00
Craig Topper d402df3ce8 Merge HasVEXPrefix/HasEVEXPrefix/HasXOPPrefix into a 2-bit 'encoding' field in TSFlags. 
llvm-svn: 200624
 2014-02-02 07:08:01 +00:00
Craig Topper 10243c8907 Separate x86 opcode maps and 0x66/0xf2/0xf3 prefixes from each other in the TSFlags. This greatly simplifies the switch statements in the disassembler tables and the code emitters. 
llvm-svn: 200522
 2014-01-31 08:47:06 +00:00
Craig Topper ec68866f55 Move REP out of the Prefix field of the X86 format. Give it its own bit. It had special handling anyway and this enables a future patch. 
llvm-svn: 200520
 2014-01-31 07:00:55 +00:00
Craig Topper b7c7f38918 Simplify x86 disassembler table handling of when to use TYPE_Rv/TYPE_R16/TYPE_R32 now that HasOpSizePrefix only means 16-bit instructions. 
llvm-svn: 199295
 2014-01-15 05:02:02 +00:00
Craig Topper 2ea87dad77 The rest of r198588. Remove SegOvrBits from X86 TSFlags since they weren't being used. 
llvm-svn: 198589
 2014-01-06 06:57:27 +00:00
Craig Topper 3484fc2161 Add a new x86 specific instruction flag to force some isCodeGenOnly instructions to go through to the disassembler tables without resorting to string matches. Apply flag to all _REV instructions. 
llvm-svn: 198543
 2014-01-05 04:17:28 +00:00
Craig Topper fae226c67e Remove unused HasFROperands field from disassembler. 
llvm-svn: 198332
 2014-01-02 18:44:21 +00:00
Craig Topper 83b7e24b76 Remove unused function argument. 
llvm-svn: 198291
 2014-01-02 03:58:45 +00:00
Elena Demikhovsky dacddb0bab AVX-512: added VPCONFLICT instruction and intrinsics, 
added EVEX_KZ to tablegen

llvm-svn: 193959
 2013-11-03 13:46:31 +00:00
Elena Demikhovsky 003e7d73b9 Added encoding prefixes for KNL instructions (EVEX). 
Added 512-bit operands printing.
Added instruction formats for KNL instructions.

llvm-svn: 187324
 2013-07-28 08:28:38 +00:00
Chandler Carruth 91d19d8e93 Sort the #include lines for utils/... 
I've tried to find main moudle headers where possible, but the TableGen
stuff may warrant someone else looking at it.

llvm-svn: 169251
 2012-12-04 10:37:14 +00:00
Craig Topper 3f23c1a8b9 Remove code for setting the VEX L-bit as a function of operand size from the code emitters and the disassembler table builder. Fix a couple instructions that were still missing VEX_L. 
llvm-svn: 164204
 2012-09-19 06:37:45 +00:00
Dmitri Gribenko 2bc1d483fe Fix Doxygen issues: 
* wrap code blocks in \code ... \endcode;
* refer to parameter names in paragraphs correctly (\arg is not what most
  people want -- it starts a new paragraph).

llvm-svn: 163790
 2012-09-13 12:34:29 +00:00
Dmitri Gribenko 65340a69e1 Fix a bunch of -Wdocumentation warnings. 
llvm-svn: 162446
 2012-08-23 16:54:08 +00:00
Craig Topper f7755df776 Update GATHER instructions to support 2 read-write operands. Patch from myself and Manman Ren. 
llvm-svn: 160110
 2012-07-12 06:52:41 +00:00
Craig Topper 6491c8020e X86 disassembler support for jcxz, jecxz, and jrcxz. Fixes PR11643. Patch by Kay Tiong Khoo. 
llvm-svn: 151510
 2012-02-27 01:54:29 +00:00
Craig Topper 03a0beda88 Add FMA4 instructions to disassembler. 
llvm-svn: 147367
 2011-12-30 05:20:36 +00:00
Craig Topper aea148c366 Add X86 BZHI instruction as well as BMI2 feature detection. 
llvm-svn: 142122
 2011-10-16 07:55:05 +00:00
Craig Topper 25ea4e5ad3 Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand 3 instead of Operand 2 so needs special casing in the disassembler and code emitter. Ultimately, should pass this information from tablegen 
llvm-svn: 142105
 2011-10-16 03:51:13 +00:00
Craig Topper f18c896337 Add support in the disassembler for ignoring the L-bit on certain VEX instructions. Mark instructions that have this behavior. Fixes PR10676. 
llvm-svn: 141065
 2011-10-04 06:30:42 +00:00
Peter Collingbourne 84c287e33c Move TableGen's parser and entry point into a library 
This is the first step towards splitting LLVM and Clang's tblgen executables.

llvm-svn: 140951
 2011-10-01 16:41:13 +00:00
Craig Topper 526adabe87 Don't allow 32-bit only instructions to be disassembled in 64-bit mode. Fixes part of PR10700. 
llvm-svn: 140370
 2011-09-23 06:57:25 +00:00
Eli Friedman 0318036c4d Make the disassembler able to disassemble a bunch of instructions with names in the TableGen files containing "64" on x86-32. This includes a bunch of x87 instructions, like fld, and a bunch of SSSE3 instructions on MMX registers like pshufb. Part of PR8873. 
llvm-svn: 135337
 2011-07-16 02:41:28 +00:00
Sean Callanan c3fd523731 X86 table-generator and disassembler support for the AVX 
instruction set.  This code adds support for the VEX prefix
and for the YMM registers accessible on AVX-enabled
architectures.  Instruction table support that enables AVX
instructions for the disassembler is in an upcoming patch.

llvm-svn: 127644
 2011-03-15 01:23:15 +00:00
Michael J. Spencer ab425d8360 I swear I did a make clean and make before committing all this... 
llvm-svn: 120304
 2010-11-29 18:47:54 +00:00
Chris Lattner d8adec70f3 factor the operand list (and related fields/operations) out of 
CodeGenInstruction into its own helper class.  No functionality change.

llvm-svn: 117893
 2010-11-01 04:03:32 +00:00
Bruno Cardoso Lopes c2f87b7bb2 Reapply r105521, this time appending "LLU" to 64 bit 
immediates to avoid breaking the build.

llvm-svn: 105652
 2010-06-08 22:51:23 +00:00
Chris Lattner fdd2614330 revert r105521, which is breaking the buildbots with stuff like this: 
In file included from X86InstrInfo.cpp:16:
X86GenInstrInfo.inc:2789: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2790: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2792: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2793: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2808: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2809: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2816: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2817: error: integer constant is too large for 'long' type

llvm-svn: 105524
 2010-06-05 04:17:30 +00:00
Bruno Cardoso Lopes 594fa26317 Initial AVX support for some instructions. No patterns matched 
yet, only assembly encoding support.

llvm-svn: 105521
 2010-06-05 03:53:24 +00:00