Commit Graph

10 Commits

Author SHA1 Message Date
Evandro Menezes 6b8d8f4010 [AArch64] Adjust the cost model for Exynos M3
Fix typo and simplify matching expression.

llvm-svn: 329130
2018-04-03 22:57:17 +00:00
Evandro Menezes 36afbee1d8 [AArch64] Adjust the cost model for Exynos M3
Fix typo in the number of integer dividers.

llvm-svn: 328027
2018-03-20 20:00:29 +00:00
Craig Topper e1d6a4df1c [TableGen] When trying to reuse a scheduler class for instructions from an InstRW, make sure we haven't already seen another InstRW containing this instruction on this CPU.
This is similar to the check later when we remap some of the instructions from one class to a new one. But if we reuse the class we don't get to do that check.

So many CPUs have violations of this check that I had to add a flag to the SchedMachineModel to allow it to be disabled. Hopefully we can get those cleaned up quickly and remove this flag.

A lot of the violations are due to overlapping regular expressions, but that's not the only kind of issue it found.

llvm-svn: 327808
2018-03-18 19:56:15 +00:00
Evandro Menezes d4254ac1b9 [AArch64] Adjust the cost model for Exynos M3
Fix typo.

llvm-svn: 327663
2018-03-15 20:37:32 +00:00
Evandro Menezes 5303f897d4 [AArch64] Adjust the cost model for Exynos M3
Add special case for rotate right.

llvm-svn: 327662
2018-03-15 20:31:25 +00:00
Evandro Menezes 1515e859c6 [AArch64] Adjust the cost model for Exynos M3
Increase the number of cheap as move cases of register reset.

llvm-svn: 327661
2018-03-15 20:31:13 +00:00
Evandro Menezes 205c0e085e [AArch64] Adjust the cost model for Exynos M3
Fix the modeling of transfers between a generic register and a partial ASIMD
one.

llvm-svn: 324766
2018-02-09 19:26:11 +00:00
Evandro Menezes cb7959fd78 [AArch64] Adjust the cost model for Exynos M3
Fix the modeling of long division and SIMD conversion from integer and
horizontal minimum and maximum.

llvm-svn: 324417
2018-02-06 22:35:47 +00:00
Clement Courbet ea8d07eb76 [AArch64][NFC] Make all ProcResource definitions include their SchedModel.
This makes targets ExynosM1,ExynosM3,ThunderX2T99 consistent with all
other targets.

llvm-svn: 323955
2018-02-01 12:12:01 +00:00
Evandro Menezes 9f9daa1f14 [AArch64] Add pipeline model for Exynos M3
Add the scheduling and cost model for Exynos M3.

Differential revision: https://reviews.llvm.org/D42387

llvm-svn: 323773
2018-01-30 15:40:16 +00:00