5 Commits

Author	SHA1	Message	Date
Simon Dardis	b79ecec20d	[mips] Fix predicates of mfc1, mtc1 instructions ... Reviewers: atanasyan, abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D46692 llvm-svn: 332339	2018-05-15 11:10:30 +00:00
Simon Dardis	fba0362096	[mips] Correct the predicates of indexed floating point stores and loads. ... Also, fix the register class for microMIPS. Reviewers: atanasyan, abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D46689 llvm-svn: 332227	2018-05-14 10:53:15 +00:00
Simon Dardis	ce6ada4151	[mips] Correct the predicates of cvt.fmt.fmt instructions ... Reviewers: atanasyan, smaksimovic, abeserminji Differential Revision: https://reviews.llvm.org/D46390 llvm-svn: 331969	2018-05-10 10:42:30 +00:00
Stefan Maksimovic	b3e7ed3b94	[mips] Define certain instructions in microMIPS32r3 ... Instructions affected: mthc1, mfhc1, add.d, sub.d, mul.d, div.d, mov.d, neg.d, cvt.w.d, cvt.d.s, cvt.d.w, cvt.s.d These instructions are now defined for microMIPS32r3 + microMIPS32r6 in MicroMipsInstrFPU.td since they shared their encoding with those already defined in microMIPS32r6InstrInfo.td and have been therefore removed from the latter file. Some instructions present in MicroMipsInstrFPU.td which did not have both AFGR64 and FGR64 variants defined have been altered to do so. Differential revision: https://reviews.llvm.org/D42738 llvm-svn: 324584	2018-02-08 09:25:17 +00:00
Stefan Maksimovic	98749e0249	[mips] Properly select abs and sqrt instructions ... - Alter abs for micromips to have both AFGR64 and FGR64 variants, same as sqrt - Remove sqrt and abs from MicroMips32r6InstrInfo.td, use micromips FGR64 variants - Restrict non-micromips abs/sqrt with NotInMicroMips predicate Differential revision: https://reviews.llvm.org/D41439 llvm-svn: 323184	2018-01-23 10:09:39 +00:00