Commit Graph

357499 Commits

Author SHA1 Message Date
Mircea Trofin 29e5722949 Revert "[llvm] Added support for stand-alone cmake object libraries."
This reverts commit 695c7d6313.

Breaks windows (e.g.
http://lab.llvm.org:8011/builders/clang-x64-windows-msvc/builds/16497)

Likely to cause problems with XCode.
2020-06-15 12:15:39 -07:00
Davide Italiano e51e82745e [Target/PPC] Fold inside an assertion.
Pointed out by dblaikie.
2020-06-15 12:08:57 -07:00
Mircea Trofin 695c7d6313 [llvm] Added support for stand-alone cmake object libraries.
Summary:
Currently, add_llvm_library would create an OBJECT library alongside
of a STATIC / SHARED library, but losing the link interface (its
elements would become dependencies instead). To support scenarios
where linking an object library also brings in its usage
requirements, this patch adds support for 'stand-alone' OBJECT
libraries - i.e. without an accompanying SHARED/STATIC library, and
maintaining the link interface defined by the user.

The support is via a new option, OBJECT_ONLY, to avoid breaking changes
- since just specifying "OBJECT" would currently imply also STATIC or
SHARED, depending on BUILD_SHARED_LIBS.

This is useful for cases where, for example, we want to build a part
of a component separately. Using a STATIC target would incur the risk
that symbols not referenced in the consumer would be dropped (which may
be undesirable).

The current application is the ML part of Analysis. It should be part
of the Analysis component, so it may reference other analyses; and (in
upcoming changes) it has dependencies on optional libraries.

Reviewers: karies, davidxl

Subscribers: mgorny, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D81447
2020-06-15 12:01:43 -07:00
Matt Arsenault e07cf92377 AMDGPU/GlobalISel: Don't hardcode maximum register size
This is a somewhat artifical limit, so avoid repeating it many places
in case it changes.
2020-06-15 15:01:19 -04:00
Louis Dionne 96e48e9a61 [libc++] Add the ability to run arbitrary programs using the DSL
This is useful for checking runtime properties of the target system.
This is a partial re-application of 3ea9450bda. This part was tested
to work on a Windows host with a SSH executor.
2020-06-15 14:59:53 -04:00
Matt Arsenault 1a7f115dce AMDGPU/GlobalISel: Extend load/store workaround to i128 vectors 2020-06-15 14:55:11 -04:00
Mehdi Amini a9a21bb4b6 Revert "[mlir] Add support for lowering tanh to LLVMIR."
This reverts commit 32c757e4f8.

Broke the build bot:

******************** TEST 'MLIR :: Examples/standalone/test.toy' FAILED ********************
[...]
/tmp/ci-KIMiRFcVZt/lib/libMLIRLinalgToLLVM.a(LinalgToLLVM.cpp.o): In function `(anonymous namespace)::ConvertLinalgToLLVMPass::runOnOperation()':
LinalgToLLVM.cpp:(.text._ZN12_GLOBAL__N_123ConvertLinalgToLLVMPass14runOnOperationEv+0x100): undefined reference to `mlir::populateExpandTanhPattern(mlir::OwningRewritePatternList&, mlir::MLIRContext*)'
2020-06-15 18:46:57 +00:00
Rahul Joshi 72d20b9604 [LLVM] Change isa<> to a variadic function template
Change isa<> to a variadic function template, so that it can be used to test against one of multiple types as follows:
   isa<Type0, Type1, Type2>(Val)

Differential Revision: https://reviews.llvm.org/D81045
2020-06-15 18:46:57 +00:00
Julian Lettner 968f58c684 [lit] Include unexecuted tests in xUnit report
Pass in all discovered tests to report generators.

The XunitReport generator now creates testcase items for unexecuted
tests and documents why they have been skipped.  This makes it easier
to compare test runs with different filters or configurations, or across
platforms.

I don't know who is using the JsonReport generator and what the
expectations there are (it doesn't have tests), so decided to preserve
the old behavior by filtering out the unexecuted tests.

Reviewed By: jdenny

Differential Revision: https://reviews.llvm.org/D81316
2020-06-15 11:36:31 -07:00
Lang Hames 5682f192bd [RuntimeDyld] Add dependence on Core.
Commit 498dd745f5 introduced a dependence on Core. This patch updates
LLVMbuild.txt to reflect this.
2020-06-15 11:14:27 -07:00
Matt Arsenault 362eedcbb4 AMDGPU/GlobalISel: Correct memory size in test 2020-06-15 14:12:28 -04:00
aartbik 91801a7c34 [mlir] [integration-test] [VectorOps] Start an integration test directory for MLIR
Summary:
This CL introduces an integration test directory for MLIR in general, with
vector dialect integration tests in particular as a first working suite. To
run all the integration tests (and currently just the vector suite):

$ cmake --build . --target check-mlir-integration
[0/1] Running the MLIR integration tests
Testing Time: 0.24s
Passed: 22

The general call is to contribute to this integration test directory with more
tests and other suites, running end-to-end examples that may be too heavy for
the regular test directory, but should be tested occasionally to verify the
health of MLIR.

Background discussion at:
https://llvm.discourse.group/t/vectorops-rfc-add-suite-of-integration-tests-for-vector-dialect-operations/1213/

Reviewers: nicolasvasilache, reidtatge, andydavis1, rriddle, ftynse, mehdi_amini, jpienaar, stephenneuendorffer

Reviewed By: nicolasvasilache, stephenneuendorffer

Subscribers: mgorny, mehdi_amini, rriddle, jpienaar, shauheen, antiagainst, nicolasvasilache, arpith-jacob, mgester, lucyrfox, liufengdb, stephenneuendorffer, Joonsoo, grosul1, frgossen, Kayjukh, jurahul, msifontes

Tags: #mlir

Differential Revision: https://reviews.llvm.org/D81626
2020-06-15 11:05:58 -07:00
Davide Italiano 5cb44196aa [Target/PPC] Silence an unused variable warning. NFC. 2020-06-15 11:05:01 -07:00
Craig Topper d72cb4ce21 Recommit "[X86] Separate imm from relocImm handling."
Fix the copy/paste mistake that caused it to fail previously
2020-06-15 10:59:43 -07:00
Florian Hahn 120c059292 [DSE,MSSA] Port partial store merging.
Port partial constant store merging logic to MemorySSA backed DSE. The
heavy lifting is done by the existing helper function. It is used in
context where we already ensured that the later instruction can
eliminate the earlier one, if it is a complete overwrite.
2020-06-15 18:41:46 +01:00
Hanhan Wang 32c757e4f8 [mlir] Add support for lowering tanh to LLVMIR.
Summary:
Add a pattern for expanding tanh op into exp form.
A `tanh` is expanded into:
   1) 1-exp^{-2x} / 1+exp^{-2x}, if x => 0
   2) exp^{2x}-1 / exp^{2x}+1  , if x < 0.

Differential Revision: https://reviews.llvm.org/D81618
2020-06-15 10:29:31 -07:00
Lang Hames 498dd745f5 [ORC] Honor linker private global prefix on symbol names.
If a symbol name begins with the linker private global prefix (as
described by the DataLayout) then it should be treated as non-exported,
regardless of its LLVM IR visibility value.
2020-06-15 10:28:36 -07:00
Louis Dionne e54828ad47 [libc++abi] Ensure custom libc++ header paths are honoured during libc++abi build
This is necessary for standalone builds where the libc++ in use has a
custom configuration set up inside __config_site -- one needs to build
libc++abi against the installed headers of libc++ (which are properly
configured) instead of the ones inside libcxx/include.

See https://reviews.llvm.org/rGe619e9d#927848 for details.
2020-06-15 13:22:51 -04:00
Nico Weber 32f1a909b8 [gn build] (manually) merge 3b29376e3f 2020-06-15 13:21:34 -04:00
Wouter van Oortmerssen 3b29376e3f [WebAssembly] Adding 64-bit version of R_WASM_MEMORY_ADDR_* relocs
This adds 4 new reloc types.

A lot of code that previously assumed any memory or offset values could be contained in a uint32_t (and often truncated results from functions returning 64-bit values) have been upgraded to uint64_t. This is not comprehensive: it is only the values that come in contact with the new relocation values and their dependents.

A new tablegen mapping was added to automatically upgrade loads/stores in the assembler, which otherwise has no way to select for these instructions (since they are indentical other than for the offset immediate). It follows a similar technique to https://reviews.llvm.org/D53307

Differential Revision: https://reviews.llvm.org/D81704
2020-06-15 10:07:42 -07:00
Francesco Petrogalli 017969de76 [llvm][SveEmitter] SVE ACLE for quadword permute intrinsics.
Summary:
The following intrinsics have been added, guarded by the macro
`__ARM_FEATURE_SVE_MATMUL_FP64`:

* svtrn1q[_*]
* svtrn2q[_*]
* svuzp1q[_*]
* svuzp2q[_*]
* svzip1q[_*]
* svzip2q[_*]

Supported types:

* svint[8|16|32|64]_t
* svuint[8|16|32|64]_t
* svfloat[16|32|64]_t

TODO: add support for svbfloat16_t

Reviewers: efriedma, sdesmalen, kmclaughlin, rengolin

Reviewed By: sdesmalen

Subscribers: tschuett, kristof.beyls, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D80851
2020-06-15 16:52:36 +00:00
Joachim Protze 9e5aefc5f9 [OpenMP][Tests] fix data race in an OpenMP runtime test
Reviewed by: AndreyChurbanov

Differential Revision: https://reviews.llvm.org/D81804
2020-06-15 18:48:35 +02:00
Craig Topper ad1c46c3c0 [X86] Remove printanymem/printopaquemem from the InstPrinters. Just tell tablegen to printMemReference directly. NFC
Most of the wrappers exist to print the memory size in Intel syntax
and then call the printMemReference. But printanymem/printopaquemem
don't print anything extra in Intel syntax so just drop them.
2020-06-15 09:46:06 -07:00
Florian Hahn 71a91b9837 [DSE] Hoist partial store merging code into function (NFC).
Hoist the general logic into a new function, because it can be re-used
by the MemorySSA backed DSE as well.
2020-06-15 17:44:24 +01:00
Jessica Paquette 1ac8451a9b [GlobalISel] Simplify G_ADD when it has (0-X) on the LHS or RHS
This implements the following combines:

((0-A) + B) -> B-A
(A + (0-B)) -> A-B

Porting over the basic algebraic combines from the DAGCombiner. There are
several combines which fold adds away into subtracts. This is just the simplest
one.

I noticed that add combines are some of the most commonly hit across CTMark,
(via print statements when they fire), so I'm porting over some of the obvious
ones.

This gives some minor code size improvements on CTMark at -O3 on AArch64.

Differential Revision: https://reviews.llvm.org/D77453
2020-06-15 09:43:24 -07:00
sameeran joshi 93f602b339 [flang] unit test support for out-of-tree and in-tree using google tests framework
Review comments addressed.
2020-06-15 22:09:56 +05:30
Siva Chandra 7e54df6829 [libc] Enable string functions for aarch64. 2020-06-15 09:36:40 -07:00
Jonas Devlieghere d74323606d [lldb] Remove indentation before help output.
This patch remove the indentation before the command help output.
Supposedly it was meant to be aligned with the different subcommands.

Differential revision: https://reviews.llvm.org/D81783
2020-06-15 09:27:17 -07:00
Siva Chandra Reddy 051f0ffdbf [libc] Extract an architecture independent copy of memcpy implementation.
Along that way, platform specific options to memcpy, memset and bzero
builds have been enclosed in conditionals. Also, the optimization level
has been set to -O2 for the memory function builds to actually see the
static functions inlined.

Reviewers: gchatelet

Differential Revision: https://reviews.llvm.org/D81621
2020-06-15 09:24:32 -07:00
Francesco Petrogalli 28a00ac9ba [llvm][SVE] IR intrinsics for quadword permutation instructions.
Summary:
Adding intrinsics and codegen patterns for:

* trn1 <Zd>.q, <Zm>.q, <Zn>.q
* trn2 <Zd>.q, <Zm>.q, <Zn>.q
* zip1 <Zd>.q, <Zm>.q, <Zn>.q
* zip2 <Zd>.q, <Zm>.q, <Zn>.q
* uzp1 <Zd>.q, <Zm>.q, <Zn>.q
* uzp2 <Zd>.q, <Zm>.q, <Zn>.q

These instructions are defined in Armv8.6-A.

Reviewers: sdesmalen, efriedma, kmclaughlin

Reviewed By: sdesmalen

Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D80850
2020-06-15 16:21:56 +00:00
David Truby 9362698450 [flang] Change DIE("unreachable") cases to use llvm_unreachable
Reviewers: sscalpone

Subscribers: llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D79507
2020-06-15 17:21:35 +01:00
Louis Dionne 58610eb368 [libc++] Raise an exception if a Lit feature resolves to an invalid name
This allows reporting issues early when creating feature names.
2020-06-15 12:20:50 -04:00
Nathan Ridge d1505233c8 [clangd] Follow-up to fix lit-test bustage in type-hierarchy.test
This is a follow-up to D81845.
2020-06-15 12:18:21 -04:00
Jacques Pienaar 2b41bc5a8b [mlir][shape] Update test case to new op asm format 2020-06-15 09:04:54 -07:00
Nathan Ridge 7759f70fb0 [clangd] Support typeHierarchy/resolve for children of parents as well
Summary:
The initial implementation of typeHierarchy/resolve only supported
cases where an initial request was made for children, and then
typeHierarchy/resolve was used to get additional levels of children.

However, a client may also want to make an initial request for
parents, and then show other children of those parents, so support
typeHierarchy/resolve for items returned in response to a request
for parents as well.

Subscribers: ilya-biryukov, MaskRay, jkorous, arphaman, kadircet, usaxena95, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D81845
2020-06-15 11:59:23 -04:00
Alex Zinenko 3f5bd53eb1 [mlir] Introduce callback-based builders for AffineForOp
Similarly to `scf::ForOp`, introduce additional `function_ref` arguments to
`AffineForOp::build` that can be used to populate the body of the loop during
its construction. Provide compatibility functions for constructing affine loop
nests using `edsc::ScopedContext`.

`edsc::AffineLoopNestBuilder` and reletad functionality is now deprecated and
will be removed soon, users are expected to switch to `affineLoopNestBuilder`
that provides similar functionality with a simpler OpBuilder-based
implementation.

Differential Revision: https://reviews.llvm.org/D81754
2020-06-15 17:55:49 +02:00
Alex Zinenko 36150c3637 [mlir] Affine symbols: do not expect AffineScope to always exist
In the affine symbol and dimension check, the code currently assumes
`getAffineScope` and its users `isValidDim` and `isValidSymbol` are only called
on values defined in regions that have a parent Op with `AffineScope` trait.
This is not necessarily the case, and these functions may be called on valid IR
that does not satisfy this assumption. Return `nullptr` from `getAffineScope`
if there is no parent op with `AffineScope` trait. Treat this case
conservatively in `isValidSymbol` by only accepting as symbols the values that
are guaranteed to be symbols (constants, and certain operations). No
modifications are necessary to `isValidDim` that delegates most of the work to
`isValidDim`.

Differential Revision: https://reviews.llvm.org/D81753
2020-06-15 17:55:49 +02:00
Alexander Belyaev 3813f24e97 [mlir][shape] Add a pattern to rewrite `shape.reduce` as `scf.for`.
Differential Revision: https://reviews.llvm.org/D81694
2020-06-15 17:54:50 +02:00
Denys Petrov e1741e34e0 [analyzer] Reasoning about comparison expressions in RangeConstraintManager
Summary:

Implemented RangeConstraintManager::getRangeForComparisonSymbol which handles comparison operators.
RangeConstraintManager::getRangeForComparisonSymbol cares about the sanity of comparison expressions sequences helps reasonably to branch an exploded graph.
It can significantly reduce the graph and speed up the analysis. For more details, please, see the differential revision.

This fixes https://bugs.llvm.org/show_bug.cgi?id=13426

Differential Revision: https://reviews.llvm.org/D78933
2020-06-15 18:35:15 +03:00
Matt Arsenault 2ca552322c AMDGPU/GlobalISel: Fix 8-byte aligned, 96-bit scalar loads
These are legal since we can do a 96-bit load on some subtargets, but
this is only for vector loads. If we can't widen the load, it needs to
be broken down once known scalar. For 16-byte alignment, widen to a
128-bit load.
2020-06-15 11:33:16 -04:00
Wouter van Oortmerssen d9e0bbd17b [WebAssembly] Adding 64-bit versions of all load & store ops.
Context: https://github.com/WebAssembly/memory64/blob/master/proposals/memory64/Overview.md
This is just a first step, adding the new instruction variants while keeping the existing 32-bit functionality working.
Some of the basic load/store tests have new wasm64 versions that show that the basics of the target are working.
Further features need implementation, but these will be added in followups to keep things reviewable.

Differential Revision: https://reviews.llvm.org/D80769
2020-06-15 08:31:56 -07:00
Erich Keane 837ca47960 [NFCI] Change the data structure of MaybeODRUseExprSet
In 1eddce41, I fixed a non-deterministic result problem by switching a
SmallPtrSet to a SmallSetVector to ensure we iterated it
deterministically.  Unfortunately, this seems to show a surprisingly
significant compiletime impact.

This patch does 2 things in an attempt to fix this:

First, it makes the 'small size' optimization 4 instead of 2.  As these
are pointers, this only increases the size of Sema by 4
sizeof(pointer)s (2 for the set, 2 for the vector).

Second, instead of using SmallSetVector, which is a SmallVector +
SmallDenseSet, it uses a SetVector of SmallVector + SmallPtrSet.  The
hope is that the pointer-specific optimizations of the SmallPtrSet will
minimize the impact on compile-time.
2020-06-15 08:15:50 -07:00
Florian Hahn 8c61f13a0f [DSE,MSSA] Delete instructions after printing it.
Also enables a now-passing test case, that exposed a crash caused by the
wrong order.
2020-06-15 16:01:36 +01:00
Simon Pilgrim cb8a0ba829 [X86][SSE] Add LowerVectorAllZero helper for checking if all bits of a vector are zero.
Pull the lowering code out of LowerVectorAllZeroTest (and rename it MatchVectorAllZeroTest).

We should be able to reuse this in combineVectorSizedSetCCEquality as well.

Another cleanup to simplify D81547.
2020-06-15 15:54:38 +01:00
Stefan Pintilie 57c9dc0521 [PowerPC] Do not add the relocation addend to the instruction encoding
We should not be adding the relocation addend to the instruction encoding.
This patch removes that and sets those bits to zero.

Differential Revision: https://reviews.llvm.org/D81082
2020-06-15 09:51:34 -05:00
Florian Hahn 979720a9bb [DSE,MSSA] Add additional merging test cases (NFC).
Additional tests added ahead of partial overlapping store merging.
2020-06-15 15:45:07 +01:00
Dmitry Polukhin c98c94d85f [clang-tidy] Add diagnostics level to YAML output
Summary:
Also added BuildDirectory for completness and removed unused `Fix`.

Test Plan: check-all

Reviewers: alexfh, gribozavr2

Subscribers: xazax.hun, cfe-commits

Tags: #clang-tools-extra, #clang

Differential Revision: https://reviews.llvm.org/D79285
2020-06-15 07:40:53 -07:00
Dominik Montada 046566a1d5 [NFC] Remove unnecessary require global-isel from tests 2020-06-15 16:35:18 +02:00
Dominik Montada 87e5742654 [NFC] Add braces to if-statement in MachineVerifier 2020-06-15 16:33:56 +02:00
Simon Pilgrim ae33cbc494 [X86][SSE] LowerVectorAllZeroTest - add support for >256-bit vectors
Reduce by splitting the vector until we reach the target size for PTEST/MOVMSK_PCMPEQ. There might be some cases where AVX512 can perform this with 512-bit vectors but so far I haven't encountered any such pattern that reaches LowerVectorAllZeroTest.

Prep work for D81547
2020-06-15 15:30:24 +01:00