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47 Commits

Author SHA1 Message Date
Hrvoje Varga e51b0e13f3 [mips][microMIPS] Implement RECIP.fmt, RINT.fmt, ROUND.L.fmt, ROUND.W.fmt, SEL.fmt, SELEQZ.fmt, SELNEQZ.fmt and CLASS.fmt 
Differential Revision: http://reviews.llvm.org/D13885

llvm-svn: 254405
 2015-12-01 11:59:21 +00:00
Zoran Jovanovic a887b36167 [mips][microMIPS] Fix issue with offset operand of BALC and BC instructions 
Value of offset operand for microMIPS BALC and BC instructions is currently shifted 2 bits, but it should be 1 bit.
Differential Revision: http://reviews.llvm.org/D14770

llvm-svn: 254296
 2015-11-30 12:56:18 +00:00
Zlatko Buljan 797c2aec6b [mips][microMIPS] Implement LWM16, SB16, SH16, SW16, SWSP and SWM16 instructions 
Differential Revision: http://reviews.llvm.org/D11406

llvm-svn: 252885
 2015-11-12 13:21:33 +00:00
Daniel Sanders ea4f653d18 [mips][ias] Range check uimm2 operands and fix a bug this revealed. 
Summary:
The bug was that the MIPS32R6/MIPS64R6/microMIPS32R6 versions of LSA and DLSA
(unlike the MSA version) failed to account for the off-by-one encoding of the
immediate. The range is actually 1..4 rather than 0..3.

Reviewers: vkalintiris

Subscribers: atanasyan, dsanders, llvm-commits

Differential Revision: http://reviews.llvm.org/D14015

llvm-svn: 252295
 2015-11-06 12:22:31 +00:00
Hrvoje Varga 18148671ee [mips][microMIPS] Implement PAUSE, RDHWR, RDPGPR, SDBBP, SSNOP, SYNC, SYNCI and WAIT instructions 
Differential Revision: http://reviews.llvm.org/D12628

llvm-svn: 251510
 2015-10-28 11:04:29 +00:00
Hrvoje Varga 3c88fbd367 [mips][microMIPS] Implement LB, LBE, LBU and LBUE instructions 
Differential Revision: http://reviews.llvm.org/D11633

llvm-svn: 250511
 2015-10-16 12:24:58 +00:00
Hrvoje Varga 3a3c4b8a39 [mips][microMIPS] Implement BREAK16, LI16, MOVE16, SDBBP16, SUBU16 and XOR16 instructions 
Differential Revision: http://reviews.llvm.org/D11292#inline-103143

llvm-svn: 250381
 2015-10-15 08:39:07 +00:00
Hrvoje Varga 8c9526400e Test commit. 
llvm-svn: 250367
 2015-10-15 05:20:51 +00:00
Zlatko Buljan d76b666a06 Test commit 
llvm-svn: 250026
 2015-10-12 11:19:40 +00:00
Zoran Jovanovic 5a8dffc618 [mips][microMIPS] Implement JALRC16, JRCADDIUSP and JRC16 instructions 
Differential Revision: http://reviews.llvm.org/D11219

llvm-svn: 249317
 2015-10-05 14:00:09 +00:00
Zoran Jovanovic 2960f3a346 [mips][microMIPS] Implement CACHEE, WRPGPR and WSBH instructions 
Differential Revision: http://reviews.llvm.org/D10337

llvm-svn: 249004
 2015-10-01 12:49:27 +00:00
Daniel Sanders 86cce70010 [mips][sched] Split IIBranch into specific instruction classes. 
Summary:
Almost no functional change since the InstrItinData's have been duplicated.
The one functional change is to remove IIBranch from the MSA branches. The
classes will be assigned to the MSA instructions as part of implementing
the P5600 scheduler.

II_IndirectBranchPseudo and II_ReturnPseudo can probably be removed. I've
preserved the itinerary information for the corresponding pseudo
instructions to avoid making a functional change to these pseudos in
this patch.

Reviewers: vkalintiris

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D12189

llvm-svn: 248273
 2015-09-22 13:36:28 +00:00
Zoran Jovanovic 8eb8c9861d [mips] Add support for branch-likely pseudo-instructions 
Differential Revision: http://reviews.llvm.org/D10537

llvm-svn: 247697
 2015-09-15 15:06:26 +00:00
Zoran Jovanovic 7beb737b46 [mips][microMIPS] Implement CACHEE and PREFE instructions for microMIPS32r6 
Differential Revision: http://reviews.llvm.org/D11632

llvm-svn: 247670
 2015-09-15 10:05:10 +00:00
Daniel Sanders 7d6d898826 [mips] Unified the MipsMemSimm9GPRAsmOperand and MipsMemSimm9AsmOperand operands, NFC. 
Summary:
These operands had the same purpose, however the MipsMemSimm9GPRAsmOperand
operand was only for micromips32r6 and the MipsMemSimm9AsmOperand did not
have a ParserMatchClass.

Patch by Scott Egerton

Reviewers: vkalintiris, dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D12730

llvm-svn: 247573
 2015-09-14 15:57:24 +00:00
Zoran Jovanovic 6b28f09d67 [mips][microMIPS] Implement ADDU16, AND16, ANDI16, NOT16, OR16, SLL16 and SRL16 instructions 
Differential Revision: http://reviews.llvm.org/D11178

llvm-svn: 247146
 2015-09-09 13:55:45 +00:00
Zoran Jovanovic d9790793d6 [mips][microMIPS] Implement CACHEE and PREFE instructions 
Differential Revision: http://reviews.llvm.org/D11628

llvm-svn: 247125
 2015-09-09 09:10:46 +00:00
Zoran Jovanovic 2da1437d62 [mips][microMIPS] Implement LLE, LUI, LW and LWE instructions 
Differential Revision: http://reviews.llvm.org/D1179

llvm-svn: 247017
 2015-09-08 15:02:50 +00:00
Zoran Jovanovic 9eaa30d2bf [mips][microMIPS] Implement SB, SBE, SCE, SH and SHE instructions 
Differential Revision: http://reviews.llvm.org/D11801

llvm-svn: 246999
 2015-09-08 10:18:38 +00:00
Zoran Jovanovic 7b85682541 [mips][microMIPS] Implement ABS.fmt, CEIL.L.fmt, CEIL.W.fmt, FLOOR.L.fmt, FLOOR.W.fmt, TRUNC.L.fmt, TRUNC.W.fmt, RSQRT.fmt and SQRT.fmt instructions 
Differential Revision: http://reviews.llvm.org/D11674

llvm-svn: 246968
 2015-09-07 13:01:04 +00:00
Zoran Jovanovic ada7091812 [mips][microMIPS] Implement BC16, BEQZC16 and BNEZC16 instructions 
Differential Revision: http://reviews.llvm.org/D11181

llvm-svn: 246963
 2015-09-07 11:56:37 +00:00
Zoran Jovanovic 14f308e44f [mips][microMIPS] Implement CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, MAX.fmt, MIN.fmt, MAXA.fmt, MINA.fmt and CMP.condn.fmt instructions 
Differential Revision: http://reviews.llvm.org/D12141

llvm-svn: 246960
 2015-09-07 10:31:31 +00:00
Zoran Jovanovic 89ca2b982e [mips][microMIPS] Implement ADD.fmt, SUB.fmt, MOV.fmt, MUL.fmt, DIV.fmt, MADDF.fmt, MSUBF.fmt and NEG.fmt instructions 
Differential Revision: http://reviews.llvm.org/D11978

llvm-svn: 246919
 2015-09-05 09:25:30 +00:00
Zoran Jovanovic a6593ff613 [mips][microMIPS] Implement SW and SWE instructions 
Differential Revision: http://reviews.llvm.org/D10869

llvm-svn: 245293
 2015-08-18 12:53:08 +00:00
Zoran Jovanovic 366783e14c [mips][microMIPS] Create microMIPS64r6 subtarget and implement DALIGN, DAUI, DAHI, DATI, DEXT, DEXTM and DEXTU instructions 
Differential Revision: http://reviews.llvm.org/D10923

llvm-svn: 244744
 2015-08-12 12:45:16 +00:00
Zoran Jovanovic 2a47d08afd [mips][microMIPS] Implement SLL and NOP instructions 
http://reviews.llvm.org/D10474

llvm-svn: 241150
 2015-07-01 09:54:51 +00:00
Zoran Jovanovic 67e04be640 [mips][microMIPS] Implement BREAK, EHB and EI instructions 
http://reviews.llvm.org/D10090

llvm-svn: 240531
 2015-06-24 10:32:16 +00:00
Zoran Jovanovic cdfcbe41f2 [mips][microMIPS] Implement ERET and ERETNC instructions 
http://reviews.llvm.org/D10091

llvm-svn: 239522
 2015-06-11 10:22:46 +00:00
Zoran Jovanovic 85a53a1ed5 [mips][microMIPSr6] Implement SEB and SEH instructions 
Differential Revision: http://reviews.llvm.org/D9739

llvm-svn: 238333
 2015-05-27 15:39:47 +00:00
Jozef Kolek 888830adfe [mips][microMIPSr6] Implement BEQZALC, BGEZALC, BGTZALC, BLEZALC, BLTZALC and BNEZALC instructions 
This patch implements microMIPS32r6 BEQZALC, BGEZALC, BGTZALC, BLEZALC, BLTZALC
and BNEZALC instructions using mapping.

Differential Revision: http://reviews.llvm.org/D10031

llvm-svn: 238325
 2015-05-27 14:19:22 +00:00
Zoran Jovanovic dde61c00c3 [mips][microMIPSr6] Implement NOR, OR, ORI, XOR and XORI instructions 
Differential Revision: http://reviews.llvm.org/D8800

llvm-svn: 237697
 2015-05-19 14:12:55 +00:00
Zoran Jovanovic 299fed6b7d [mips][microMIPSr6] Implement AND and ANDI instructions 
Differential Revision: http://reviews.llvm.org/D8772

llvm-svn: 237696
 2015-05-19 13:32:31 +00:00
Zoran Jovanovic 3825261572 [mips][microMIPSr6] Implement DIV, DIVU, MOD and MODU instructions 
Differential Revision: http://reviews.llvm.org/D8769

llvm-svn: 237685
 2015-05-19 11:21:37 +00:00
Jozef Kolek cc0c0fc926 [mips][microMIPSr6] Implement LSA instruction 
This patch implements LSA instruction using mapping.

Differential Revision: http://reviews.llvm.org/D8919

llvm-svn: 237634
 2015-05-18 23:12:10 +00:00
Jozef Kolek cbb227b48d [mips][microMIPSr6] Implement ALIGN and AUI instructions 
This patch implements ALIGN and AUI instructions using mapping.

Differential Revision: http://reviews.llvm.org/D8782

llvm-svn: 237563
 2015-05-18 11:44:30 +00:00
Jozef Kolek 6fec325d10 [mips][microMIPSr6] Implement CLO and CLZ instructions 
This patch implements CLO and CLZ instructions using mapping.

Differential Revision: http://reviews.llvm.org/D8553

llvm-svn: 237257
 2015-05-13 14:18:11 +00:00
Jozef Kolek 38bb81db85 [mips][microMIPSr6] Implement SELEQZ and SELNEZ instructions 
This patch implements SELEQZ and SELNEZ instructions using mapping.

Differential Revision: http://reviews.llvm.org/D8497

llvm-svn: 237158
 2015-05-12 17:39:32 +00:00
Jozef Kolek 8abad7bacc [mips][microMIPSr6] Implement ALUIPC and AUIPC instructions 
This patch implements ALUIPC and AUIPC instructions using mapping.

Differential Revision: http://reviews.llvm.org/D8441

llvm-svn: 236858
 2015-05-08 14:25:11 +00:00
Jozef Kolek 9ce6e0a926 [mips][microMIPSr6] Implement ADDIUPC and LWPC instructions 
This patch implements ADDIUPC and LWPC instructions using mapping.

Differential Revision: http://reviews.llvm.org/D8415

llvm-svn: 236852
 2015-05-08 13:52:04 +00:00
Jozef Kolek cf98462818 [mips][microMIPSr6] Implement JIALC and JIC instructions 
This patch implements JIALC and JIC instructions using mapping.

Differential Revision: http://reviews.llvm.org/D8389

llvm-svn: 236748
 2015-05-07 17:12:23 +00:00
Zoran Jovanovic 387ce30685 [mips][microMIPSr6] Implement MUL, MUH, MULU and MUHU instructions 
Differential Revision: http://reviews.llvm.org/D8894

llvm-svn: 236131
 2015-04-29 17:23:22 +00:00
Zoran Jovanovic cca29e8f6e [mips][microMIPSr6] Implement SUB and SUBU instructions 
Differential Revision: http://reviews.llvm.org/D8764

llvm-svn: 236118
 2015-04-29 16:22:46 +00:00
Zoran Jovanovic 5f34d44354 [mips][microMIPSr6] Implement ADD, ADDU and ADDIU instructions 
Differential Revision: http://reviews.llvm.org/D8704

llvm-svn: 236111
 2015-04-29 15:11:07 +00:00
Jozef Kolek 8e086cedfa [mips][microMIPSr6] Implement CACHE and PREF instructions 
Implement CACHE and PREF instructions using mapping.

Differential Revision: http://reviews.llvm.org/D8893

llvm-svn: 235379
 2015-04-21 11:17:25 +00:00
Jozef Kolek 207d248eba [mips][microMIPSr6] Implement BITSWAP instruction 
Implement BITSWAP instruction using mapping.

Differential Revision: http://reviews.llvm.org/D8857

llvm-svn: 235321
 2015-04-20 18:14:59 +00:00
Jozef Kolek 676d60125c [mips][microMIPSr6] Implement disassembler support 
Implement disassembler support for microMIPS32r6.

Differential Revision: http://reviews.llvm.org/D8490

llvm-svn: 235307
 2015-04-20 14:40:38 +00:00
Jozef Kolek 5de4a6c0af [mips][microMIPSr6] Implement BALC and BC instructions 
This patch implements BALC and BC instructions using mapping.

Differential Revision: http://reviews.llvm.org/D8388

llvm-svn: 235302
 2015-04-20 13:04:14 +00:00