Commit Graph

16 Commits

Author SHA1 Message Date
Dylan McKay 9a9ae99b30 [AVR] Disallow the LDDWRdPtrQ instruction with Z as the destination
This is an AVR-specific workaround for a limitation of the register
allocator that only exposes itself on targets with high register
contention like AVR, which only has three pointer registers.

The three pointer registers are X, Y, and Z.
In most nontrivial functions, Y is reserved for the frame pointer,
as per the calling convention. This leaves X and Z. Some instructions,
such as LPM ("load program memory"), are only defined for the Z
register. Sometimes this just leaves X.

When the backend generates a LDDWRdPtrQ instruction with Z as the
destination pointer, it usually trips up the register allocator
with this error message:

  LLVM ERROR: ran out of registers during register allocation

This patch is a hacky workaround. We ban the LDDWRdPtrQ instruction
from ever using the Z register as an operand. This gives the
register allocator a bit more space to allocate, fixing the
regalloc exhaustion error.

Here is a description from the patch author Peter Nimmervoll

  As far as I understand the problem occurs when LDDWRdPtrQ uses
  the ptrdispregs register class as target register. This should work, but
  the allocator can't deal with this for some reason. So from my testing,
  it seams like (and I might be totally wrong on this) the allocator reserves
  the Z register for the ICALL instruction and then the register class
  ptrdispregs only has 1 register left and we can't use Y for source and
  destination. Removing the Z register from DREGS fixes the problem but
  removing Y register does not.

More information about the bug can be found on the avr-rust issue
tracker at https://github.com/avr-rust/rust/issues/37.

A bug has raised to track the removal of this workaround and a proper
fix; PR39553 at https://bugs.llvm.org/show_bug.cgi?id=39553.

Patch by Peter Nimmervoll

llvm-svn: 346114
2018-11-05 05:00:44 +00:00
Dylan McKay 454258671d [AVR] Redefine the 'LSL' instruction as an alias of 'ADD'
The 'LSL Rd' instruction is equivalent to 'ADD Rd, Rd'.

llvm-svn: 341278
2018-09-01 12:23:00 +00:00
Dylan McKay 8b0f9d2e58 [AVR] Define the ROL instruction as an alias of ADC
The 'rol Rd' instruction is equivalent to 'adc Rd'.

This caused compile warnings from tablegen because of conflicting bits
shared between each instruction.

llvm-svn: 341275
2018-09-01 12:22:07 +00:00
Dylan McKay 820553fdb1 [AVR] Fix the testsuite after '%' changed to '$' in MIR
llvm-svn: 324583
2018-02-08 09:17:11 +00:00
Dylan McKay d00f9c1ef1 [AVR] Elaborate LDWRdPtr into `ld r, X++; ld r+1, X`
Patch by Gergo Erdi.

llvm-svn: 314896
2017-10-04 10:33:36 +00:00
Dylan McKay 448c56e2a5 [AVR] Fix test errors due to tied operands not matching
Broken due to r307259.

llvm-svn: 307503
2017-07-09 16:36:35 +00:00
Dylan McKay 8f515b1ef7 [AVR] Support the LDWRdPtr instruction with the same Src+Dst register
llvm-svn: 301313
2017-04-25 15:09:04 +00:00
Matthias Braun f1141285eb MIRTests: Remove unnecessary 2>&1 redirection
llc mir output goes to stdout nowadays, so the 2>&1 is not necessary
anymore for most tests.

llvm-svn: 295859
2017-02-22 18:47:41 +00:00
Dylan McKay 7653d91afa [AVR] Marm MIR test functions as tracking liveness information
This fixes an assertion error that broke three tests.

llvm-svn: 294140
2017-02-05 20:25:34 +00:00
Dylan McKay a7e0548722 [AVR] Explicitly set the target in all CodeGen tests
This seems to have caused failures on the buildbot.

llvm-svn: 289324
2016-12-10 11:23:16 +00:00
Dylan McKay 5c90b8cb4f [AVR] Use the register scavenger when expanding 'LDDW' instructions
Summary: This gets rid of the hardcoded 'r0' that was used previously.

Reviewers: asl

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D27567

llvm-svn: 289322
2016-12-10 10:51:55 +00:00
Dylan McKay 1cdbf42a33 [AVR] Remove a set of redundant tests
This fixes the build.

llvm-svn: 289201
2016-12-09 11:22:26 +00:00
Dylan McKay a5d49dfbb3 [AVR] Add tests for a large number of pseudo instructions
This adds MIR tests for 24 pseudo instructions.

llvm-svn: 289191
2016-12-09 07:49:04 +00:00
Dylan McKay 371117e7a5 [AVR] Add MIR tests for pseudo instruction expansions
This adds tests for 13 pseudo instruction expansions.

llvm-svn: 289039
2016-12-08 10:52:13 +00:00
Dylan McKay 0cc0446ad2 [AVR] Add MIR tests for a few pseudo instructions
llvm-svn: 289031
2016-12-08 08:54:41 +00:00
Dylan McKay 6dbc8d5a0c [AVR] Move a pseudo expansion test into a folder
llvm-svn: 288899
2016-12-07 11:21:45 +00:00