5606dd8a45
Using addPassesToEmitWholeFile is not a good idea here.
...
Use FunctionPassManager to do the job.
llvm-svn: 30160
2006-09-07 21:41:11 +00:00
ce2c1eb154
Add linker into list of LINK_COMPONENTS.
...
llvm-svn: 30159
2006-09-07 21:36:55 +00:00
c465046e65
Throttle back tail duplication to avoid creating really ugly sequences of code.
...
For Transforms/TailDup/if-tail-dup.ll, f.e., it produces:
_foo:
movl 8(%esp), %eax
movl 4(%esp), %ecx
testl $1, %ecx
je LBB1_2 #cond_next
LBB1_1: #cond_true
movl $1, (%eax)
LBB1_2: #cond_next
testl $2, %ecx
je LBB1_4 #cond_next10
LBB1_3: #cond_true6
movl $1, 4(%eax)
LBB1_4: #cond_next10
testl $4, %ecx
je LBB1_6 #cond_next18
LBB1_5: #cond_true14
movl $1, 8(%eax)
LBB1_6: #cond_next18
testl $8, %ecx
je LBB1_8 #return
LBB1_7: #cond_true22
movl $1, 12(%eax)
ret
LBB1_8: #return
ret
instead of:
_foo:
movl 4(%esp), %eax
testl $2, %eax
sete %cl
movl 8(%esp), %edx
testl $1, %eax
je LBB1_2 #cond_next
LBB1_1: #cond_true
movl $1, (%edx)
testb %cl, %cl
jne LBB1_4 #cond_next10
jmp LBB1_3 #cond_true6
LBB1_2: #cond_next
testb %cl, %cl
jne LBB1_4 #cond_next10
LBB1_3: #cond_true6
movl $1, 4(%edx)
testl $4, %eax
je LBB1_6 #cond_next18
jmp LBB1_5 #cond_true14
LBB1_4: #cond_next10
testl $4, %eax
je LBB1_6 #cond_next18
LBB1_5: #cond_true14
movl $1, 8(%edx)
testl $8, %eax
je LBB1_8 #return
jmp LBB1_7 #cond_true22
LBB1_6: #cond_next18
testl $8, %eax
je LBB1_8 #return
LBB1_7: #cond_true22
movl $1, 12(%edx)
ret
LBB1_8: #return
ret
llvm-svn: 30158
2006-09-07 21:30:15 +00:00
dc22b97b9a
new testcase
...
llvm-svn: 30157
2006-09-07 21:29:32 +00:00
dc4ff5311f
Eliminate X86ISD::TEST, using X86ISD::CMP instead. Match X86ISD::CMP patterns
...
using test, which provides nice simplifications like:
- movl %edi, %ecx
- andl $2, %ecx
- cmpl $0, %ecx
+ testl $2, %edi
je LBB1_11 #cond_next90
There are a couple of dagiselemitter deficiencies that this exposes, they will
be handled later.
llvm-svn: 30156
2006-09-07 20:33:45 +00:00
1b7f09cdf7
Some notes on better load folding we could do
...
llvm-svn: 30155
2006-09-07 20:32:01 +00:00
12ee0cbde4
Add lto into the list of PARALLEL_DIRS
...
llvm-svn: 30154
2006-09-07 20:21:58 +00:00
5b3510abd3
Use addPassesToEmitWholeFile() instead of addPassesToEmitFile()
...
llvm-svn: 30153
2006-09-07 20:20:56 +00:00
a9411c0977
Consistency.
...
llvm-svn: 30152
2006-09-07 19:03:48 +00:00
95b3dde8bb
Fix pasto that was breaking x86 tests.
...
llvm-svn: 30151
2006-09-07 18:50:20 +00:00
3b18c1a946
Change DisambiguateGlobalSymbols to not rename asm globals, which breaks
...
bugpoint on leopard.
llvm-svn: 30150
2006-09-07 18:21:07 +00:00
721fc38342
Add new option to leave asm names alone
...
llvm-svn: 30149
2006-09-07 18:20:41 +00:00
f9ed9f60ef
This fails
...
llvm-svn: 30148
2006-09-07 17:43:59 +00:00
aa64b9491f
Warn people not to use GCC 4.1.1.
...
llvm-svn: 30147
2006-09-07 17:34:27 +00:00
c7abe471fe
Make the x86 asm flavor part of the subtarget info.
...
llvm-svn: 30146
2006-09-07 12:23:47 +00:00
f5ce7ef4a8
*** empty log message ***
...
llvm-svn: 30145
2006-09-07 08:39:35 +00:00
d0c0bc502e
Fixed my rotten Engrish grammar.
...
llvm-svn: 30144
2006-09-07 08:36:28 +00:00
4d7ce8a554
cleanups and updates to the GSG, patch by B Scott Michel, thanks!
...
This is PR899
llvm-svn: 30143
2006-09-07 04:19:09 +00:00
707339a57b
Fix CodeGen/Generic/2006-09-06-SwitchLowering.ll, a bug where SDIsel inserted
...
too many phi operands when lowering a switch to branches in some cases.
llvm-svn: 30142
2006-09-07 01:59:34 +00:00
6a7b824ded
New testcase for a switch lowering bug.
...
llvm-svn: 30141
2006-09-07 01:59:05 +00:00
7f3f0973e6
Clean up.
...
llvm-svn: 30140
2006-09-07 01:17:57 +00:00
0b5fb52b0e
testcase, ensure this never breaks.
...
llvm-svn: 30137
2006-09-06 21:54:59 +00:00
4c7a3fbdea
Watch out for variable_ops instructions.
...
llvm-svn: 30135
2006-09-06 20:32:45 +00:00
ac22e54131
Variable ops instructions may ignore the last few operands for code emission.
...
llvm-svn: 30134
2006-09-06 20:24:14 +00:00
483872338a
Document getTargetTriple().
...
llvm-svn: 30133
2006-09-06 20:22:55 +00:00
5561aa7271
Add getTargetTriple() that linker can use to query target architecture.
...
llvm-svn: 30132
2006-09-06 20:16:28 +00:00
ef94ebb666
Oops - forgot to update banner.
...
llvm-svn: 30131
2006-09-06 19:21:41 +00:00
ee9f617cff
Keep track of all modules crated using a name to module map.
...
Add private member function getMoudle().
llvm-svn: 30130
2006-09-06 18:50:26 +00:00
d495bd075a
Cleaned up some of the grammar in the Live Intervals section. Removed the
...
huge honking FIXME comment. I'll address the "Live Intervals Analysis"
section soon.
llvm-svn: 30129
2006-09-06 18:42:41 +00:00
55381e04e6
Update project with new files.
...
llvm-svn: 30128
2006-09-06 18:38:54 +00:00
681ecbb3b3
Separate target specifc asm properties from asm printers.
...
llvm-svn: 30127
2006-09-06 18:35:33 +00:00
a6211dcdad
Separate target specific asm properties from the asm printers.
...
llvm-svn: 30126
2006-09-06 18:34:40 +00:00
abd8bcbe5e
add the orr instruction
...
llvm-svn: 30125
2006-09-06 18:03:12 +00:00
95b7c7af2e
Instead of demangling symbol name by hand, use original name, which was
...
used to mangle symbol name, directly.
llvm-svn: 30124
2006-09-06 00:45:52 +00:00
e3b9490b05
Extract target triplet from optimized module.
...
Untabify.
llvm-svn: 30123
2006-09-06 00:28:22 +00:00
ddfb10b5af
Only call isUse/isDef on register operands
...
llvm-svn: 30122
2006-09-05 20:32:06 +00:00
2656932979
Bugfix to work with the two-addr changes that have been made in the tree recently
...
llvm-svn: 30121
2006-09-05 20:27:32 +00:00
65df0ffadd
make this harder
...
llvm-svn: 30120
2006-09-05 20:27:06 +00:00
6509c248f3
IsDef can only be accessed / set if operand is a register.
...
llvm-svn: 30119
2006-09-05 20:20:04 +00:00
2cb238320d
Only call isUse/isDef on register operands
...
llvm-svn: 30118
2006-09-05 20:19:27 +00:00
45456d44e3
Don't call isDef on non-registers
...
llvm-svn: 30117
2006-09-05 20:02:51 +00:00
fd500a27f2
Initialize IsDef of all non-register MachineOperand to false.
...
llvm-svn: 30116
2006-09-05 18:56:02 +00:00
845b223da4
Fix Duraid's changes to work when TLI is null. This fixes the failing
...
lowerinvoke regtests.
llvm-svn: 30115
2006-09-05 17:48:07 +00:00
0dce3311c4
Change the default to 0, which means 'default'.
...
llvm-svn: 30114
2006-09-05 17:39:15 +00:00
7a150d3113
Fix a few dejagnu failures. e.g. fast-cc-merge-stack-adj.ll
...
llvm-svn: 30113
2006-09-05 08:32:49 +00:00
17c28b2e0e
JIT encoding bug.
...
llvm-svn: 30112
2006-09-05 05:59:25 +00:00
a2d7d1c4fa
Fix JIT encoding of two-addr instructions.
...
llvm-svn: 30111
2006-09-05 03:01:52 +00:00
e3d2e1e41e
Update the X86 JIT to make it work with the new two-addr changes. This also
...
adds assertions that check to make sure every operand gets emitted.
llvm-svn: 30110
2006-09-05 02:52:35 +00:00
af23f9b5f6
Completely eliminate def&use operands. Now a register operand is EITHER a
...
def operand or a use operand.
llvm-svn: 30109
2006-09-05 02:31:13 +00:00
13a5dcddce
Fix a long-standing wart in the code generator: two-address instruction lowering
...
actually *removes* one of the operands, instead of just assigning both operands
the same register. This make reasoning about instructions unnecessarily complex,
because you need to know if you are before or after register allocation to match
up operand #'s with the target description file.
Changing this also gets rid of a bunch of hacky code in various places.
This patch also includes changes to fold loads into cmp/test instructions in
the X86 backend, along with a significant simplification to the X86 spill
folding code.
llvm-svn: 30108
2006-09-05 02:12:02 +00:00
Devang Patel