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23 Commits

Author SHA1 Message Date
Owen Anderson 55f1c09e31 Push LLVMContexts through the IntegerType APIs. 
llvm-svn: 78948
 2009-08-13 21:58:54 +00:00
Evan Cheng cc9ca3500d Shrinkify Thumb2 load / store multiple instructions. 
llvm-svn: 78717
 2009-08-11 21:11:32 +00:00
Jim Grosbach f24f9d9cb6 Whitespace cleanup. Remove trailing whitespace. 
llvm-svn: 78666
 2009-08-11 15:33:49 +00:00
Owen Anderson 53aa7a960c Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type. 
llvm-svn: 78610
 2009-08-10 22:56:29 +00:00
Evan Cheng 12da273f90 tADDrSPI doesn't have a predicate operand, but tADDhirr and tADDi3 have. 
llvm-svn: 77305
 2009-07-28 07:38:35 +00:00
Evan Cheng 780748d565 - More refactoring. This gets rid of all of the getOpcode calls. 
- This change also makes it possible to switch between ARM / Thumb on a
  per-function basis.
- Fixed thumb2 routine which expand reg + arbitrary immediate. It was using
  using ARM so_imm logic.
- Use movw and movt to do reg + imm when profitable.
- Other code clean ups and minor optimizations.

llvm-svn: 77300
 2009-07-28 05:48:47 +00:00
Evan Cheng faede73a32 Rename tMOVhi2lor to tMOVgpr2tgpr. It's not moving from a high register to a low register. It's moving from a GPR register class to a more restrictive tGPR class. Also change tMOVlor2hir, and tMOVhir2hir. 
llvm-svn: 77172
 2009-07-26 23:59:01 +00:00
Evan Cheng 8953720f23 Refactor. Get rid of a few more getOpcode() calls. 
llvm-svn: 77164
 2009-07-26 18:55:14 +00:00
Owen Anderson edb4a70325 Revert the ConstantInt constructors back to their 2.5 forms where possible, thanks to contexts-on-types. More to come. 
llvm-svn: 77011
 2009-07-24 23:12:02 +00:00
David Goodwin cdd405d804 Correctly handle the Thumb-2 imm8 addrmode. Specialize frame index elimination more exactly for Thumb-2 to get better code gen. 
llvm-svn: 76919
 2009-07-24 00:16:18 +00:00
Owen Anderson 47db941fd3 Get rid of the Pass+Context magic. 
llvm-svn: 76702
 2009-07-22 00:24:57 +00:00
Evan Cheng fa60698c29 Fix PR4567. Thumb1 target was using the wrong instruction to handle sp = sub fp, #c. 
llvm-svn: 76401
 2009-07-20 06:59:32 +00:00
Evan Cheng 151b23d043 Fix a regression from 76124. Thumb1 instructions default to S bit being true. 
llvm-svn: 76374
 2009-07-19 19:16:46 +00:00
Anton Korobeynikov c5df7e2dc1 Emit cross regclass register moves for thumb2. 
Minor code duplication cleanup.

llvm-svn: 76124
 2009-07-16 23:26:06 +00:00
Evan Cheng 84517443ca Let callers decide the sub-register index on the def operand of rematerialized instructions. 
Avoid remat'ing instructions whose def have sub-register indices for now. It's just really really hard to get all the cases right.

llvm-svn: 75900
 2009-07-16 09:20:10 +00:00
Owen Anderson b6b2530000 Move EVER MORE stuff over to LLVMContext. 
llvm-svn: 75703
 2009-07-14 23:09:55 +00:00
Torok Edwin fbcc663cbf llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable. 
This adds location info for all llvm_unreachable calls (which is a macro now) in
!NDEBUG builds.
In NDEBUG builds location info and the message is off (it only prints
"UREACHABLE executed").

llvm-svn: 75640
 2009-07-14 16:55:14 +00:00
Evan Cheng cd4cdd1157 Major changes to Thumb (not Thumb2). Many 16-bit instructions either modifies CPSR when they are outside the IT blocks, or they can predicated when in Thumb2. Move the implicit def of CPSR to an optional def which defaults CPSR. This allows the 's' bit to be toggled dynamically. 
A side-effect of this change is asm printer is now using unified assembly. There are some minor clean ups and fixes as well.

llvm-svn: 75359
 2009-07-11 06:43:01 +00:00
Torok Edwin fb8d6d5b58 Implement changes from Chris's feedback. 
Finish converting lib/Target.

llvm-svn: 75043
 2009-07-08 20:53:28 +00:00
David Goodwin 03ab0bbb24 Generalize opcode selection in ARMBaseRegisterInfo. 
llvm-svn: 75036
 2009-07-08 20:28:28 +00:00
David Goodwin 9ca33e8a9f Push methods into base class in preparation for sharing. 
llvm-svn: 75020
 2009-07-08 18:31:39 +00:00
Torok Edwin 6dd2730024 Start converting to new error handling API. 
cerr+abort -> llvm_report_error
assert(0)+abort -> LLVM_UNREACHABLE (assert(0)+llvm_unreachable-> abort() included)

llvm-svn: 75018
 2009-07-08 18:01:40 +00:00
David Goodwin ade05a37f1 Checkpoint refactoring of ThumbInstrInfo and ThumbRegisterInfo into Thumb1InstrInfo, Thumb2InstrInfo, Thumb1RegisterInfo and Thumb2RegisterInfo. Move methods from ARMInstrInfo to ARMBaseInstrInfo to prepare for sharing with Thumb2. 
llvm-svn: 74731
 2009-07-02 22:18:33 +00:00