llvm-project

Commit Graph

Author	SHA1	Message	Date
Puyan Lotfi	43e94b15ea	Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922	2018-01-31 22:04:26 +00:00
Matt Arsenault	60b91e0ba2	AMDGPU: Remove unnecessary IR from MIR tests llvm-svn: 307311	2017-07-06 20:56:57 +00:00
Mark Searles	11d0a04050	[AMDGPU] Fix bugs in new waitcnt pass. Add test. - new waitcnt pass remains off by default; -enable-si-insert-waitcnts=1 to enable it - fix handling of PERMUTE ops - fix insertion of waitcnt instrs at function begin/end ( port of analogous code that was added to old waitcnt pass ) - add new test Differential Revision: https://reviews.llvm.org/D33114 llvm-svn: 304311	2017-05-31 16:44:23 +00:00

Author

SHA1

Message

Date

Puyan Lotfi

43e94b15ea

Followup on Proposal to move MIR physical register namespace to '$' sigil.

Discussed here:

http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html

In preparation for adding support for named vregs we are changing the sigil for
physical registers in MIR to '$' from '%'. This will prevent name clashes of
named physical register with named vregs.

llvm-svn: 323922

2018-01-31 22:04:26 +00:00

Matt Arsenault

60b91e0ba2

AMDGPU: Remove unnecessary IR from MIR tests

llvm-svn: 307311

2017-07-06 20:56:57 +00:00

Mark Searles

11d0a04050

[AMDGPU] Fix bugs in new waitcnt pass. Add test.

- new waitcnt pass remains off by default; -enable-si-insert-waitcnts=1 to enable it
- fix handling of PERMUTE ops
- fix insertion of waitcnt instrs at function begin/end ( port of analogous code that was added to old waitcnt pass )
- add new test

  Differential Revision: https://reviews.llvm.org/D33114

llvm-svn: 304311

2017-05-31 16:44:23 +00:00

3 Commits