71928e681b
Add disassembler to MIPS.
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Patch by Vladimir Medic.
llvm-svn: 154935
2012-04-17 18:03:21 +00:00
55059262aa
Revert r153924. There were buildbot failures.
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llvm-svn: 153925
2012-04-03 02:51:09 +00:00
e2498d014b
MIPS disassembler support.
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Patch by Vladimir Medic.
llvm-svn: 153924
2012-04-03 02:20:58 +00:00
b1f68f9696
Initial 64 bit direct object support.
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This patch allows llvm to recognize that a 64 bit object file is being produced
and that the subsequently generated ELF header has the correct information.
The test case checks for both big and little endian flavors.
Patch by Jack Carter.
llvm-svn: 153889
2012-04-02 19:25:22 +00:00
54bfde79db
Make MCInstrInfo available to the MCInstPrinter. This will be used to remove getInstructionName and the static data it contains since the same tables are already in MCInstrInfo.
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llvm-svn: 153860
2012-04-02 06:09:36 +00:00
8f4e3a0088
Select static relocation model if it is jitting.
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llvm-svn: 153795
2012-03-31 02:38:36 +00:00
fd93a59557
Make MCRegisterInfo available to the the MCInstPrinter.
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Used to allow context sensitive printing of super-register or sub-register
references.
llvm-svn: 152043
2012-03-05 19:33:20 +00:00
1ee768db53
Pass endian information to constructors. Define separate functions to create
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objects for big endian and little endian targets.
Patch by Jack Carter.
llvm-svn: 151788
2012-03-01 01:53:15 +00:00
9f6101191b
remove Emacs-tag form .cpp files in Mips Backend, and fix some typo.
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llvm-svn: 150805
2012-02-17 08:55:11 +00:00
c4965bce14
Convert assert(0) to llvm_unreachable
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llvm-svn: 149814
2012-02-05 07:21:30 +00:00
647841b181
Add big endian mips support. Based on a patch by Jack Carter.
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llvm-svn: 147924
2012-01-11 04:04:14 +00:00
9e1d369e3c
Tidy up. Simplify logic. No functional change intended.
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llvm-svn: 146896
2011-12-19 19:52:25 +00:00
ecb2908bf9
Sink codegen optimization level into MCCodeGenInfo along side relocation model
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and code model. This eliminates the need to pass OptLevel flag all over the
place and makes it possible for any codegen pass to use this information.
llvm-svn: 144788
2011-11-16 08:38:26 +00:00
c85e3ff334
Mips MC object code emission improvements:
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"With this patch we can now generate runnable Mips code through LLVM
direct object emission. We have run numerous simple programs, both C
and C++ and with -O0 and -O3 from the output. The code is not production
ready, but quite useful for experimentation." Patch and message by
Jack Carter
llvm-svn: 144414
2011-11-11 22:58:42 +00:00
ee09394644
Register the MC object streamer.
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Patch by Reed Kotler at Mips Technologies.
llvm-svn: 140887
2011-09-30 21:29:38 +00:00
44220ca045
Register Asm backend. Add functions to MipsAsmBackend.
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Patch by Reed Kotler at Mips Technologies.
llvm-svn: 140886
2011-09-30 21:23:45 +00:00
750ecec7d5
Initial implementation of MipsMCCodeEmitter.
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Patch by Reed Kotler at Mips Technologies.
llvm-svn: 140878
2011-09-30 20:40:03 +00:00
3d673cc323
Add a base class for Mips TargetMachines and add Mips64 TargetMachines.
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llvm-svn: 140233
2011-09-21 03:00:58 +00:00
b491f48aba
Support for PSP is gone too.
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llvm-svn: 139622
2011-09-13 18:55:33 +00:00
b0e99ef8f0
It is not necessary to search for mipsallegrex in target triple string.
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llvm-svn: 139607
2011-09-13 17:35:28 +00:00
4c493e8050
Refactor instprinter and mcdisassembler to take a SubtargetInfo. Add -mattr= handling to llvm-mc. Reviewed by Owen Anderson.
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llvm-svn: 139237
2011-09-07 17:24:38 +00:00
2bb4035707
Move TargetRegistry and TargetSelect from Target to Support where they belong.
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These are strictly utilities for registering targets and components.
llvm-svn: 138450
2011-08-24 18:08:43 +00:00
4d6c9d711d
Some refactoring so TargetRegistry.h no longer has to include any files
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from MC.
llvm-svn: 138367
2011-08-23 20:15:21 +00:00
61faa55b74
Separate MCInstPrinter registration from AsmPrinter registration.
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llvm-svn: 135974
2011-07-25 21:20:24 +00:00
6376593ed1
createXXXMCCodeGenInfo should be static.
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llvm-svn: 135826
2011-07-23 00:01:04 +00:00
8c886a40d2
Combine all MC initialization routines into one. e.g. InitializeX86MCAsmInfo,
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InitializeX86MCInstrInfo, etc. are combined into InitializeX86TargetMC.
llvm-svn: 135812
2011-07-22 21:58:54 +00:00
efd9b4240f
- Move CodeModel from a TargetMachine global option to MCCodeGenInfo.
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- Introduce JITDefault code model. This tells targets to set different default
code model for JIT. This eliminates the ugly hack in TargetMachine where
code model is changed after construction.
llvm-svn: 135580
2011-07-20 07:51:56 +00:00
2129f59637
Introduce MCCodeGenInfo, which keeps information that can affect codegen
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(including compilation, assembly). Move relocation model Reloc::Model from
TargetMachine to MCCodeGenInfo so it's accessible even without TargetMachine.
llvm-svn: 135468
2011-07-19 06:37:02 +00:00
67c033e6b8
Move getInitialFrameState from TargetFrameInfo to MCAsmInfo (suggestions for
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better location welcome).
llvm-svn: 135438
2011-07-18 22:29:13 +00:00
d60fa58ba1
Sink getDwarfRegNum, getLLVMRegNum, getSEHRegNum from TargetRegisterInfo down
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to MCRegisterInfo. Also initialize the mapping at construction time.
This patch eliminate TargetRegisterInfo from TargetAsmInfo. It's another step
towards fixing the layering violation.
llvm-svn: 135424
2011-07-18 20:57:22 +00:00
1705ab00ab
Rename createAsmInfo to createMCAsmInfo and move registration code to MCTargetDesc to prepare for next round of changes.
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llvm-svn: 135219
2011-07-14 23:50:31 +00:00
bc153d49b7
Next round of MC refactoring. This patch factor MC table instantiations, MC
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registeration and creation code into XXXMCDesc libraries.
llvm-svn: 135184
2011-07-14 20:59:42 +00:00
Akira Hatanaka