Commit Graph

203025 Commits

Author SHA1 Message Date
Matt Arsenault 91f90e694f SLSR: Pass address space to isLegalAddressingMode
This only updates one of the uses. The other is used in cases
that may never touch memory, so I'm not sure why this is even
calling it. Perhaps there should be a new, similar hook for such
cases or pass -1 for unknown address space.

llvm-svn: 239540
2015-06-11 16:13:39 +00:00
Matt Arsenault e23a063dc3 Fix merges of non-zero vector stores
Now actually stores the non-zero constant instead of 0.
I somehow forgot to include this part of r238108.

The test change was just an independent instruction order swap,
so just add another check line to satisfy CHECK-NEXT.

llvm-svn: 239539
2015-06-11 16:03:52 +00:00
Daniel Sanders ed64d62c70 Replace string GNU Triples with llvm::Triple in computeDataLayout(). NFC.
Summary:
This continues the patch series to eliminate StringRef forms of GNU triples
from the internals of LLVM that began in r239036.

Reviewers: rengolin

Reviewed By: rengolin

Subscribers: llvm-commits, jfb, rengolin

Differential Revision: http://reviews.llvm.org/D10361

llvm-svn: 239538
2015-06-11 15:34:59 +00:00
Douglas Katzman fd5286717c Add comments to PrintActions1 and Driver::PrintActions.
Differential Revision: http://reviews.llvm.org/D10214

llvm-svn: 239537
2015-06-11 15:05:22 +00:00
Sanjay Patel 2987c29a1e add the -mrecip driver flag and process its options (3rd try)
The 1st and 2nd tries to land this (r238055, r238851) were reverted due to
bot failures caused by the LLVM part of the patch. That was hopefully fixed 
after r239001.

This is the front-end counterpart to D8982.

The -mrecip option interface is based on maintaining compatibility with gcc:
https://gcc.gnu.org/onlinedocs/gcc-4.9.2/gcc/i386-and-x86-64-Options.html#index-mrecip_003dopt-1627
https://gcc.gnu.org/onlinedocs/gcc-4.9.2/gcc/RS_002f6000-and-PowerPC-Options.html#index-mrecip-2289

...while adding more functionality (allowing users to specify the number of refinement steps for each
estimate type).

Differential Revision: http://reviews.llvm.org/D8989

llvm-svn: 239536
2015-06-11 14:53:41 +00:00
Tom Stellard 076ac95e79 R600/SI: Define latency for flat instructions
llvm-svn: 239535
2015-06-11 14:51:50 +00:00
Tom Stellard 731c927839 R600/SI: Move flat instruction defs to CIInstructions.td
llvm-svn: 239534
2015-06-11 14:51:49 +00:00
Tom Stellard 53e015f37d R600/SI: Add -mcpu=bonaire to a test that uses flat address space
Flat instructions don't exist on SI, but there is a bug in the backend that
allows them to be selected.

llvm-svn: 239533
2015-06-11 14:51:46 +00:00
Sanjay Patel 8b2150efdb remove function names from comments; NFC
llvm-svn: 239532
2015-06-11 14:26:49 +00:00
Daniel Jasper 20580fd5d3 clang-format: Make SFS_Inline imply SFS_Empty.
In the long run, these two might be independent or we might to only
allow specific combinations. Until we have a corresponding request,
however, it is hard to do the right thing and choose the right
configuration options. Thus, just don't touch the options yet and
just modify the behavior slightly.

llvm-svn: 239531
2015-06-11 13:31:45 +00:00
Daniel Jasper 56691b8cb9 clang-format: [JS] Ensure that formatting actually takes place in tests.
And fix formatting issue discovered by that :-).

llvm-svn: 239530
2015-06-11 13:29:20 +00:00
Aaron Ballman b6b58b3152 Fixing MSVC 2013 build error.
llvm-svn: 239529
2015-06-11 13:06:02 +00:00
Yaron Keren b54db52a7b C++11 rangify several loops.
llvm-svn: 239528
2015-06-11 12:33:25 +00:00
Gabor Ballabas cebcb3b52f Allow case-insensitive values for -march for ARM in line with GCC.
GCC allows case-insensitive values for -mcpu, -march and -mtune options.
This patch implements the same behaviour for the -march option for ARM.

llvm-svn: 239527
2015-06-11 12:29:56 +00:00
Daniel Marjamaki 647e61244b Token: complement is() method with isOneOf() to allow easier usage
llvm-svn: 239526
2015-06-11 12:28:14 +00:00
Toma Tabacu b36d610cc2 [mips] Pass on -m{single,double}-float to GAS.
Summary: We already pass these to the IAS, but not to GAS.

Reviewers: dsanders, atanasyan

Reviewed By: atanasyan

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10358

llvm-svn: 239525
2015-06-11 12:13:18 +00:00
Alexey Bataev 6e8248fdad [OPENMP] Fox for http://llvm.org/PR23663: OpenMP crash
Destroy RuntimeCleanupScope before generation of termination instruction in parallel loop precondition.

llvm-svn: 239524
2015-06-11 10:53:56 +00:00
Toma Tabacu e1e460dbc5 Recommit "[mips] [IAS] Add support for BNE and BEQ with an immediate operand." (r239396).
Apparently, Arcanist didn't include some of my local changes in my previous
commit attempt.

llvm-svn: 239523
2015-06-11 10:36:10 +00:00
Zoran Jovanovic cdfcbe41f2 [mips][microMIPS] Implement ERET and ERETNC instructions
http://reviews.llvm.org/D10091

llvm-svn: 239522
2015-06-11 10:22:46 +00:00
Manuel Klimek f0c95b32ec Fix crash in clang-format.
The following example used to crash clang-format.
 #define a\
  /**/}

Adjusting the indentation level cache for the line starting with the
comment would lead to an out-of-bounds array read.

llvm-svn: 239521
2015-06-11 10:14:13 +00:00
Zoran Jovanovic 6b0dcd7b8c [mips] Change existing uimm10 operand to restrict the accepted immediates
http://reviews.llvm.org/D10312

llvm-svn: 239520
2015-06-11 09:51:58 +00:00
Zoran Jovanovic fcecf26092 [mips][microMIPSr6] Change disassembler tests to one line format
llvm-svn: 239519
2015-06-11 09:42:10 +00:00
Hao Liu 405f1d1651 [LoopVectorize] Revert the enabling of interleaved memory access in Loop Vectorizor, which was wrongly committed in r239514.
llvm-svn: 239515
2015-06-11 09:18:07 +00:00
Hao Liu 4566d18e89 [AArch64] Match interleaved memory accesses into ldN/stN instructions.
Add a pass AArch64InterleavedAccess to identify and match interleaved memory accesses. This pass transforms an interleaved load/store into ldN/stN intrinsic. As Loop Vectorizor disables optimization on interleaved accesses by default, this optimization is also disabled by default. To enable it by "-aarch64-interleaved-access-opt=true"

E.g. Transform an interleaved load (Factor = 2):
       %wide.vec = load <8 x i32>, <8 x i32>* %ptr
       %v0 = shuffle %wide.vec, undef, <0, 2, 4, 6>  ; Extract even elements
       %v1 = shuffle %wide.vec, undef, <1, 3, 5, 7>  ; Extract odd elements
     Into:
       %ld2 = { <4 x i32>, <4 x i32> } call aarch64.neon.ld2(%ptr)
       %v0 = extractelement { <4 x i32>, <4 x i32> } %ld2, i32 0
       %v1 = extractelement { <4 x i32>, <4 x i32> } %ld2, i32 1

E.g. Transform an interleaved store (Factor = 2):
       %i.vec = shuffle %v0, %v1, <0, 4, 1, 5, 2, 6, 3, 7>  ; Interleaved vec
       store <8 x i32> %i.vec, <8 x i32>* %ptr
     Into:
       %v0 = shuffle %i.vec, undef, <0, 1, 2, 3>
       %v1 = shuffle %i.vec, undef, <4, 5, 6, 7>
       call void aarch64.neon.st2(%v0, %v1, %ptr)

llvm-svn: 239514
2015-06-11 09:05:02 +00:00
Daniel Jasper 229628b39e clang-format: Don't add spaces in foreach macro definition.
Before clang-format would e.g. add a space into

   #define Q_FOREACH(x, y)

which turns this into a non-function-like macro.

Patch by Strager Neds, thank you!

llvm-svn: 239513
2015-06-11 08:38:19 +00:00
David Majnemer e0e228a380 Reinstate r239499 and r239503
They were reverted because the FileCheck patterns didn't match on
release builds.

llvm-svn: 239512
2015-06-11 08:12:44 +00:00
Manuel Klimek aad3b8486d Revert "[MS ABI] Allow fastcall member function pointers to get CodeGen'd"
Revert "[MS ABI] Allow memfn pointers with unconvertible types to be formed"

This reverts r239499 and r239503; the former breaks tests [1] and the
latter is based on the former.

[1]
http://lab.llvm.org:8080/green/job/clang-stage2-configure-Rlto_check/4473/testReport/Clang/CodeGenCXX/microsoft_abi_virtual_member_pointers_cpp/

llvm-svn: 239511
2015-06-11 07:54:35 +00:00
Arnaud A. de Grandmaison af37ad19a9 [LiveVariables] Improve isLiveOut runtime performances. NFC.
On large goto table based interpreters, where phi nodes can have (very) large
fan-ins, isLiveOut exhibited poor performances: about 40% of the full
codegen time was spent in PHIElim, sorting MachineBasicBlock addresses.

This patch improve the performances for such cases, and does not show
compile time regressions on the LNT, at bootstrap (llvm+clang+lldb) or
any other benchmarks we have in-house.

llvm-svn: 239510
2015-06-11 07:50:21 +00:00
Simon Pilgrim 5965680d53 [X86][SSE] Vectorized i8 and i16 shift operators
This patch ensures that SHL/SRL/SRA shifts for i8 and i16 vectors avoid scalarization. It builds on the existing i8 SHL vectorized implementation of moving the shift bits up to the sign bit position and separating the 4, 2 & 1 bit shifts with several improvements:

1 - SSE41 targets can use (v)pblendvb directly with the sign bit instead of performing a comparison to feed into a VSELECT node.
2 - pre-SSE41 targets were masking + comparing with an 0x80 constant - we avoid this by using the fact that a set sign bit means a negative integer which can be compared against zero to then feed into VSELECT, avoiding the need for a constant mask (zero generation is much cheaper).
3 - SRA i8 needs to be unpacked to the upper byte of a i16 so that the i16 psraw instruction can be correctly used for sign extension - we have to do more work than for SHL/SRL but perf tests indicate that this is still beneficial.

The i16 implementation is similar but simpler than for i8 - we have to do 8, 4, 2 & 1 bit shifts but less shift masking is involved. SSE41 use of (v)pblendvb requires that the i16 shift amount is splatted to both bytes however.

Tested on SSE2, SSE41 and AVX machines.

Differential Revision: http://reviews.llvm.org/D9474

llvm-svn: 239509
2015-06-11 07:46:37 +00:00
Arnaud A. de Grandmaison 2e8ffa3b44 [PHIElim] Use ranges and const-ify, NFC.
llvm-svn: 239508
2015-06-11 07:45:05 +00:00
Nemanja Ivanovic b17f1129fa Clang support for vector quad bit permute and gather instructions through builtins
This patch corresponds to review:
http://reviews.llvm.org/D10095

This is for just two instructions and related builtins:
vbpermq
vgbbd

llvm-svn: 239506
2015-06-11 06:25:36 +00:00
Nemanja Ivanovic ea1db8a697 LLVM support for vector quad bit permute and gather instructions through builtins
This patch corresponds to review:
http://reviews.llvm.org/D10096

This is the back end portion of the patch related to D10095.
The patch adds the instructions and back end intrinsics for:
vbpermq
vgbbd

llvm-svn: 239505
2015-06-11 06:21:25 +00:00
Richard Smith 00be6d0ff8 [modules] Fix a few places where merging wasn't performed if modules was disabled but local module visibilty was enabled.
llvm-svn: 239504
2015-06-11 03:05:39 +00:00
David Majnemer 9321f926b0 [MS Compatibility] Handle cleanups we create for a ctor closure
This fixes PR23801.

llvm-svn: 239503
2015-06-11 02:38:06 +00:00
Reid Kleckner c35e7f52ba Revert "Move dllimport name mangling to IR mangler."
This reverts commit r239437.

This broke clang-cl self-hosts. We'd end up calling the __imp_ symbol
directly instead of using it to do an indirect function call.

llvm-svn: 239502
2015-06-11 01:31:48 +00:00
Pete Cooper 7cbe58d3c5 Remove MachineModuleInfo::UsedFunctions as it has no users.
It hasn't been used since r130964.

This also removes MachineModuleInfo::isUsedFunction and
MachineModuleInfo::AnalyzeModule, both of which were only
there to support UsedFunctions.

llvm-svn: 239501
2015-06-11 01:04:56 +00:00
David Majnemer ac936ff5ab [MS ABI] Allow fastcall member function pointers to get CodeGen'd
This restriction appears unnecessary and most likely came about during
early work for musttail.

llvm-svn: 239500
2015-06-11 00:45:44 +00:00
David Majnemer 01b9bb42d4 [MS ABI] Allow memfn pointers with unconvertible types to be formed
Remove the restriction which forbade forming pointers to member
functions which had parameter types or return types which were not
convertible.

llvm-svn: 239499
2015-06-11 00:20:57 +00:00
Chris Bieneman 6bd006f31a [CMake] Cleanup add_compiler_rt_object_library to be platform-agnostic
Summary:
This change takes darwin-specific goop that was scattered around CMakeLists files and spread between add_compiler_rt_object_library and add_compiler_rt_darwin_object_library and moves it all under add_compiler_rt_object_library.

The goal of this is to try to push platform handling as low in the utility functions as possible.

Reviewers: rnk, samsonov

Reviewed By: rnk, samsonov

Subscribers: rnk, rsmith, llvm-commits

Differential Revision: http://reviews.llvm.org/D10250

llvm-svn: 239498
2015-06-10 23:55:07 +00:00
Sanjay Patel 1275a3c913 change assert that will never fire to llvm_unreachable
llvm-svn: 239497
2015-06-10 23:27:33 +00:00
Alexei Starovoitov f657ca8d78 [bpf] add support for BPF backend
add support for bpfel/bpfeb targets

llvm-svn: 239496
2015-06-10 22:59:13 +00:00
Jingyue Wu f6ca8cfdcc [NFC] added a missing space
llvm-svn: 239495
2015-06-10 22:54:02 +00:00
Richard Smith ae7c04f065 Work around MSVC miscompilation.
llvm-svn: 239494
2015-06-10 22:49:14 +00:00
Pete Cooper 3fc3040860 Stop returning a Use* from allocHungOffUses.
This always just set the User::OperandList which is now set
in that method instead of being returned.

Reviewed by Duncan Exon Smith.

llvm-svn: 239493
2015-06-10 22:38:46 +00:00
Pete Cooper 93f9ff5781 Add User::growHungoffUses and use it to grow the hung off uses. NFC.
PhiNode, SwitchInst, LandingPad and IndirectBr all had virtually identical
logic for growing the hung off uses.
Move it to User so that they can all call a single shared implementation.

Their destructors were all empty after this change and were deleted.  They all
have virtual clone_impl methods which can be used as vtable anchors.

Reviewed by Duncan Exon Smith.

llvm-svn: 239492
2015-06-10 22:38:41 +00:00
Pete Cooper 178dcc2938 Delete User::dropHungOffUses and move it in to ~User which is the only caller. NFC.
Now that the subclasses which care about hung off uses let ~User clean it up,
there's no need for a separate method.  Just inline it to ~User and delete it.

Reviewed by Duncan Exon Smith.

llvm-svn: 239491
2015-06-10 22:38:38 +00:00
Pete Cooper c6c0439d2a Make User track whether a class has 'hung off uses' and delete them in its destructor.
Currently all of the logic for deleting hung off uses, which PHI/switch/etc use,
is in their classes.

This adds a bit to Value which tracks whether that user had hung off uses,
then User can be responsible for clearing them instead of the sub classes.

Note, the bit used here was taken from NumOperands which was 30-bits.
Given the reduction to 29 bits, and the average User being just over 100 bytes,
a single User with 29-bits of num operands would need 50GB of RAM for itself
so its reasonable to assume that 29-bits is enough for now.

This is a step towards hiding all the hung off uses logic in the User.

Reviewed by Duncan Exon Smith.

llvm-svn: 239490
2015-06-10 22:38:34 +00:00
Pete Cooper 87b925b064 Move the special Phi logic for hung off uses in to User::allocHungOffUses. NFC.
PhiNode's need to allocate space for an array of Use[N] and then BasicBlock*[N].

They had their own allocHungOffUses to handle all of this.  This moves the logic
in to User::allocHungOffUses and PhiNode passes in a bool to say to allocate
the BB* space too.

Reviewed by Duncan Exon Smith.

llvm-svn: 239489
2015-06-10 22:38:30 +00:00
Peter Collingbourne 115fe37621 ArgumentPromotion: Drop sret attribute on functions that are only called directly.
If the first argument to a function is a 'this' argument and the second
has the sret attribute, the ArgumentPromotion pass may promote the 'this'
argument to more than one argument, violating the IR constraint that 'sret'
may only be applied to the first or second argument.

Although this IR constraint is arguably unnecessary, it highlighted the fact
that ArgPromotion does not need to preserve this attribute. Dropping the
attribute reduces register pressure in the backend by avoiding the register
copy required by sret. Because sret implies noalias, we also replace the
former with the latter.

Differential Revision: http://reviews.llvm.org/D10353

llvm-svn: 239488
2015-06-10 21:14:34 +00:00
Richard Smith 95d83959d8 [modules] Don't allow use of non-visible (inherited) default template arguments.
llvm-svn: 239487
2015-06-10 20:36:34 +00:00