4fb38d3cd3
Reimplement (part of) the or -> add optimization. Matching 'or' into 'add'
...
is general goodness because it allows ORs to be converted to LEA to avoid
inserting copies. However, this is bad because it makes the generated .s
file less obvious and gives valgrind heartburn (tons of false positives in
bitfield code).
While the general fix should be in valgrind, we can at least try to avoid
emitting ADD instructions that *don't* get promoted to LEA. This is more
work because it requires introducing pseudo instructions to represents
"add that knows the bits are disjoint", but hey, people really love valgrind.
This fixes this testcase:
https://bugs.kde.org/show_bug.cgi?id=242137#c20
the add r/i cases are coming next.
llvm-svn: 116007
2010-10-07 23:36:18 +00:00
0f1677e190
After splitting, the remaining LiveInterval may be fragmented into multiple
...
connected components. These components should be allocated different virtual
registers because there is no reason for them to be allocated together.
Add the ConnectedVNInfoEqClasses class to calculate the connected components,
and move values to new LiveIntervals.
Use it from SplitKit::rewrite by creating new virtual registers for the
components.
llvm-svn: 116006
2010-10-07 23:34:34 +00:00
a7b68d6d95
Fix LSR to keep the RegUseTracker up to date when combining users.
...
This doesn't usually matter, because the other heuristics usually
succeed regardless, but it's good to keep the register use
bookkeeping consistent.
llvm-svn: 116005
2010-10-07 23:33:43 +00:00
57da4caa85
Remove LoopIndexSplit pass. It is neither maintained nor used by anyone.
...
llvm-svn: 116004
2010-10-07 23:29:37 +00:00
f41f11c37e
Unbreak cmake build.
...
llvm-svn: 116003
2010-10-07 23:12:15 +00:00
412e37bd34
Code refactoring.
...
llvm-svn: 116002
2010-10-07 23:12:15 +00:00
1c090c00bc
Reduce casting in various tables by defining the table
...
with the right types.
llvm-svn: 116001
2010-10-07 23:08:41 +00:00
abe8c130b1
Warn about broken GCCs on ARM due to the problem fixed:
...
http://gcc.gnu.org/ml/gcc-patches/2010-09/msg01070.html
llvm-svn: 115998
2010-10-07 22:30:47 +00:00
70a7b54f97
simplify code: don't build up vector only to assert it is empty.
...
llvm-svn: 115997
2010-10-07 22:26:19 +00:00
df7a4f2515
Now with fewer extraneous semicolons!
...
llvm-svn: 115996
2010-10-07 22:25:06 +00:00
33c1eb16e8
Move checking for t2MOVCCi16 to the right place.
...
llvm-svn: 115994
2010-10-07 22:14:01 +00:00
91029094e0
Trivial MC code emitter shell. No instruction forms actually handled yet.
...
llvm-svn: 115993
2010-10-07 22:12:50 +00:00
139edad73a
Correctly check if a path is a directory. Fix by Brian Korver.
...
llvm-svn: 115991
2010-10-07 22:05:57 +00:00
3a24f9230a
Provie a clearner interface so that FE can decide whether a function has prototype or not.
...
llvm-svn: 115988
2010-10-07 22:03:01 +00:00
8aed386d82
Include the auto-generated bits for machine encoding.
...
llvm-svn: 115987
2010-10-07 21:57:55 +00:00
1e00173d20
Fix typo in comment.
...
llvm-svn: 115986
2010-10-07 21:55:16 +00:00
3e1e447ca2
Remember to promote load/store types for stack to register size.
...
llvm-svn: 115984
2010-10-07 21:40:18 +00:00
f5c60d8156
convert test to use the existing classes that the multipatterns
...
use. Since TEST is completely different than all other binops,
don't define a multipattern for it.
This completes factorization of binops.
llvm-svn: 115982
2010-10-07 21:31:03 +00:00
ae8d67d3bb
convert cmp to use a multipattern
...
llvm-svn: 115978
2010-10-07 20:56:25 +00:00
5c31bf0619
Canonicalize X86ISD::MOVDDUP nodes to v2f64 to make sure all cases match. Also eliminate unneeded isel patterns. rdar://8520311
...
llvm-svn: 115977
2010-10-07 20:50:20 +00:00
a6769bb993
This file needs ToolOutputFile.h too.
...
llvm-svn: 115976
2010-10-07 20:48:46 +00:00
07b5b1802e
ARM instruction don't have instruction prefixes, so remove the helper functions
...
for them from the MCCodeEmitter.
llvm-svn: 115975
2010-10-07 20:41:30 +00:00
ba05c68ce3
Add output stream operator for MCInst.
...
llvm-svn: 115974
2010-10-07 20:38:37 +00:00
0df7ea4c24
Move tool_output_file into its own file.
...
llvm-svn: 115973
2010-10-07 20:32:40 +00:00
9786868939
Add initialization routines for Instrumentation.
...
llvm-svn: 115971
2010-10-07 20:17:24 +00:00
a8c0bbb869
reduce redundancy between pattern copies.
...
llvm-svn: 115968
2010-10-07 20:14:23 +00:00
9fece2bea2
the opcode for BinOpMI/BinOpMI8 is always the same, remove the argument.
...
llvm-svn: 115967
2010-10-07 20:06:24 +00:00
546c11c72f
Improve comment.
...
llvm-svn: 115966
2010-10-07 20:05:18 +00:00
f7ef5dfccc
Add initialization routines to InstCombine.
...
llvm-svn: 115965
2010-10-07 20:04:55 +00:00
752b60bc01
convert adc/sbb to a multipattern. Because the adde/sube nodes
...
are not defined as returning EFLAGS (like add_flag and friends),
the entire multipattern and several of the subclasses need to be
cloned.
This could be handled through better instantiation support in tblgen,
but it isn't meta enough.
llvm-svn: 115964
2010-10-07 20:01:55 +00:00
44621e4306
Add initialization routines for VMCore.
...
llvm-svn: 115963
2010-10-07 19:51:21 +00:00
7713f26045
Fix Whitespace.
...
llvm-svn: 115959
2010-10-07 18:51:10 +00:00
d12e9d38b4
Fix warnings on Windows.
...
llvm-svn: 115958
2010-10-07 18:50:57 +00:00
e9d5d0736c
Add initialization routines for Target.
...
llvm-svn: 115957
2010-10-07 18:50:11 +00:00
c6a6e9ba7c
Fix obvious mistake pointed out by Michael Spencer.
...
llvm-svn: 115952
2010-10-07 18:47:10 +00:00
9bfd9679f9
Print more loop info.
...
llvm-svn: 115951
2010-10-07 18:47:07 +00:00
7c31730053
Print out MBB number when rewriting.
...
llvm-svn: 115950
2010-10-07 18:47:05 +00:00
80fc0762f3
Add initialization routines for CodeGen.
...
llvm-svn: 115949
2010-10-07 18:41:20 +00:00
98eb3ec6c5
Add an implementation of the initialization routine for IPA.
...
llvm-svn: 115947
2010-10-07 18:31:27 +00:00
6875c2ea26
Add initialization routines for Analysis and IPA.
...
llvm-svn: 115946
2010-10-07 18:31:00 +00:00
d4b62765a7
gtest: Fix warnings on MinGW.
...
llvm-svn: 115945
2010-10-07 18:29:44 +00:00
33a390e2ca
CMake: Fix warning in gtest.
...
llvm-svn: 115935
2010-10-07 18:12:54 +00:00
bf70a035f0
Add an initialization routine for libLLVMipo.a
...
llvm-svn: 115933
2010-10-07 18:09:59 +00:00
383fec5d99
Add a header that I forgot to commit.
...
llvm-svn: 115932
2010-10-07 18:05:11 +00:00
49715fd494
Cache interval iterators in SplitEditor::addTruncSimpleRange so we only have to
...
do one find().
llvm-svn: 115929
2010-10-07 17:56:39 +00:00
9575af4b06
Clean up debug printing.
...
llvm-svn: 115928
2010-10-07 17:56:35 +00:00
4698c5d7f7
Next step on the getting-rid-of-static-ctors train: begin adding per-library
...
initialization functions that initialize the set of passes implemented in
that library. Add C bindings for these functions as well.
llvm-svn: 115927
2010-10-07 17:55:47 +00:00
82d38df40c
Fix a warning when building with clang++.
...
llvm-svn: 115924
2010-10-07 17:04:18 +00:00
daab660fb1
trailing whitespace
...
llvm-svn: 115923
2010-10-07 16:56:28 +00:00
ac1ffa27b6
Add the missing cases to the type->registerclass conversion function.
...
llvm-svn: 115921
2010-10-07 16:32:42 +00:00
a845022ddd
Implement two virtual functions in SPUTargetLowering.
...
Before the implementation of isLegalAddressingMode, some rare cases
of code were miscompiled if optimized with the LoopStrengthReduce pass.
It is unclear (to me) if LSR is "allowed" to produce wrong code with a
bad TargetLowering, or if the bug is elsewhere and this patch just
hides it.
llvm-svn: 115919
2010-10-07 16:24:35 +00:00
87002b592e
Minor cosmetic change: fix DOSish \r\n.
...
llvm-svn: 115910
2010-10-07 07:21:04 +00:00
1666b61357
MC-COFF: Fix symbol aliases. Fixes PR8251.
...
llvm-svn: 115909
2010-10-07 06:29:33 +00:00
efc22274cd
test: Fix binary stdin issues with coff-dump on Windows.
...
llvm-svn: 115908
2010-10-07 06:29:21 +00:00
a2583ea9f2
Use the correct register class for load instructions - fixes
...
compilation of MultiSource/Benchmarks/Bullet.
llvm-svn: 115907
2010-10-07 05:50:44 +00:00
76a9752d45
Use the correct register class here.
...
llvm-svn: 115906
2010-10-07 05:39:19 +00:00
a98be90efe
Use the thumb2 conditional move instruction.
...
llvm-svn: 115905
2010-10-07 05:31:49 +00:00
6d74673366
Remove in-progress assertion, add TODO.
...
llvm-svn: 115904
2010-10-07 05:14:08 +00:00
1b468683c2
Add the header that I accidentally forgot from r115900.
...
llvm-svn: 115901
2010-10-07 04:17:38 +00:00
5e19bfcde3
Move the pass initialization helper functions into the llvm namespace, and add
...
a header declaring them all. This is also where we will declare per-library pass-set
initializer functions down the road.
llvm-svn: 115900
2010-10-07 04:13:08 +00:00
1958cefd69
Model operand cycles of vldm / vstm; also fixes scheduling itineraries of vldr / vstr, etc.
...
llvm-svn: 115898
2010-10-07 01:50:48 +00:00
67677515ac
add support for isConvertibleToThreeAddress to ArithBinOpEFLAGS,
...
allowing us to convert ADD over. deletes 160 lines of .td file.
llvm-svn: 115897
2010-10-07 01:37:01 +00:00
4fc52f6fa0
Fix a few issues in ArithBinOpEFLAGS that made it specific to and.
...
Start using ArithBinOpEFLAGS for OR, XOR, and SUB.
This removes 500 lines from the .td file. Now AND/OR/XOR/SUB are all
defined exactly the same way instead of being close relatives.
llvm-svn: 115896
2010-10-07 01:26:27 +00:00
26d6a0449a
Convert 'and' to single instance of a multipattern
...
which instantiates the 34 versions of and all in one
swoop. The BaseOpc/BaseOpc2/BaseOpc4 stuff should not
be required, but tblgen's feeble brain explodes when I
use Or4<BaseOpc>.V in the multipattern.
No change in the generated .inc files.
llvm-svn: 115893
2010-10-07 01:10:20 +00:00
5b255c2dd6
Allow use of the 16-bit literal move instruction in CMOVs for Thumb2 mode.
...
llvm-svn: 115890
2010-10-07 00:53:56 +00:00
b71a77d7b8
add a new BinOpAI class to represent the immediate form that directly acts on EAX.
...
This does change the generated .inc files to include the implicit use/def of eax.
Since these instructions are only generated by the assembler and disassembler it
doesn't actually matter though.
llvm-svn: 115885
2010-10-07 00:43:39 +00:00
742adc328a
Allow use of the 16-bit literal move instruction in CMOVs for ARM mode.
...
llvm-svn: 115884
2010-10-07 00:42:42 +00:00
894d2e6146
add a bunch of classes for other common patterns.
...
As usual, no change in generated .inc files.
llvm-svn: 115882
2010-10-07 00:35:28 +00:00
6da4d820fa
Since the Hello pass is built as a loadable dynamic library, don't try to convert it to new-style registration yet.
...
llvm-svn: 115881
2010-10-07 00:31:16 +00:00
e17d7212f1
Define a new BinOpRI8 class and use it to define the imm8 versions of and.
...
llvm-svn: 115880
2010-10-07 00:12:45 +00:00
b19bae4e3e
Constrain the offset register to a *_NOSP register class when inserting LEA
...
instructions.
This unbreaks the machine code verifier and fixes PR8317.
llvm-svn: 115879
2010-10-07 00:07:26 +00:00
356f16c142
add the pattern operator to match to X86TypeInfo, use this to
...
convert AND64ri32 to use BinOpRI.
llvm-svn: 115878
2010-10-07 00:01:39 +00:00
bf7cffc730
add a common SDPatternOperator base class to SDNode and PatFrag for
...
stuff that wants to take one or the other. These can both be used
as the operation of a dag in a pattern match.
llvm-svn: 115877
2010-10-07 00:01:00 +00:00
b2dd88db6b
Properly handle GR32_NOSP in X86RegisterInfo::getMatchingSuperRegClass.
...
This function looks like it is about ready to be generated by TebleGen.
llvm-svn: 115876
2010-10-06 23:56:46 +00:00
18842783cc
Add MachineRegisterInfo::constrainRegClass and use it in MachineCSE.
...
This function is intended to be used when inserting a machine instruction that
trivially restricts the legal registers, like LEA requiring a GR32_NOSP
argument.
llvm-svn: 115875
2010-10-06 23:54:39 +00:00
1a065e4e5b
Skip unused registers when verifying LiveIntervals.
...
llvm-svn: 115874
2010-10-06 23:54:35 +00:00
c473587e28
Fixed RELEASE_28 tags.
...
llvm-svn: 115872
2010-10-06 23:50:30 +00:00
25cd3bfbd7
remove trailing whitespace
...
llvm-svn: 115860
2010-10-06 22:46:47 +00:00
bff84d418f
First in a sequence of ARM/MC/*ELF* specific work.
...
Lifted the EmitRawText calls to ARMAsmPrinter::emitAttribute()
Added ARMAsmPrinter::emitAttributes() (plural s).
TODO:
.cpu attribute needs to be refactored
llvm-svn: 115859
2010-10-06 22:36:46 +00:00
883936ce0b
Another case of 256 sections not being enough :-)
...
llvm-svn: 115858
2010-10-06 22:28:19 +00:00
af08ad4350
Appease the clang self-host buildbot by providing a correct instantiation.
...
llvm-svn: 115857
2010-10-06 22:23:20 +00:00
24ab1ce8c2
Clean up MOVi32imm and t2MOVi32imm pseudo instruction definitions.
...
llvm-svn: 115853
2010-10-06 22:01:26 +00:00
f49540cb4f
Kill of the vestiges of the 'call' Modifier (no longer needed for PLT).
...
llvm-svn: 115845
2010-10-06 21:36:43 +00:00
2c95027258
Now that VDUPfqf and VDUPfdfare properly pseudos, kill the no-longer-needed
...
"lane" operand modifier.
llvm-svn: 115843
2010-10-06 21:22:32 +00:00
b270f28c1a
Now that VDUPfqf and VDUPfdfare properly pseudos, nuke the special handling.
...
llvm-svn: 115841
2010-10-06 21:17:07 +00:00
2e3e2a006b
Change the NEON VDUPfdf and VDUPfqf pseudo-instructions to actually be
...
pseudo instructions.
llvm-svn: 115840
2010-10-06 21:16:16 +00:00
436bc5fdb3
Fix libc++ link in release notes.
...
llvm-svn: 115837
2010-10-06 21:07:30 +00:00
5f2d6a5cd9
Get binding and visibility info from the the alias, but Type from the symbol
...
being aliased.
llvm-svn: 115836
2010-10-06 21:02:29 +00:00
ad8134f03b
Hide analysis group registration behind a macro, just like pass registration.
...
llvm-svn: 115835
2010-10-06 21:02:27 +00:00
9a33ec24eb
Add support for DW_TAG_unspecified_parameters.
...
llvm-svn: 115833
2010-10-06 20:50:40 +00:00
233b3a2f95
Add a 'pattern' arg to the ARM PseudoNeonI class.
...
llvm-svn: 115831
2010-10-06 20:36:55 +00:00
e535b01a74
MC: Add missing forward in MCLoggingStreamer.
...
llvm-svn: 115830
2010-10-06 20:36:47 +00:00
7fb03204cd
Cleanup Whitespace.
...
llvm-svn: 115829
2010-10-06 20:36:38 +00:00
5ed50b6151
Revert "RequiresUnique" patch. This should be handled at a lower level.
...
llvm-svn: 115827
2010-10-06 20:18:44 +00:00
b93cf04d9a
Pass initialization functions should take a PassRegistry as a parameter
...
rather than being fixed to the global registry.
llvm-svn: 115824
2010-10-06 20:07:03 +00:00
d444577382
If a symbol is global, reloc against it even if it is in a mergeable section.
...
llvm-svn: 115817
2010-10-06 19:27:21 +00:00
ec0da969fb
Remove unused variables.
...
llvm-svn: 115802
2010-10-06 18:11:50 +00:00
3ab7e510e9
Remove compatibilty code for old-style multiple return values.
...
llvm-svn: 115799
2010-10-06 16:59:24 +00:00
8025f89860
target operand flag values aren't a bitmask
...
llvm-svn: 115798
2010-10-06 16:51:55 +00:00
83b2a3337f
Make sure weak symbols are listed after the local ones.
...
llvm-svn: 115795
2010-10-06 16:47:31 +00:00
8f3d2c9058
Correctly handle GOTPCREL relocations.
...
llvm-svn: 115793
2010-10-06 16:23:36 +00:00
aadc5596f1
ComputeLinearIndex doesn't need its TLI argument.
...
llvm-svn: 115792
2010-10-06 16:18:29 +00:00
3f0068d661
Constify isReachableFromEntry.
...
llvm-svn: 115788
2010-10-06 15:49:14 +00:00
5af766bb1e
Add missing "-" to the command line.
...
llvm-svn: 115777
2010-10-06 11:43:06 +00:00
546548036c
Remove tabs.
...
llvm-svn: 115764
2010-10-06 07:19:18 +00:00
10f60fa411
Change RequiresMerge to RequiresUnique. It's a better description of what this
...
fix is trying to accomplish.
This code could still use some polishing.
llvm-svn: 115759
2010-10-06 07:03:52 +00:00
6f2ae72c90
No need to check out everything: binutils is enough.
...
Patch by John Tytgat.
llvm-svn: 115757
2010-10-06 06:45:11 +00:00
49d4c0bd18
- Add TargetInstrInfo::getOperandLatency() to compute operand latencies. This
...
allow target to correctly compute latency for cases where static scheduling
itineraries isn't sufficient. e.g. variable_ops instructions such as
ARM::ldm.
This also allows target without scheduling itineraries to compute operand
latencies. e.g. X86 can return (approximated) latencies for high latency
instructions such as division.
- Compute operand latencies for those defined by load multiple instructions,
e.g. ldm and those used by store multiple instructions, e.g. stm.
llvm-svn: 115755
2010-10-06 06:27:31 +00:00
cd8fe46d4b
If the destination module all ready has a copy of the global coming from the
...
source module *and* it must be merged (instead of simply replaced or appended
to), then merge instead of replacing or adding another global.
The ObjC __image_info section was being appended to because of this
failure. This caused a crash because the linker expects the image info section
to be a specific size.
<rdar://problem/8198537>
llvm-svn: 115753
2010-10-06 06:16:30 +00:00
6e85be2ecf
enhance X86TypeInfo to include information about the encoding and
...
operand kind for immediates. Use these to define a new BinOpRI
class and switch AND8/16/32ri over to it. AND64ri32 needs some
more refactoring before it can make the switcheroo.
llvm-svn: 115752
2010-10-06 05:55:42 +00:00
3d7ec7b55d
Update release location.
...
llvm-svn: 115749
2010-10-06 05:36:01 +00:00
94eff91dc0
add a class for _REV nodes.
...
llvm-svn: 115748
2010-10-06 05:35:22 +00:00
a46073b56b
sink more intelligence into the ITy base class. Now it knows
...
that i8 operations are even and i16,i32,i64 operations have a
low opcode bit set (they are odd).
llvm-svn: 115747
2010-10-06 05:28:38 +00:00
b6da2be7e8
refactor things a bit, now the REX_W and OpSize prefix bytes are inferred from the type info.
...
llvm-svn: 115745
2010-10-06 05:20:57 +00:00
7bbd809b6c
with tblgen suitably extended, we can now get the load node from typeinfo.
...
llvm-svn: 115744
2010-10-06 04:58:43 +00:00
28f034c21a
Generalize tblgen's dag parsing logic to handle arbitrary expressions
...
as the operator of the dag. Specifically, this allows parsing things
like (F.x 4) in addition to just (a 4).
Unfortunately, this runs afoul of an idiom being used by llvmc. It
is using dags like (foo [1,2,3]) to represent a list of stuff being
passed into foo. With this change, this is parsed as a [1,2,3]
subscript on foo instead of being the first argument to the dag.
Cope with this in the short term by requiring a "-llvmc-temp-hack"
argument to tblgen to get the old parsing behavior.
llvm-svn: 115742
2010-10-06 04:55:48 +00:00
805b74d650
rename add some comments.
...
llvm-svn: 115741
2010-10-06 04:37:17 +00:00
7d5bb96723
filecheckize
...
llvm-svn: 115740
2010-10-06 04:36:30 +00:00
e76cfcf8a8
cleanups
...
llvm-svn: 115739
2010-10-06 04:31:40 +00:00
ad205575fc
lib/System/Win32/Signals.inc: Enable LLVM_DISABLE_CRT_DEBUG also on mingw.
...
llvm-svn: 115731
2010-10-06 02:15:22 +00:00
0198ce06fc
Provide a fast "get me the target triple from the module" API. This can
...
drastically reduce the linking time during LTO.
Patch by Shantonu Sen!
llvm-svn: 115728
2010-10-06 01:22:42 +00:00
1fc81e90f7
lets go all meta and define new X86 type wrappers that declare the associated
...
gunk that goes along with an MVT (e.g. reg class, preferred load operation,
memory operand)
llvm-svn: 115727
2010-10-06 00:45:24 +00:00
eadaeaab93
introduce a new BinOpRM class and use it to factor AND*rm. This points out
...
that I need a heavier handed approach to get ultimate factorization.
llvm-svn: 115726
2010-10-06 00:30:49 +00:00
9402633637
remove the !nameconcat tblgen feature. It "shorthand" and only used in 4 places
...
where !cast is just as short.
llvm-svn: 115722
2010-10-06 00:19:21 +00:00
04c342ea20
replace stuff like:
...
let AsmString = !strconcat(
!strconcat(!strconcat(opc, "${p}"), !strconcat(".", dt)),
!strconcat("\t", asm));
with:
let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm);
:)
llvm-svn: 115720
2010-10-06 00:05:18 +00:00
61ea00b494
allow !strconcat to take more than two operands to eliminate
...
!strconcat(!strconcat(!strconcat(!strconcat
Simplify some x86 td files to use it.
llvm-svn: 115719
2010-10-05 23:58:18 +00:00
d7565c3a06
Use a relocation against the symbol if it is a PLT and the symbol is in another
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section. Common because of linkonce sections.
llvm-svn: 115718
2010-10-05 23:57:26 +00:00
b9f2d50d5f
Comment out fastisel debugging message.
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llvm-svn: 115717
2010-10-05 23:50:58 +00:00
97b1368ae3
associate the instruction suffix letter with the integer gpr
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register class, and use this to simplify use of BinOpRR.
llvm-svn: 115716
2010-10-05 23:43:04 +00:00
7359194b63
introduce a new BinOpRR class, and convert 4 and instructions to use it.
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llvm-svn: 115715
2010-10-05 23:32:05 +00:00
8cfc459274
Random cleanup and make the intermediate register in fptosi a
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32-bit fp reg, not 64-bit.
Fixes SingleSource.
llvm-svn: 115711
2010-10-05 23:13:24 +00:00
4d5156c7d0
Count uses in all nested loops, not just the deepest.
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llvm-svn: 115710
2010-10-05 23:10:12 +00:00
56e2925e6c
Remove SplitAnalysis::removeUse. It was only used to make SplitAnalysis
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reusable, but that is no longer relevant since a split will always replace the
original.
llvm-svn: 115709
2010-10-05 23:10:09 +00:00
0445e2a053
dupli always has an interval now.
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llvm-svn: 115708
2010-10-05 23:10:04 +00:00
cff5b0ea36
Move cmov pseudo instructions to InstrCompiler,
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convert all the rest of the cmovs to the multiclass,
with good results:
X86InstrCMovSetCC.td | 598 +--------------------------------------------------
X86InstrCompiler.td | 61 +++++
2 files changed, 77 insertions(+), 582 deletions(-)
llvm-svn: 115707
2010-10-05 23:09:10 +00:00
1a1c600110
Use #NAME# to have the CMOV multiclass define things with the same names as before
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(e.g. CMOVBE16rr instead of CMOVBErr16).
llvm-svn: 115705
2010-10-05 23:00:14 +00:00
b8ff8f0cb6
when david added support for #NAME# he didn't update the comments and
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tried (but failed) to artificially constrain it to working with #NAME#.
Just allow any # in identifiers, and update the comments.
llvm-svn: 115704
2010-10-05 22:59:29 +00:00
c25b39702f
Another step towards getting rid of static ctors for pass registration: have INITIALIZE_PASS AND INITIALIZE_AG_PASS
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expand to an initializeMyPass() function (in additional to the extant static ctors). Eventually, these will be called
from a big InitializeAllPasses() function, and the PassInfo's they create (which would be leaked if this code were used
at the moment) will be handed off to a PassRegistry for ownership.
llvm-svn: 115703
2010-10-05 22:58:16 +00:00
7538ed80a9
enhance tblgen to support anonymous defm's, use this to
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simplify the X86 CMOVmr's.
llvm-svn: 115702
2010-10-05 22:51:56 +00:00
fa25dd9548
convert cmov mr patterns to use a multipattern. Death to redundancy
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and verbosity
llvm-svn: 115701
2010-10-05 22:42:54 +00:00
0ad137e98e
Implement more alias cases.
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llvm-svn: 115699
2010-10-05 22:26:43 +00:00
0067ee02f9
switch CMOVBE to the multipattern:
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21 insertions(+), 53 deletions(-)
Moar change coming before I switch the rest.
llvm-svn: 115697
2010-10-05 22:23:58 +00:00
2dfa8be26a
We can split around loops with multiple exits now.
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llvm-svn: 115696
2010-10-05 22:19:35 +00:00
89d276aa48
Update SplitEditor API to reflect the fact that the original live interval is
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never kept after splitting.
Keeping the original interval made sense when the split region doesn't modify
the register, and the original is spilled. We can get the same effect by
detecting reloaded values when spilling around copies.
llvm-svn: 115695
2010-10-05 22:19:33 +00:00
b46d32367f
Intervals are half-open.
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llvm-svn: 115694
2010-10-05 22:19:29 +00:00
907d86db22
fix a bug I introduced in r115669, which ended up with MOV64mr_TC
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not getting marked as mayStore. This fixes llvm-gcc bootstrap.
llvm-svn: 115693
2010-10-05 22:16:48 +00:00
c3a767e9b0
add a multiclass for cmov's, but don't start using it yet.
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llvm-svn: 115692
2010-10-05 22:01:02 +00:00
10a0fdeab5
PSHUFW is in SSE, not SSSE3.
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llvm-svn: 115691
2010-10-05 21:58:12 +00:00
aa02c1c91d
use a multipattern to define setcc instructions:
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X86InstrCMovSetCC.td | 200 ++++++---------------------------------------------
1 file changed, 27 insertions(+), 173 deletions(-)
llvm-svn: 115689
2010-10-05 21:34:29 +00:00
3844da781f
256 sections should be enough for anyone...
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llvm-svn: 115687
2010-10-05 21:20:07 +00:00
Chris Lattner