72dfd20aba
ARM assembly parsing for two-operand form of 'mul' instruction.
...
Ongoing rdar://10435114.
llvm-svn: 144688
2011-11-15 20:02:06 +00:00
c14871cc67
ARM assembly parsing for LSR/LSL/ROR(immediate).
...
More of rdar://9704684
llvm-svn: 144301
2011-11-10 19:18:01 +00:00
61db5a59f7
ARM assembly parsing for ASR(immediate).
...
Start of rdar://9704684
llvm-svn: 144293
2011-11-10 16:44:55 +00:00
16c8fc5191
Revert r142618, r142622, and r142624, which were based on an incorrect reading of the ARMv7 docs.
...
llvm-svn: 142626
2011-10-20 22:23:58 +00:00
48da0ed477
Fix tests for corrected MSR encodings.
...
llvm-svn: 142622
2011-10-20 21:53:19 +00:00
84cf2b8c98
ARM encoding tests for STC.
...
llvm-svn: 141787
2011-10-12 17:36:13 +00:00
483995875f
ARM parsing and encoding for the <option> form of LDC/STC instructions.
...
llvm-svn: 141786
2011-10-12 17:34:41 +00:00
9398141c48
ARM assembly parsing and encoding for LDC{2}{L}/STC{2}{L} instructions.
...
Fill out the rest of the encoding information, update to properly mark
the LDC/STC instructions as predicable while the LDC2/STC2 instructions are
not, and adjust the parser accordingly.
llvm-svn: 141721
2011-10-11 21:55:36 +00:00
e65c2ab453
Tidy up.
...
llvm-svn: 140114
2011-09-20 00:24:37 +00:00
788a8cd4e6
Tidy up a bit.
...
llvm-svn: 140096
2011-09-19 23:34:18 +00:00
ee9ff79319
Remove FIXME. TBB/TBH are Thumb mode only instructions.
...
llvm-svn: 140048
2011-09-19 20:30:29 +00:00
4eea5d6284
Fix comment.
...
llvm-svn: 139919
2011-09-16 18:03:00 +00:00
d2868cf016
Add some missing 'CHECK' lines and tidy up others.
...
llvm-svn: 139849
2011-09-15 21:17:38 +00:00
0ecd395095
Thumb2 assembly parsing and encoding for MSR/MRS.
...
Fix a bug in handling default flags for both ARM and Thumb encodings.
llvm-svn: 139721
2011-09-14 20:03:46 +00:00
54175d519e
Tidy up formatting a bit.
...
llvm-svn: 139396
2011-09-09 20:17:49 +00:00
f6d5d60f99
ARM 'rscs' mnemonic is carry-setting 'rsc', not 'rs' with a 'cs' condition code.
...
llvm-svn: 138952
2011-09-01 18:22:13 +00:00
967674d26c
Improve handling of #-0 offsets for many more pre-indexed addressing modes.
...
llvm-svn: 138754
2011-08-29 19:36:44 +00:00
f02d98d7c0
Add support for parsing #-0 on non-memory-operand immediate values, and add a testcase that necessitates it.
...
llvm-svn: 138739
2011-08-29 17:17:09 +00:00
b205c029a4
Improve encoding support for BLX with immediat eoperands, and fix a BLX decoding bug this uncovered.
...
llvm-svn: 138675
2011-08-26 23:32:08 +00:00
6c70e58041
Correct encoding of BL with immediate offset.
...
llvm-svn: 138673
2011-08-26 22:54:51 +00:00
a01bcbfc80
Support an extension of ARM asm syntax to allow immediate operands to ADR instructions. This is helpful for disassembler testing, and indeed exposed a disassembler bug that is also fixed here.
...
llvm-svn: 138635
2011-08-26 18:09:22 +00:00
61a3ece665
Fix incorrect encoding of UMAAL and friends. Patch by James Molloy.
...
llvm-svn: 137641
2011-08-15 20:08:25 +00:00
aa07cb6a98
Fix tests per now-correct encoding as of r137371.
...
llvm-svn: 137376
2011-08-11 22:31:48 +00:00
d564bf3181
ARM STR(immediate) assembly parsing and encoding.
...
llvm-svn: 137331
2011-08-11 19:22:40 +00:00
27ad83d8a9
ARM push of a single register encodes as pre-indexed STR.
...
Per the ARM ARM, a 'push' of a single register encodes as an STR,
not an STM.
llvm-svn: 137318
2011-08-11 18:07:11 +00:00
8ba76c6d5c
ARM pop of a single register encodes as post-indexed LDR.
...
Per the ARM ARM, a 'pop' of a single register encodes as an LDR,
not an LDM.
llvm-svn: 137316
2011-08-11 17:35:48 +00:00
51726e2147
ARM SRS instruction parsing, diassembly and encoding support.
...
Fix the instruction encoding for operands. Refactor mode to use explicit
instruction definitions per FIXME to be more consistent with loads/stores.
Fix disassembler accordingly. Add tests.
llvm-svn: 136509
2011-07-29 20:26:09 +00:00
c4dc52cd52
ARM assembly parsing and encoding for RFE instruction.
...
Fill in the missing fixed bits and the register operand bits of the instruction
encoding. Refactor the definition to make the mode explicit, which is
consistent with how loads and stores are normally represented and makes
parsing much easier. Add parsing aliases for pseudo-instruction variants.
Update the disassembler for the new representations. Add tests for parsing and
encoding.
llvm-svn: 136479
2011-07-29 18:47:24 +00:00
1c1d2438aa
ARM update tests for CPS instruction.
...
llvm-svn: 136472
2011-07-29 17:39:27 +00:00
b9bebc1b03
CBZ/CBNZ are Thumb2 only. No need for ARM mode tests for them.
...
llvm-svn: 136408
2011-07-28 21:59:38 +00:00
a03ab0e3dc
ARM assembly parsing and encoding for BLX (immediate).
...
Add parsing support for BLX (immediate). Since the register operand version is
predicated and the label operand version is not, we have to use some special
handling to get the operand list right for matching.
llvm-svn: 136406
2011-07-28 21:57:55 +00:00
7f45559e86
Remove obsolete FIXME reference in comment.
...
llvm-svn: 136400
2011-07-28 21:37:05 +00:00
864b609491
ARM assembly parsing and encoding for BFC and BFI.
...
Add parsing support that handles converting the lsb+width source into the
odd way we represent the instruction (an inverted bitfield mask).
llvm-svn: 136399
2011-07-28 21:34:26 +00:00
8b3184e540
ARM parsing and encoding for ADR.
...
The label does not have a '#' prefix. Add parsing and encoding tests.
llvm-svn: 136360
2011-07-28 16:33:54 +00:00
4356636fc0
Update ARM tests for parsing and encoding of WFE, WFI and YIELD.
...
llvm-svn: 136358
2011-07-28 16:00:41 +00:00
4059137f56
ARM parsing and encoding tests.
...
UXTAB, UXTAB16, UXTAH, UXTB, UXTB16, and UXTH.
llvm-svn: 136312
2011-07-28 00:37:03 +00:00
e37f7dc349
ARM assembly parsing and encoding for USUB16 and USUB8.
...
llvm-svn: 136289
2011-07-27 23:10:05 +00:00
05f80d3add
ARM assembly parsing and encoding for USAX.
...
llvm-svn: 136288
2011-07-27 23:07:00 +00:00
16dd4adcbe
Clean up tabs.
...
llvm-svn: 136286
2011-07-27 22:35:06 +00:00
57e2d3cb84
ARM assembly parsing and encoding support for USAT and USAT16.
...
Use range checked immediate operands for instructions. Add tests.
llvm-svn: 136285
2011-07-27 22:34:17 +00:00
fea7a44a9b
ARM assembly parsing and encoding tests for USAD8 and USADA8.
...
llvm-svn: 136284
2011-07-27 22:23:02 +00:00
1644409b47
ARM assembly parsing and encoding tests for UQSUB16 and UQSUB8.
...
llvm-svn: 136282
2011-07-27 22:13:08 +00:00
1a3ddffc1c
Fix comment copy/paste-o.
...
llvm-svn: 136281
2011-07-27 22:11:41 +00:00
84ecab228a
ARM assembly parsing and encoding tests for UQASX and UQSAX.
...
llvm-svn: 136280
2011-07-27 22:09:30 +00:00
928f4175c0
ARM assembly parsing and encoding tests for UQADD16 and UQADD8.
...
llvm-svn: 136279
2011-07-27 22:08:14 +00:00
39b062bfaa
ARM assembly parsing and encoding for UMULL.
...
Fix parsing of the 's' suffix for the mnemonic. Add tests.
llvm-svn: 136277
2011-07-27 22:01:42 +00:00
0c398b9c7e
ARM assembly parsing and encoding for UMLAL.
...
Fix parsing of the 's' suffix for the mnemonic. Add tests.
llvm-svn: 136274
2011-07-27 21:58:11 +00:00
121c21aba9
ARM assembly parsing and encoding tests for UMAAL.
...
llvm-svn: 136272
2011-07-27 21:53:42 +00:00
7cfd32a006
ARM assembly parsing and encoding tests for UHSUB16 and UHSUB8.
...
llvm-svn: 136267
2011-07-27 21:21:59 +00:00
3f45383ef5
ARM assembly parsing and encoding tests for UHADD16, UHADD8 and UHASX.
...
llvm-svn: 136266
2011-07-27 21:20:45 +00:00
03f56d9de6
ARM parsing and encoding of SBFX and UBFX.
...
Encode the width operand as it encodes in the instruction, which simplifies
the disassembler and the encoder, by using the imm1_32 operand def. Add a
diagnostic for the context-sensitive constraint that the width must be in
the range [1,32-lsb].
llvm-svn: 136264
2011-07-27 21:09:25 +00:00
36ce7492a6
ARM assembly parsing and encoding tests for UADD16, UADD8 and UASX.
...
llvm-svn: 136261
2011-07-27 20:43:44 +00:00
542333ea05
ARM assembly parsing and encoding tests for TST instruction.
...
llvm-svn: 136260
2011-07-27 20:38:58 +00:00
f176e1addb
ARM assembly parsing and encoding tests for TEQ instruction.
...
llvm-svn: 136259
2011-07-27 20:37:36 +00:00
833b9d3353
ARM assembly parsing and encoding for extend instructions.
...
Assembly parser handling for extend instruction rotate operands. Add tests
for the sign extend instructions.
llvm-svn: 136252
2011-07-27 20:15:40 +00:00
4e895470bd
ARM parsing and encoding tests for load/store exclusive instructions.
...
llvm-svn: 136105
2011-07-26 18:07:21 +00:00
15e8d74231
ARM assembly parsing and encoding for SWP[B] instructions.
...
llvm-svn: 136098
2011-07-26 17:15:11 +00:00
f16378479b
ARM parsing and encoding for SVC instruction.
...
llvm-svn: 136090
2011-07-26 16:24:27 +00:00
2c374c4fb6
ARM assembly parsing and encoding tests for SUB instruction.
...
llvm-svn: 136089
2011-07-26 15:44:05 +00:00
dc45f00cf5
Update ARM STM tests. Fix check: prefix for diagnostic tests.
...
llvm-svn: 136088
2011-07-26 15:41:22 +00:00
9becc53e32
ARM assembly parsing and encoding for SSAX, SSUB16 and SSUB8.
...
llvm-svn: 136013
2011-07-25 23:32:14 +00:00
475c6dbef6
ARM assembly parsing and encoding for SSAT16 instruction.
...
llvm-svn: 136006
2011-07-25 23:09:14 +00:00
3a9cbeed73
ARM assembly parsing and encoding for SSAT instruction.
...
Fix the Rn register encoding for both SSAT and USAT. Update the parsing of the
shift operand to correctly handle the allowed shift types and immediate ranges
and issue meaningful diagnostics when an illegal value or shift type is
specified. Add aliases to parse an ommitted shift operand (default value of
'lsl #0').
Add tests for diagnostics and proper encoding.
llvm-svn: 135990
2011-07-25 22:20:28 +00:00
d69b3423a8
Add FIXME
...
llvm-svn: 135819
2011-07-22 22:15:38 +00:00
bc5d709ad9
ARM encoding and assembly parsing tests for SMULWB, SMULWT, SMUSD and SMUSDX.
...
llvm-svn: 135818
2011-07-22 22:13:00 +00:00
e7e1e163db
ARM assembly parsing and encoding updates.
...
Tests for SMULBB, SMLALBT, SMLALTB, SMLALTT, and SMULL. Fix parsing of SMULLS.
llvm-svn: 135817
2011-07-22 22:06:05 +00:00
999afadffa
ARM assembly parsing and encoding tests.
...
Add tests for SMLSD, SMLSDX, SMLSLD, SMLSLDX, SMMLA, SMMLAR, SMMLS, SMMLSR,
SMMUL, SMMULR, SMUAD and SMUADX.
llvm-svn: 135810
2011-07-22 21:34:56 +00:00
5b84e16503
ARM assembly parsing and encoding tests for SMLAWB/SMLAWT.
...
llvm-svn: 135800
2011-07-22 20:51:24 +00:00
e2220221a2
ARM assembly parsing and encoding tests.
...
Tests for SMLAL, SMLALBB, SMLALBT, SMLALTB, SMLALTT, SMLALD, and SMLALDX
instructions.
llvm-svn: 135798
2011-07-22 20:30:40 +00:00
8dfcc0bb92
ARM assembly parsing and encoding of SMLAL instruction.
...
Fix parsing of carry-setting variant SMLALS and add tests.
llvm-svn: 135797
2011-07-22 20:18:21 +00:00
d7c8c35301
ARM encoding and assembly parsing of SMLAD{X} instructions.
...
Fix encoding of destination register. Add tests.
llvm-svn: 135796
2011-07-22 20:11:20 +00:00
0b28f0cca2
ARM testcases for assembly parsing and encoding SMLA* instructions.
...
llvm-svn: 135795
2011-07-22 20:01:34 +00:00
d1f8bde10f
ARM assembly parsing and encoding for SMC instruction.
...
llvm-svn: 135782
2011-07-22 18:13:31 +00:00
24ace20824
ARM encoding and assembly parsing tests.
...
Add tests for SHADD8, SHADD16, SHASX, SHSUB8, and SHSUB16.
llvm-svn: 135780
2011-07-22 18:04:48 +00:00
0a547701a4
ARM assembly parsing and encoding for SETEND instruction.
...
Add parsing and diagnostics for malformed inputs. Tests for diagnostics and
for correct encodings.
llvm-svn: 135776
2011-07-22 17:44:50 +00:00
4535b9194a
ARM assembly parsing and encoding tests for SEL instruction.
...
llvm-svn: 135772
2011-07-22 16:59:33 +00:00
3354674b48
ARM parsing and encoding tests for SBC instruction.
...
llvm-svn: 135718
2011-07-21 23:03:59 +00:00
8dbf59d041
ARM testcases for SADD/SASX parsing and encoding.
...
llvm-svn: 135715
2011-07-21 23:00:49 +00:00
2a0320c877
ARM assembly parsing support for RSC instruction.
...
Add two-operand instruction aliases. Add parsing and encoding tests for
variants of the instruction.
llvm-svn: 135713
2011-07-21 22:56:30 +00:00
17806e6636
ARM assembly parsing support for RSB instruction.
...
Add two-operand instruction aliases. Add parsing and encoding tests for
variants of the instruction.
llvm-svn: 135712
2011-07-21 22:37:43 +00:00
2a22c06267
ARM parsing and encoding tests for RBIT, REV, REV16 and REVSH.
...
llvm-svn: 135710
2011-07-21 22:29:23 +00:00
b31e60b7c6
ARM parsing and encodings tests for saturating arithmetic insns.
...
llvm-svn: 135709
2011-07-21 22:18:28 +00:00
0a8d89242f
ARM assembly parsing POP/PUSH mnemonics.
...
Aliases for LDM/STM. The single-register versions should encode to LDR/STR
with writeback, but we don't (yet) get that correct. Neither does Darwin's
system assembler, though, so that's not a deal-breaker of a limitation.
llvm-svn: 135702
2011-07-21 19:57:11 +00:00
b2aa2c4a24
Add tests for ARM PKH assembly parsing.
...
llvm-svn: 135696
2011-07-21 19:02:03 +00:00
2ea9f25f5f
Add parsing/encoding tests for ARM ORR instruction.
...
llvm-svn: 135602
2011-07-20 18:48:53 +00:00
a3fcb962eb
Consolidate ARM NOP encoding test.
...
llvm-svn: 135600
2011-07-20 18:39:38 +00:00
614e90a126
ARM parsing and encoding tests for MVN
...
llvm-svn: 135599
2011-07-20 18:37:08 +00:00
8d11490771
ARM assembly parsing of MUL instruction.
...
Correctly handle 's' bit and predication suffices. Add parsing and encoding
tests.
llvm-svn: 135596
2011-07-20 18:20:31 +00:00
d25c2cdad7
Tweak ARM assembly parsing and printing of MSR instruction.
...
The system register spec should be case insensitive. The preferred form for
output with mask values of 4, 8, and 12 references APSR rather than CPSR.
Update and tidy up tests accordingly.
llvm-svn: 135532
2011-07-19 22:45:10 +00:00
97094d8f06
ARM assembly parsing of MRS instruction.
...
Teach the parser to recognize the APSR and SPSR system register names. Add
and update tests accordingly.
llvm-svn: 135527
2011-07-19 21:59:29 +00:00
b17d9b12a6
Move mr[r]c[2] ARM tests and tidy up a bit.
...
llvm-svn: 135517
2011-07-19 20:28:56 +00:00
69721dce67
ARM testcases for MOVT.
...
llvm-svn: 135516
2011-07-19 20:23:25 +00:00
5cc3b4cd9a
ARM assembly parsing for MOV (register).
...
Correct the handling of the 's' suffix when parsing ARM mode. It's only a
truly separate opcode in Thumb. Add test cases to make sure we handle
the s and condition suffices correctly, including diagnostics.
llvm-svn: 135513
2011-07-19 20:10:31 +00:00
7c09e3c3f3
ARM assembly parsing for MOV (immediate).
...
Add range checking for the immediate operand and handle the "mov" mnemonic
choosing between encodings based on the value of the immediate. Add tests
for fixups, encoding choice and values, and diagnostic for out of range values.
llvm-svn: 135500
2011-07-19 19:13:28 +00:00
51849920f1
Add some testcases for ARM MLA/MLS instructions.
...
llvm-svn: 135196
2011-07-14 21:43:05 +00:00
26e7449443
ARM MCRR/MCRR2 immediate operand range checking.
...
llvm-svn: 135192
2011-07-14 21:26:42 +00:00
d37d2025e9
ARM MCR/MCR2 assembly parsing operand constraints.
...
The immediate operands are restricted to 0-7. Enforce that when parsing
assembly.
llvm-svn: 135189
2011-07-14 21:19:17 +00:00
2f9aeeef3b
Update ARM Assembly of LDM/STM.
...
ldm/stm are the cannonical spellings for ldmia/stmia, so use them as such.
Update the parsing/encoding tests accordingly.
llvm-svn: 135168
2011-07-14 18:35:38 +00:00
d616cf3497
ARM ISB assembly parsing tests.
...
llvm-svn: 135158
2011-07-14 18:02:25 +00:00
e6f8b1fac6
ARM tests for EOR instruction parsing and encoding.
...
llvm-svn: 135119
2011-07-14 00:22:21 +00:00
Jim Grosbach