Commit Graph

49 Commits

Author SHA1 Message Date
Petar Jovanovic a5da588b2f [mips] Implement %hi(sym1 - sym2) and %lo(sym1 - sym2) expressions
Patch implements %hi(sym1 - sym2) and %lo(sym1 - sym2) expressions for MIPS
by creating target expression class MipsMCExpr.

Patch by Sasa Stankovic.

Differential Revision: http://llvm-reviews.chandlerc.com/D2592

llvm-svn: 200783
2014-02-04 18:41:57 +00:00
David Woodhouse d2cca113df Delete MCSubtargetInfo data members from target MCCodeEmitter classes
The subtarget info is explicitly passed to the EncodeInstruction
method and we should use that subtarget info to influence any
encoding decisions.

llvm-svn: 200350
2014-01-28 23:13:25 +00:00
David Woodhouse 3fa98a65e9 Propagate MCSubtargetInfo through TableGen's getBinaryCodeForInstr()
llvm-svn: 200349
2014-01-28 23:13:18 +00:00
David Woodhouse 9784cef38d Explictly pass MCSubtargetInfo to MCCodeEmitter::EncodeInstruction()
llvm-svn: 200348
2014-01-28 23:13:07 +00:00
Mark Seaborn c3bd177ec2 Fix misaligned indentation in "if" block in MipsMCCodeEmitter.cpp
llvm-svn: 198262
2013-12-31 13:05:15 +00:00
Mark Seaborn 774c24385e Fix indentation alignment of a declaration in MipsMCCodeEmitter.cpp
llvm-svn: 198162
2013-12-29 10:47:04 +00:00
Zoran Jovanovic 69be811a6e Support for microMIPS TLS relocations.
llvm-svn: 197685
2013-12-19 16:02:32 +00:00
Matheus Almeida 6b59c449d9 [mips][msa] Fix issue with immediate fields of LD/ST instructions
not being correctly encoded/decoded.
In more detail, immediate fields of LD/ST instructions should be
divided/multiplied by the size of the data format before encoding and
after decoding, respectively.

llvm-svn: 196494
2013-12-05 11:06:22 +00:00
Matheus Almeida 779c593708 [mips][msa] Fix immediate value of LSA instruction as it was being wrongly encoded.
The immediate field should be encoded as "imm - 1" as the CPU always adds one to that field.

llvm-svn: 195004
2013-11-18 12:32:49 +00:00
Zoran Jovanovic 8a80aa76c8 Support for microMIPS branch instructions.
llvm-svn: 193992
2013-11-04 14:53:22 +00:00
Zoran Jovanovic 507e084a18 Support for microMIPS jump instructions
llvm-svn: 193623
2013-10-29 16:38:59 +00:00
Zoran Jovanovic e7ae8af896 Support for microMIPS relocations 1.
llvm-svn: 193247
2013-10-23 16:14:44 +00:00
Akira Hatanaka 6a3fe57444 [mips] Add definition of instruction "drotr32" (double rotate right plus 32).
llvm-svn: 190232
2013-09-07 00:18:01 +00:00
Jack Carter 4e07b95daf Changed comment
llvm-svn: 189396
2013-08-27 19:45:28 +00:00
Jack Carter 9770097727 [Mips] Support for unaligned load/store microMips instructions
This includes instructions lwl, lwr, swl and swr.

Patch by Zoran Jovnovic

llvm-svn: 188312
2013-08-13 20:19:16 +00:00
Jack Carter 7bd3c7d1fc Mips ELF: MicroMips direct object Little endian support.
Test included.

Patch by Zoran Jovanovich

llvm-svn: 188024
2013-08-08 23:30:40 +00:00
Bill Wendling bc07a8900c Use pointers to the MCAsmInfo and MCRegInfo.
Someone may want to do something crazy, like replace these objects if they
change or something.

No functionality change intended.

llvm-svn: 184175
2013-06-18 07:20:20 +00:00
Rafael Espindola f30f2cce50 Make helper functions static.
And remove header and cpp file that are empty after that.

llvm-svn: 182746
2013-05-27 22:34:59 +00:00
Akira Hatanaka be6a818fd4 [mips] First patch which adds support for micromips.
This patch adds support for recoded (meaning assembly-language compatible to
standard mips32) arithmetic 32-bit instructions.

Patch by Zoran Jovanovic.

llvm-svn: 179873
2013-04-19 19:03:11 +00:00
Jack Carter b5cf5909ac Mips assembler: Enable handling of nested expressions
This patch allows the Mips assembler to parse and emit nested 
expressions as instruction operands. It also extends the 
expansion of memory instructions when an offset is given as 
an expression. 

Contributer: Vladimir Medic
llvm-svn: 179657
2013-04-17 00:18:04 +00:00
Jack Carter 4f69a0f25d Fix the invalid opcode for Mips branch instructions in the assembler
For mips a branch an 18-bit signed offset (the 16-bit 
offset field shifted left 2 bits) is added to the 
address of the instruction following the branch 
(not the branch itself), in the branch delay slot, 
to form a PC-relative effective target address. 

Previously, the code generator did not perform the 
shift of the immediate branch offset which resulted 
in wrong instruction opcode. This patch fixes the issue.

Contributor: Vladimir Medic
llvm-svn: 177687
2013-03-22 00:29:10 +00:00
David Blaikie 725fda1213 Fix the (clang -Werror) build by removing an unused member variable.
llvm-svn: 175607
2013-02-20 07:39:18 +00:00
Jack Carter ab3cb425aa ELF symbol table field st_other support,
excluding visibility bits.

Mips (MicroMips) specific STO handling .

The st_other field settig for STO_MIPS_MICROMIPS

Contributer: Zoran Jovanovic
llvm-svn: 175564
2013-02-19 22:04:37 +00:00
Reed Kotler 76c9bcd43a Remove a final dependency on the form field in tablegen; which is a remnant
of the old jit and which we don't intend to support in mips16 or micromips.
This dependency is for the testing of whether an instruction is a pseudo.

llvm-svn: 175297
2013-02-15 21:05:58 +00:00
Akira Hatanaka 5d6faed1f0 [mips] Set HWEncoding field of registers. Use delete function
getMipsRegisterNumbering and use MCRegisterInfo::getEncodingValue instead.

llvm-svn: 169760
2012-12-10 20:04:40 +00:00
Jack Carter b05cb67b81 Mips direct object xgot support
This patch provides support for the MIPS relocations:

    *)  R_MIPS_GOT_HI16
    *)  R_MIPS_GOT_LO16
    *)  R_MIPS_CALL_HI16
    *)  R_MIPS_CALL_LO16

These are used for large GOT instruction sequences.

Contributer: Jack Carter
llvm-svn: 168471
2012-11-21 23:38:59 +00:00
Jack Carter 5b5559d3f3 This patch moves from using a hard coded number (4)
for the number of bytes in a particular instruction
to using
   const MCInstrDesc &Desc = MCII.get(TmpInst.getOpcode());
   Desc.getSize()

This is necessary with the advent of 16 bit instructions with
mips16 and micromips. It is also puts Mips in compliance with
the other targets for getting instruction size.

llvm-svn: 165171
2012-10-03 21:58:54 +00:00
Jack Carter aa7aeaa0a5 The mips 64bit instructions DSLL, DSRA, DSRL, DEXT and DINS get transformed by the assembler or through codegen direct object output to other variants based on the value of the immediate values of the operands.
If the code is generated as assembler, this transformation does not occur assuming that it will occur later in the assembler.

This code was originally called from  MipsAsmPrinter.cpp and we needed to check for OutStreamer.hasRawTextSupport(). This was not a good place for it and has been moved to MCTargetDesc/MipsMCCodeEmitter.cpp where both direct object and the assembler use it it automagically.

The test cases have been checked in for a number of weeks now.

llvm-svn: 165067
2012-10-02 23:09:40 +00:00
Craig Topper 2ed23ce767 Remove unused private fields to silence -Wunused-private-field.
llvm-svn: 163973
2012-09-15 17:08:51 +00:00
Jack Carter 71e6a7492e Mips specific llvm assembler support for branch and jump instructions.
Test case included.

Contributer: Vladimir Medic
llvm-svn: 163277
2012-09-06 00:43:26 +00:00
Jack Carter 84491abb20 Mips relocations R_MIPS_HIGHER and R_MIPS_HIGHEST.
These 2 relocations gain access to the 
highest and the second highest 16 bits
of a 64 bit object.

R_MIPS_HIGHER %higher(A+S)
The %higher(x) function is [ (((long long) x + 0x80008000LL) >> 32) & 0xffff ]. 

R_MIPS_HIGHEST %highest(A+S)
The %highest(x) function is [ (((long long) x + 0x800080008000LL) >> 48) & 0xffff ]. 

llvm-svn: 161348
2012-08-06 21:26:03 +00:00
Jack Carter 5ddcfda8ef The Mips specific relocation R_MIPS_GOT_DISP
is used in cases where global symbols are 
directly represented in the GOT and we use an 
offset into the global offset table.

This patch adds direct object support for R_MIPS_GOT_DISP.

llvm-svn: 160183
2012-07-13 19:15:47 +00:00
Jack Carter b9f9de93df This allows hello world to be compiled for Mips 64 direct object.
It takes advantage of r159299 which introduces relocation support for N64. 
elf-dump needed to be upgraded to support N64 relocations as well.

This passes make check.

Jack

llvm-svn: 159301
2012-06-27 22:48:25 +00:00
Akira Hatanaka 5fd22485a3 Fix coding style violations. Remove white spaces and tabs.
llvm-svn: 158471
2012-06-14 21:10:56 +00:00
Jim Grosbach c3b0427921 Allow MCCodeEmitter access to the target MCRegisterInfo.
Add the MCRegisterInfo to the factories and constructors.

Patch by Tom Stellard <Tom.Stellard@amd.com>.

llvm-svn: 156828
2012-05-15 17:35:52 +00:00
Bill Wendling f9774c3253 Remove some potential warnings about variables used uninitialized.
llvm-svn: 155307
2012-04-22 07:23:04 +00:00
Akira Hatanaka fe384a2c84 Retrieve and add the offset of a symbol in applyFixup rather than retrieve and
set it in MipsMCCodeEmitter::getMachineOpValue. Assert in getMachineOpValue if
MachineOperand MO is of an unexpected type. 

llvm-svn: 153494
2012-03-27 02:33:05 +00:00
Akira Hatanaka 0137dfe42a Incremental big endian patch by Jack Carter.
These changes allow us to compile big endian from the command line for 32 bit
Mips targets. This patch will result in code and data actually being produced
in the correct endianess.

llvm-svn: 153153
2012-03-21 00:52:01 +00:00
Akira Hatanaka 1ee768db53 Pass endian information to constructors. Define separate functions to create
objects for big endian and little endian targets.

Patch by Jack Carter.

llvm-svn: 151788
2012-03-01 01:53:15 +00:00
Jia Liu 9f6101191b remove Emacs-tag form .cpp files in Mips Backend, and fix some typo.
llvm-svn: 150805
2012-02-17 08:55:11 +00:00
Jia Liu dd6c1cd4e8 add Emacs tag and fix some comment error in file headers
llvm-svn: 150775
2012-02-17 01:23:50 +00:00
Owen Anderson d845d9d9e9 Widen the instruction encoder that TblGen emits to a 64 bits, which should accomodate every target I can think of offhand.
llvm-svn: 148833
2012-01-24 18:37:29 +00:00
David Blaikie 46a9f016c5 More dead code removal (using -Wunreachable-code)
llvm-svn: 148578
2012-01-20 21:51:11 +00:00
Akira Hatanaka e2eed9649e Local dynamic TLS model for direct object output. Create the correct TLS MIPS
ELF relocations.

Patch by Jack Carter.

llvm-svn: 147118
2011-12-22 01:05:17 +00:00
Bruno Cardoso Lopes 56b70de01b Variable cleanup. Based on past patch submittals variable names have
been normalized and more descriptive comments added. Patch by Reed
Kotler and Jack Carter.

llvm-svn: 146088
2011-12-07 22:35:30 +00:00
Bruno Cardoso Lopes 61e6d987bf Add a few moreLocal/Global R_MIPS_GOT related fixups and
make the addend fixup code a bit more generic

Patch by Jack Carter.

llvm-svn: 145998
2011-12-07 00:28:57 +00:00
Akira Hatanaka 049e9e4d22 This patch makes the following changes necessary for MIPS' direct code emission.
- lower unaligned loads/stores.
- encode the size operand of instructions INS and EXT.
- emit relocation information needed for JAL (jump-and-link).  

llvm-svn: 145113
2011-11-23 22:19:28 +00:00
Bruno Cardoso Lopes c85e3ff334 Mips MC object code emission improvements:
"With this patch we can now generate runnable Mips code through LLVM
direct object emission. We have run numerous simple programs, both C
and C++ and with -O0 and -O3 from the output. The code is not production
ready, but quite useful for experimentation." Patch and message by
Jack Carter

llvm-svn: 144414
2011-11-11 22:58:42 +00:00
Akira Hatanaka 750ecec7d5 Initial implementation of MipsMCCodeEmitter.
Patch by Reed Kotler at Mips Technologies.

llvm-svn: 140878
2011-09-30 20:40:03 +00:00