d782d05666
R600: Move trivial getters into header, use initializer list
...
llvm-svn: 211917
2014-06-27 17:57:00 +00:00
642d2e78b3
R600: Don't crash on unhandled instruction in promote alloca
...
llvm-svn: 211906
2014-06-27 16:52:49 +00:00
6f62cf80d0
Fix missing newline and simplify debug printing.
...
llvm-svn: 211850
2014-06-27 02:36:59 +00:00
961ca43180
R600: Move load/store ReplaceNodeResults to common code.
...
Future patches will want to custom lower loads on SI.
llvm-svn: 211848
2014-06-27 02:33:47 +00:00
0989d51520
R600/SI: Add FP mode bits to binary.
...
The default rounding mode to initialize the mode register needs
to be reported to the runtime. Fill in other bits a kernel
may be interested in setting for future use.
llvm-svn: 211791
2014-06-26 17:22:30 +00:00
3c81e46b57
Silencing a warning about isZExtFree hiding an inherited virtual function. No functional change intended.
...
llvm-svn: 211783
2014-06-26 13:45:47 +00:00
c6f8fdb4e5
R600: Fix vector FMA
...
llvm-svn: 211757
2014-06-26 01:28:05 +00:00
b02c268cbd
R600/SI: Use a ComplexPattern for MUBUF stores
...
Now that non-leaf ComplexPatterns are allowed we can fold all the MUBUF
store patterns into the instruction definition. We will also be able to
reuse this new ComplexPattern for MUBUF loads and atomic operations.
llvm-svn: 211644
2014-06-24 23:33:07 +00:00
9b3816b5ee
R600: Promote i64 stores to v2i32
...
Now we need only one 64-bit pattern for stores.
llvm-svn: 211643
2014-06-24 23:33:04 +00:00
257d48d22c
R600: Fix inconsistency in rsq instructions.
...
R600 was using a clamped version of rsq, but SI was not. Add a
new rsq_clamped intrinsic and use them consistently.
It's unclear to me from the documentation what behavior
the R600 instructions have, so I assume they have the legacy behavior
described by the SI documents. For R600, use RECIPSQRT_IEEE
for both llvm.AMDGPU.rsq.legacy and llvm.AMDGPU.rsq. R600 also
has RECIPSQRT_FF, which I'm not sure how it fits in here.
llvm-svn: 211637
2014-06-24 22:13:39 +00:00
d40b970616
R600: Remove DIV_INF
...
This corresponded to an amdil instruction which there is
a 2 instruction equivalent for.
llvm-svn: 211616
2014-06-24 17:42:16 +00:00
bd469d5e67
R600/SI: Move pattern to instruction definition
...
llvm-svn: 211614
2014-06-24 17:17:06 +00:00
becb140324
R600/SI: Verify restrictions on div_scale operands.
...
llvm-svn: 211524
2014-06-23 18:28:31 +00:00
f2b0aebb8a
R600/SI: Fix div_scale intrinsic.
...
The operand that must match one of the others does matter,
and implement selecting for it.
llvm-svn: 211523
2014-06-23 18:28:28 +00:00
1d555c4e91
R600: Remove AMDILISelLowering
...
llvm-svn: 211519
2014-06-23 18:00:55 +00:00
d5f91fd883
R600: Select is not expensive.
...
llvm-svn: 211518
2014-06-23 18:00:52 +00:00
c4d3d3a16e
R600: Move add/sub with overflow out of AMDILISelLowering
...
Add more tests for these.
llvm-svn: 211517
2014-06-23 18:00:49 +00:00
e54e1c3a21
R600: Move more out of AMDILISelLowering
...
llvm-svn: 211516
2014-06-23 18:00:44 +00:00
72573adbf2
R600: Don't set fp_round_inreg action.
...
There's no point in setting this since it seems to only
by created in 1 place for ppcf128
llvm-svn: 211515
2014-06-23 18:00:41 +00:00
b8b5153935
R600/SI: Handle i64 sub.
...
We can handle it the same way as add
llvm-svn: 211514
2014-06-23 18:00:38 +00:00
9fa3f93173
R600/SI: Move selection of i64 add to separate function.
...
Also don't use a SmallVector for fixed size array.
llvm-svn: 211513
2014-06-23 18:00:34 +00:00
c791f39912
R600: Rename AMDIL file
...
llvm-svn: 211512
2014-06-23 18:00:31 +00:00
f4d871b113
Fix missing words in sentence
...
llvm-svn: 211511
2014-06-23 18:00:26 +00:00
762ef017db
Use helper function
...
llvm-svn: 211510
2014-06-23 18:00:24 +00:00
236d9afd18
Alphabetize forward declarations
...
llvm-svn: 211509
2014-06-23 18:00:20 +00:00
343cd6f056
R600: Use LowerSDIVREM for i64 node replace
...
v2: move div/rem node replacement to R600ISelLowering
make lowerSDIVREM protected
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
llvm-svn: 211478
2014-06-22 21:43:01 +00:00
109efdff6a
R600: Implement custom SDIVREM.
...
Instead of separate SDIV/SREM. SDIV used UDIV which in turn used UDIVREM anyway.
SREM used SDIV(UDIV->UDIVREM)+MUL+SUB, using UDIVREM directly is more efficient.
v2: Don't use all caps names
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
llvm-svn: 211477
2014-06-22 21:43:00 +00:00
ae4c9e7bc3
R600/SI: Add patterns for ctpop inside a branch
...
llvm-svn: 211378
2014-06-20 17:06:11 +00:00
9c603ebca4
R600/SI: Add a pattern for f32 ftrunc
...
llvm-svn: 211377
2014-06-20 17:06:09 +00:00
a79e9f0f6d
R600: Expand vector flog2
...
llvm-svn: 211376
2014-06-20 17:06:07 +00:00
5222a88653
R600: Expand vector fexp2
...
llvm-svn: 211375
2014-06-20 17:06:05 +00:00
de16a2e59f
R600/SI: SI Control Flow Annotation bug fixed
...
Mixing of AddAvailableValue and GetValueAtEndOfBlock methods of SSAUpdater
leaded to the endless loop generation when the nested loops annotated.
This fixes a bug in the OCL_ML/KNN OpenCV test. The test case is too
complex for FileCheck and would be very fragile.
Patch by: Elena Denisova
llvm-svn: 211374
2014-06-20 17:06:02 +00:00
c9dedb8e29
R600/SI: Add a VALU pattern for i64 xor
...
llvm-svn: 211373
2014-06-20 17:05:57 +00:00
f5e2997aff
R600: Trivial subtarget feature cleanups.
...
Remove an unused AMDIL leftover, correct extra periods
appearing in the help menu.
llvm-svn: 211341
2014-06-20 06:50:05 +00:00
1d099d9339
Fix typos
...
llvm-svn: 211304
2014-06-19 19:41:26 +00:00
35b2f75733
Convert some assert(0) to llvm_unreachable or fold an 'if' condition into the assert.
...
llvm-svn: 211254
2014-06-19 06:10:58 +00:00
a0050b0961
R600/SI: Add intrinsics for various math instructions.
...
These will be used for custom lowering and for library
implementations of various math functions, so it's useful
to expose these as builtins.
llvm-svn: 211247
2014-06-19 01:19:19 +00:00
2b0fa433a0
Use stdint macros for specifying size of constants
...
llvm-svn: 211231
2014-06-18 22:11:03 +00:00
692bd5ec2f
R600: Handle fnearbyint
...
The difference from rint isn't really relevant here,
so treat them as equivalent. OpenCL doesn't have nearbyint,
so this is sort of pointless other than for completeness.
llvm-svn: 211229
2014-06-18 22:03:45 +00:00
51b8e7b2e7
R600/SI: add gather4 and getlod intrinsics (v3)
...
This contains all the previous patches + getlod support on top of it.
It doesn't use SDNodes anymore, so it's quite small.
It also adds v16i8 to SReg_128, which is used for the sampler descriptor.
Reviewed-by: Tom Stellard
llvm-svn: 211228
2014-06-18 22:00:29 +00:00
b55c68f171
Use LL suffix for literal that should be 64-bits.
...
This hopefully fixes Windows
llvm-svn: 211225
2014-06-18 21:40:43 +00:00
85f0dbce5c
R600: Expand vector fceil
...
Move fp64 fceil tests to fceil64.ll
v2: rebase
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
llvm-svn: 211194
2014-06-18 17:57:29 +00:00
d22626f6bb
Work around ridiculous warning.
...
Apparently C++ doesn't really have hex floating point constants.
llvm-svn: 211192
2014-06-18 17:45:58 +00:00
43160e7af2
R600/SI: Add intrinsics for brev instructions
...
llvm-svn: 211187
2014-06-18 17:13:57 +00:00
dbc9aae1fb
R600/SI: Prettier operand printing for 64-bit ops.
...
Copy what is done for 32-bit already so the order is about the same.
llvm-svn: 211186
2014-06-18 17:13:51 +00:00
4601093267
R600: Implement f64 ftrunc, ffloor and fceil.
...
CI has instructions for these, so this fixes them for older hardware.
llvm-svn: 211183
2014-06-18 17:05:30 +00:00
e8208ec95b
R600: Custom lower f64 frint for pre-CI
...
llvm-svn: 211182
2014-06-18 17:05:26 +00:00
7aeb813b2a
R600/SI: Temporary fix for f64 fneg
...
This should be a source modifier, but this unblocks
most of my math patches.
llvm-svn: 211181
2014-06-18 17:05:22 +00:00
520e7c44c1
R600/SI: Comparisons set vcc.
...
llvm-svn: 211178
2014-06-18 16:53:48 +00:00
ecf5133a2b
R600: Implement 64bit SRA
...
v2: Use capitalized variable name
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
llvm-svn: 211159
2014-06-18 12:27:17 +00:00
Matt Arsenault