f39120571b
Thumb-2 only support [base_reg + offset_reg] addressing, not [base_reg - offset_reg].
...
llvm-svn: 75789
2009-07-15 15:50:19 +00:00
eb8c83b4c3
Replace large swaths of copy-n-paste code with obvious helper function...
...
- Which was already present in the module!
- I skipped this xform for Alpha, since it runs an extra pass during assembly
emission, but not when emitting assembly via the DumpAsm flag.
- No functionality change.
--
ddunbar@giles:llvm$ svn diff | grep '^- ' | sort | uniq -c
18 - PM.add(AsmPrinterCtor(ferrs(), *this, true));
18 - assert(AsmPrinterCtor && "AsmPrinter was not linked in");
18 - if (AsmPrinterCtor)
18 - if (DumpAsm) {
18 - }
ddunbar@giles:llvm$ svn diff | grep '^+ ' | sort | uniq -c
18 + addAssemblyEmitter(PM, OptLevel, true, ferrs());
18 + if (DumpAsm)
--
llvm-svn: 75782
2009-07-15 12:49:15 +00:00
863e587d27
Kill off old (TargetMachine level, not Target level) match quality functions.
...
llvm-svn: 75780
2009-07-15 12:26:05 +00:00
6db8134e80
Provide TargetMachine implementations with reference to Target they were created
...
from.
- This commit is almost entirely propogating the reference through the
TargetMachine subclasses' constructor calls.
llvm-svn: 75778
2009-07-15 12:11:05 +00:00
b22f50e4c4
Register Target's TargetMachine and AsmPrinter in the new registry.
...
- This abuses TargetMachineRegistry's constructor for now, this will get
cleaned up in time.
llvm-svn: 75762
2009-07-15 09:22:31 +00:00
56e2947a33
Add TargetInfo libraries for all targets.
...
- Intended to match current TargetMachine implementations.
- No facilities for linking these in yet.
llvm-svn: 75751
2009-07-15 06:35:19 +00:00
a2268c0b19
convert arm/darwin stubs to use the mangler to synthesize all the names instead of
...
doing it with printSuffixedName.
llvm-svn: 75741
2009-07-15 04:41:01 +00:00
55452c2bea
fix an arm codegen bug (the same as PR4482 on ppc) where available_externally
...
symbols were not getting stubs. While I'm at it, add a big testcase for
stub generation to make sure I don't break anything.
llvm-svn: 75737
2009-07-15 04:12:33 +00:00
53fe736214
convert [Hidden]GVNonLazyPtrs to compute the global and stub names
...
with the mangler (like x86 and ppc), instead of going through
printSuffixedName.
llvm-svn: 75736
2009-07-15 03:12:43 +00:00
b6b2530000
Move EVER MORE stuff over to LLVMContext.
...
llvm-svn: 75703
2009-07-14 23:09:55 +00:00
a9111b9f97
Fix bad indentation and 80-col violation.
...
llvm-svn: 75686
2009-07-14 21:45:58 +00:00
95bad85498
Check for PRE_INC and POST_INC.
...
llvm-svn: 75683
2009-07-14 21:29:29 +00:00
a31f96cf2b
Have asm printers use formatted_raw_ostream directly to avoid a
...
dynamic_cast<>.
llvm-svn: 75670
2009-07-14 20:18:05 +00:00
4ad7797e1c
hasThumb2() does not mean we are compiling for thumb, must also check isThumb().
...
llvm-svn: 75660
2009-07-14 18:48:51 +00:00
3f17aee94b
Remove an extra space.
...
llvm-svn: 75658
2009-07-14 18:44:34 +00:00
8c9a96b966
Reapply my previous asmprinter changes now with more testing and two
...
additional bug fixes:
1. The bug that everyone hit was a problem in the asmprinter where it
would remove $stub but keep the L prefix on a name when emitting the
indirect symbol. This is easy to fix by keeping the name of the stub
and the name of the symbol in a StringMap instead of just keeping a
StringSet and trying to reconstruct it late.
2. There was a problem printing the personality function. The current
logic to print out the personality function from the DWARF information
is a bit of a cesspool right now that duplicates a bunch of other
logic in the asm printer. The short version of it is that it depends
on emitting both the L and _ prefix for symbols (at least on darwin)
and until I can untangle it, it is best to switch the mangler back to
emitting both prefixes.
llvm-svn: 75646
2009-07-14 18:17:16 +00:00
fbcc663cbf
llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable.
...
This adds location info for all llvm_unreachable calls (which is a macro now) in
!NDEBUG builds.
In NDEBUG builds location info and the message is off (it only prints
"UREACHABLE executed").
llvm-svn: 75640
2009-07-14 16:55:14 +00:00
6c5282e3db
Revert r75615, which depended on 75610.
...
--- Reverse-merging r75615 into '.':
U lib/Target/XCore/XCoreAsmPrinter.cpp
U lib/Target/PIC16/PIC16AsmPrinter.cpp
U lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp
U lib/Target/MSP430/MSP430AsmPrinter.cpp
U lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp
U lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp
U lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
U lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp
U lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp
U lib/Target/MSIL/MSILWriter.cpp
U lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp
U lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp
llvm-svn: 75637
2009-07-14 16:12:13 +00:00
027c84d2c8
Rename getValueName -> getMangledName.
...
llvm-svn: 75615
2009-07-14 06:18:50 +00:00
bd9ba429ca
1. In Thumb mode, select tBx instead of ARM variants.
...
2. BX does not "use" the link register, it defines it.
3. Fix a couple more places in thumb td file that still uses pre-UAL syntax.
llvm-svn: 75585
2009-07-14 01:49:27 +00:00
72b80ac9b1
Fix detection of valid BFC immediates.
...
llvm-svn: 75576
2009-07-14 00:57:56 +00:00
7bbb9a91ab
Fix an obvious copy-and-paste error.
...
llvm-svn: 75566
2009-07-14 00:23:44 +00:00
acb9927fd8
Revert 75309.
...
llvm-svn: 75562
2009-07-14 00:01:42 +00:00
160521095b
Fix FP elimination code to work for Thumb-2 addrmode AddrModeT2_so. This fixes SingleSource/Benchmarks/Stanford/Queens (among others).
...
llvm-svn: 75513
2009-07-13 21:43:08 +00:00
844d6c82a7
Fix comment typos.
...
llvm-svn: 75479
2009-07-13 18:11:36 +00:00
69208f0f9e
Remove extra \n from LLVM_UNREACHABLE calls.
...
llvm-svn: 75416
2009-07-12 07:15:17 +00:00
56d0659726
assert(0) -> LLVM_UNREACHABLE.
...
Make llvm_unreachable take an optional string, thus moving the cerr<< out of
line.
LLVM_UNREACHABLE is now a simple wrapper that makes the message go away for
NDEBUG builds.
llvm-svn: 75379
2009-07-11 20:10:48 +00:00
017288a4fc
Don't put IT instruction before conditional branches.
...
llvm-svn: 75361
2009-07-11 07:26:20 +00:00
0794c6a083
Smarter isel of ldrsb / ldrsh. Only make use of these when [r,r] address is feasible.
...
llvm-svn: 75360
2009-07-11 07:08:13 +00:00
cd4cdd1157
Major changes to Thumb (not Thumb2). Many 16-bit instructions either modifies CPSR when they are outside the IT blocks, or they can predicated when in Thumb2. Move the implicit def of CPSR to an optional def which defaults CPSR. This allows the 's' bit to be toggled dynamically.
...
A side-effect of this change is asm printer is now using unified assembly. There are some minor clean ups and fixes as well.
llvm-svn: 75359
2009-07-11 06:43:01 +00:00
bf041366c4
80 col violation.
...
llvm-svn: 75358
2009-07-11 06:37:27 +00:00
a51f8ebf1a
Add superclasses of ARM Neon quad registers. The Q2PR class contains pairs of
...
quad registers and the Q4PR class holds sets of 4 quad registers.
llvm-svn: 75309
2009-07-10 23:09:06 +00:00
81cdd21dcb
Predicate VFP instructions on HasVFP2 instead of IsARM. This allows VFP instructions with thumb-2.
...
llvm-svn: 75254
2009-07-10 17:03:29 +00:00
c9b1efd515
t2LDM_RET does not fall-through.
...
llvm-svn: 75250
2009-07-10 15:33:46 +00:00
0006349f4d
Add Thumb2ITBlockPass.cpp to CMakeLists.txt, fixing
...
the cmake build.
llvm-svn: 75246
2009-07-10 08:31:50 +00:00
01b8630879
More info about Thumb1 predication support.
...
llvm-svn: 75220
2009-07-10 02:10:17 +00:00
61671c87a7
We don't need separate thumb1 instructions tADDSi3 etc. for addc and subc. The "normal" version always modify condition register CPSR so we should just use def : pat to match to the same instructions.
...
llvm-svn: 75219
2009-07-10 02:09:04 +00:00
0f9cce7951
Add a thumb2 pass to insert IT blocks.
...
llvm-svn: 75218
2009-07-10 01:54:42 +00:00
3b88dd6900
Move isPredicated from .cpp to .h
...
llvm-svn: 75217
2009-07-10 01:38:27 +00:00
5d8a1b2c18
80 col violation.
...
llvm-svn: 75212
2009-07-10 00:45:16 +00:00
223ac25930
Remove a bogus assertion.
...
llvm-svn: 75206
2009-07-10 00:23:48 +00:00
75aa75cabc
Replace TM.getRegisterInfo() calls by TRI instance variable.
...
Use getAsmName() method instead of accessing AsmName field directly.
llvm-svn: 75205
2009-07-10 00:14:05 +00:00
9ce44e2521
Handle 'a' modifier on inline assembly operands.
...
This is part of the fix for pr4521.
llvm-svn: 75201
2009-07-09 23:54:51 +00:00
26b2ba4285
Added Thumb IT instruction.
...
llvm-svn: 75198
2009-07-09 23:43:36 +00:00
ae4f2e142a
Another todo entry.
...
llvm-svn: 75192
2009-07-09 23:17:28 +00:00
4605e8aac4
Initial support for load / store multiple opt pass Thumb2 support (post-allocation only). It's kind of there, but not quite. I'll return to this later.
...
llvm-svn: 75190
2009-07-09 23:11:34 +00:00
1622d7b429
Fix ldm / stm unified syntax; add t2LDM_RET.
...
llvm-svn: 75188
2009-07-09 22:58:39 +00:00
a02fc2d327
LDM_RET should be marked mayLoad.
...
llvm-svn: 75187
2009-07-09 22:57:41 +00:00
7591d02c84
Fix ldrd / strd address mode matching code. It allows for +/- 8 bit offset. Also change the printer to make the scale 4 explicit.
...
Note, we are not yet generating these instructions.
llvm-svn: 75181
2009-07-09 22:21:59 +00:00
f9870125fc
Add a Thumb readme entry.
...
llvm-svn: 75173
2009-07-09 20:50:52 +00:00
ad93707e16
Correct comment.
...
llvm-svn: 75172
2009-07-09 20:40:44 +00:00
7bf08beb2e
Handle Thumb-2 addressing modes during FP elimination.
...
llvm-svn: 75158
2009-07-09 18:35:52 +00:00
0504e0a222
Thread LLVMContext through MVT and related parts of SDISel.
...
llvm-svn: 75153
2009-07-09 17:57:24 +00:00
27e32c092e
Reorg includes.
...
llvm-svn: 75115
2009-07-09 06:49:09 +00:00
22c2fba978
Use common code for both ARM and Thumb-2 instruction and register info.
...
llvm-svn: 75067
2009-07-08 23:10:31 +00:00
5edd90cbbc
- Add some NEON ld / st instruction static encoding.
...
- Make bits 25-27 for ldrh, etc. explicitly zero. Previously only the JIT uses the encoding information and it's assuming anything not specified to be zero. Making them explicit so the disassembler is happy.
Patch by Sean Callanan.
llvm-svn: 75065
2009-07-08 22:51:32 +00:00
e3a53c448b
Change how so_imm and t2_so_imm are handled. At instruction selection time, the immediates are no longer encoded in the imm8 + rot format, that are left as it is. The encoding is now done in ams printing and code emission time instead.
...
llvm-svn: 75048
2009-07-08 21:03:57 +00:00
f8d479c1ce
Missed an exit during the conversion.
...
Will convert assert(0) that don't have abort() to LLVM_UNREACHABLE in a later
commit.
llvm-svn: 75045
2009-07-08 20:55:50 +00:00
fb8d6d5b58
Implement changes from Chris's feedback.
...
Finish converting lib/Target.
llvm-svn: 75043
2009-07-08 20:53:28 +00:00
1d298fd75b
Implement NEON vst1 instruction.
...
llvm-svn: 75037
2009-07-08 20:32:02 +00:00
03ab0bbb24
Generalize opcode selection in ARMBaseRegisterInfo.
...
llvm-svn: 75036
2009-07-08 20:28:28 +00:00
b009980f0b
Fix cmake build.
...
Added ARMBaseRegisterInfo.cpp to lib/Target/ARM/CMakeLists.txt
llvm-svn: 75035
2009-07-08 20:13:41 +00:00
9ca33e8a9f
Push methods into base class in preparation for sharing.
...
llvm-svn: 75020
2009-07-08 18:31:39 +00:00
f731a2df6b
Implement NEON vld1 instructions.
...
llvm-svn: 75019
2009-07-08 18:11:30 +00:00
6dd2730024
Start converting to new error handling API.
...
cerr+abort -> llvm_report_error
assert(0)+abort -> LLVM_UNREACHABLE (assert(0)+llvm_unreachable-> abort() included)
llvm-svn: 75018
2009-07-08 18:01:40 +00:00
eebf58805c
Start breaking out common base functionality for register info.
...
llvm-svn: 75016
2009-07-08 17:28:55 +00:00
af7451b674
Checkpoint Thumb2 Instr info work. Generalized base code so that it can be shared between ARM and Thumb2. Not yet activated because register information must be generalized first.
...
llvm-svn: 75010
2009-07-08 16:09:28 +00:00
a21d3daadc
Remove the vicmp and vfcmp instructions. Because we never had a release with
...
these instructions, no autoupgrade or backwards compatibility support is
provided.
llvm-svn: 74991
2009-07-08 03:04:38 +00:00
14965760a7
Add a Thumb2 instruction flag to that indicates whether the instruction can be transformed to 16-bit variant.
...
llvm-svn: 74988
2009-07-08 01:46:35 +00:00
b61e3a83ee
Add a todo.
...
llvm-svn: 74976
2009-07-08 00:05:05 +00:00
f0080b734a
Also statically set bit 25 for BR_JT instructions.
...
llvm-svn: 74974
2009-07-07 23:45:10 +00:00
2cff076cfe
Statically encode bit 25 to indicate immediate form of data processing instructions. Patch by Sean Callanan.
...
llvm-svn: 74972
2009-07-07 23:40:25 +00:00
d0611f9a37
Add Thumb2 movcc instructions.
...
llvm-svn: 74946
2009-07-07 20:39:03 +00:00
02a44edf12
Add BX and BXr9 encodings. Patch by Sean Callanan.
...
llvm-svn: 74938
2009-07-07 19:16:24 +00:00
d0f6324cdc
Add Thumb2 pkhbt / pkhtb.
...
llvm-svn: 74895
2009-07-07 05:35:52 +00:00
b24e51e2d9
Add some more Thumb2 multiplication instructions.
...
llvm-svn: 74889
2009-07-07 01:17:28 +00:00
7c9434399d
80 col violation.
...
llvm-svn: 74888
2009-07-07 01:16:41 +00:00
3d8ccdb4be
isThumb2 really should mean thumb2 only, not thumb2+.
...
llvm-svn: 74871
2009-07-06 22:29:14 +00:00
40398233b7
Add bfc to armv6t2.
...
llvm-svn: 74868
2009-07-06 22:23:46 +00:00
e63b0e6f79
Added ARM::mls for armv6t2.
...
llvm-svn: 74866
2009-07-06 22:05:45 +00:00
5661ea68e7
Add the Object Code Emitter class. Original patch by Aaron Gray, I did some
...
cleanup, removed some #includes and moved Object Code Emitter out-of-line.
llvm-svn: 74813
2009-07-06 05:09:34 +00:00
aea6059ed4
Add NumFixedArgs attribute to CallSDNode which indicates the number of fixed arguments in a vararg call.
...
With the SVR4 ABI on PowerPC, vector arguments for vararg calls are passed differently depending on whether they are a fixed or a variable argument. Variable vector arguments always go into memory, fixed vector arguments are put
into vector registers. If there are no free vector registers available, fixed vector arguments are put on the stack.
The NumFixedArgs attribute allows to decide for an argument in a vararg call whether it belongs to the fixed or variable portion of the parameter list.
llvm-svn: 74764
2009-07-03 06:44:53 +00:00
0e8bde5910
Add thumb2 sign / zero extend with rotate instructions.
...
llvm-svn: 74755
2009-07-03 01:43:10 +00:00
6d9041100b
Add Thumb2 load / store multiple instructions. Not used yet.
...
llvm-svn: 74749
2009-07-03 00:18:36 +00:00
f30ee8820a
t2LDR_PRE etc are loads.
...
llvm-svn: 74741
2009-07-03 00:08:19 +00:00
53cdf022b6
Added indexed stores.
...
llvm-svn: 74740
2009-07-03 00:06:39 +00:00
8ecd7eb3f7
Sign extending pre/post indexed loads.
...
llvm-svn: 74736
2009-07-02 23:16:11 +00:00
ade05a37f1
Checkpoint refactoring of ThumbInstrInfo and ThumbRegisterInfo into Thumb1InstrInfo, Thumb2InstrInfo, Thumb1RegisterInfo and Thumb2RegisterInfo. Move methods from ARMInstrInfo to ARMBaseInstrInfo to prepare for sharing with Thumb2.
...
llvm-svn: 74731
2009-07-02 22:18:33 +00:00
6141511621
CMake build fixes, from Xerxes Ranby
...
llvm-svn: 74720
2009-07-02 18:53:52 +00:00
84c6cda2ef
Thumb2 pre/post indexed loads.
...
llvm-svn: 74696
2009-07-02 07:28:31 +00:00
844f0b4562
80 col violation.
...
llvm-svn: 74693
2009-07-02 06:44:30 +00:00
2c450d35ae
Change the meaning of predicate hasThumb2 to mean thumb2 ISA is available, not that it's in thumb mode and thumb2 is available. Added isThumb2 predicate to replace the old predicate.
...
llvm-svn: 74692
2009-07-02 06:38:40 +00:00
979da0e590
80 col violation.
...
llvm-svn: 74683
2009-07-02 01:30:04 +00:00
d9c55368e7
Factor out ARM indexed load matching code.
...
llvm-svn: 74681
2009-07-02 01:23:32 +00:00
deb35afd23
Add a new addressing mode for NEON load/store instructions.
...
llvm-svn: 74658
2009-07-01 23:16:05 +00:00
affb68bd08
Fix a comment typo.
...
llvm-svn: 74650
2009-07-01 21:59:43 +00:00
bbbf805049
Fix up a comment: besides the >80col lines, the operation for this
...
addressing mode is encoded in the second operand, not the third.
llvm-svn: 74641
2009-07-01 21:22:45 +00:00
512ff7353e
Update comments to make it clear that the function alignment is the Log2 of the
...
bytes and not bytes.
llvm-svn: 74624
2009-07-01 18:50:55 +00:00
d379e896ff
Handle IMPLICIT_DEF with isUndef operand marker, part 2. This patch moves the code to annotate machineoperands to LiveIntervalAnalysis. It also add markers for implicit_def that define physical registers. The rest, is just a lot of details.
...
llvm-svn: 74580
2009-07-01 01:59:31 +00:00
75c12e1569
Remove unused AsmPrinter OptLevel argument, and propogate.
...
- This more or less amounts to a revert of r65379. I'm curious to know what
happened that caused this variable to become unused.
llvm-svn: 74579
2009-07-01 01:48:54 +00:00
86c7e20ca6
Add PIC load and store patterns for Thumb-2.
...
llvm-svn: 74577
2009-07-01 00:01:13 +00:00
a83100f687
Thumb-2 load and store double description. But nothing yet creates them.
...
llvm-svn: 74566
2009-06-30 22:50:01 +00:00
31ceb1bcba
Add an "alignment" field to the MachineFunction object. It makes more sense to
...
have the alignment be calculated up front, and have the back-ends obey whatever
alignment is decided upon.
This allows for future work that would allow for precise no-op placement and the
like.
llvm-svn: 74564
2009-06-30 22:38:32 +00:00
d0890a2bad
Add thumb-2 store word, halfword, and byte.
...
llvm-svn: 74555
2009-06-30 22:11:34 +00:00
28d6d87244
Improve Thumb-2 jump table support.
...
llvm-svn: 74549
2009-06-30 19:50:22 +00:00
27303cde82
Add conditional and unconditional thumb-2 branch. Add thumb-2 jump table.
...
llvm-svn: 74543
2009-06-30 18:04:13 +00:00
57726817aa
A few more load instructions.
...
llvm-svn: 74500
2009-06-30 02:15:48 +00:00
76b37950ca
Add Thumb-2 support for TEQ amd TST.
...
llvm-svn: 74468
2009-06-29 22:49:42 +00:00
dbf11ba800
Rename ARMcmpNZ to ARMcmpZ and use it to represent comparisons that set only the Z flag (i.e. eq and ne). Make ARMcmpZ commutative.
...
llvm-svn: 74423
2009-06-29 15:33:01 +00:00
24a3724b04
Include the new file ThumbRegisterInfo.cpp to CMakeLists.txt
...
to make sure ThumbRegisterInfo.cpp are compiled and linked in.
Patch by Xerxes.
llvm-svn: 74421
2009-06-29 13:11:32 +00:00
b23b50d54d
Implement Thumb2 ldr.
...
After much back and forth, I decided to deviate from ARM design and split LDR into 4 instructions (r + imm12, r + imm8, r + r << imm12, constantpool). The advantage of this is 1) it follows the latest ARM technical manual, and 2) makes it easier to reduce the width of the instruction later. The down side is this creates more inconsistency between the two sub-targets. We should split ARM LDR instruction in a similar fashion later. I've added a README entry for this.
llvm-svn: 74420
2009-06-29 07:51:04 +00:00
0f2158b35f
Simplify a bit
...
llvm-svn: 74385
2009-06-27 12:59:03 +00:00
a1b5b18bd0
ARM refactoring. Step 2: split RegisterInfo
...
llvm-svn: 74384
2009-06-27 12:16:40 +00:00
33400e3670
Add ThumbInstrInfo.cpp to the CMake makefiles
...
llvm-svn: 74382
2009-06-27 07:44:59 +00:00
eab9ca7ea6
Renaming for consistency.
...
llvm-svn: 74368
2009-06-27 02:26:13 +00:00
5d8b6eef5a
Remove outdated comment.
...
llvm-svn: 74357
2009-06-26 23:39:02 +00:00
5285817490
When possible, use "mvn ra, rb" instead of "eor ra, rb, -1" because mvn has a narrow version and eor(i) does not.
...
llvm-svn: 74355
2009-06-26 23:13:13 +00:00
99152f3a2c
Split thumb-related stuff into separate classes.
...
Step 1: ARMInstructionInfo => {ARM,Thumb}InstructionInfo
llvm-svn: 74329
2009-06-26 21:28:53 +00:00
aa294c5593
Thumb-2 has CLZ.
...
llvm-svn: 74322
2009-06-26 20:47:43 +00:00
35ee722d42
Use "adcs/sbcs" only when the carry-out is live, otherwise use "adc/sbc".
...
llvm-svn: 74321
2009-06-26 20:45:56 +00:00
5960e6d974
ADC used to implement adde should use "adcs" opcode instead of "adc".
...
llvm-svn: 74293
2009-06-26 18:07:25 +00:00
0377f737ff
Currently there is a pattern for the thumb-2 MOV 16-bit immediate instruction. That instruction cannot write the flags so it should use T2I instead of T2sI.
...
Also, added a pattern for the thumb-2 MOV of shifted immediate since that can encode immediates not encodable by the 16-bit immediate.
llvm-svn: 74288
2009-06-26 16:10:07 +00:00
1eda63715f
Simplify predicate CarryDefIsUsed.
...
llvm-svn: 74277
2009-06-26 06:10:18 +00:00
2cc6d183b2
Let's ignore MDStrings also!
...
llvm-svn: 74255
2009-06-26 02:26:12 +00:00
e2c4d35f3e
Add a note about commuting conditional move.
...
llvm-svn: 74241
2009-06-26 00:28:48 +00:00
cf661fc12a
These are done / no longer applicable.
...
llvm-svn: 74239
2009-06-26 00:25:27 +00:00
5bf9011c2d
Mark a bunch of instructions commutable.
...
llvm-svn: 74237
2009-06-26 00:19:44 +00:00
9643ba8123
tst is also commutable.
...
llvm-svn: 74236
2009-06-26 00:19:07 +00:00
97727a61f9
Select ADC, SBC, and RSC instead of the ADCS, SBCS, and RSCS when the carry bit def is not used.
...
llvm-svn: 74228
2009-06-25 23:34:10 +00:00
16f357cccf
Use MVN for ~t2_so_imm immediates.
...
llvm-svn: 74223
2009-06-25 23:11:21 +00:00
e85169cd1b
Add Def/Use of CPSR for Thumb-1 instructions.
...
llvm-svn: 74219
2009-06-25 22:49:55 +00:00
7e687191fd
Unbreak mingw build. Patch by Viktor Kutuzov.
...
llvm-svn: 74212
2009-06-25 22:04:44 +00:00
c7ea8df67e
ISD::ADDE / ISD::SUBE updates the carry bit so they should isle to ADCS and SBCS / RSCS.
...
llvm-svn: 74200
2009-06-25 20:59:23 +00:00
e892e8bfaf
Test commit
...
llvm-svn: 74185
2009-06-25 17:52:32 +00:00
8f74c88cb6
Revert 74164. We'll want to use this method later.
...
llvm-svn: 74176
2009-06-25 16:03:07 +00:00
350abb9799
Remove unused hasV6T2Ops method. We already have a separate feature to
...
identify Thumb2.
llvm-svn: 74164
2009-06-25 05:20:31 +00:00
2042c3519d
Add missing dependencies to the CMake build system.
...
llvm-svn: 74161
2009-06-25 05:03:06 +00:00
d76f0be844
Change thumb2 instruction definitions so if-converter so add predicate operands and / or flip the 's' bit to set the condition flag.
...
llvm-svn: 74158
2009-06-25 02:08:06 +00:00
6ea7ad0351
Add thumb2 add sp.
...
llvm-svn: 74156
2009-06-25 01:21:30 +00:00
b566ab7b97
Some reorg and additional comments.
...
llvm-svn: 74152
2009-06-25 01:05:06 +00:00
9d68302e48
No need to code gen MDNodes
...
llvm-svn: 74150
2009-06-25 00:47:42 +00:00
83f979a48b
Add Thumb2 pc relative add.
...
llvm-svn: 74141
2009-06-24 23:47:58 +00:00
4c048fe5ad
80 col violation.
...
llvm-svn: 74138
2009-06-24 23:14:45 +00:00
70413126b6
sink dwarf finalization out of each target into AsmPrinter::doFinalization
...
llvm-svn: 74097
2009-06-24 18:54:37 +00:00
2981dc1742
eliminate the ExtWeakSymbols set from AsmPrinter. This eliminates
...
a bunch of code from all the targets, and eliminates nondeterministic
ordering of directives being emitted in the output.
llvm-svn: 74096
2009-06-24 18:52:01 +00:00
443af01b1a
Unbreak build on Linux by removing Darwinism.
...
llvm-svn: 74046
2009-06-24 01:08:42 +00:00
a3d375845e
Revert this accidental commit.
...
llvm-svn: 74042
2009-06-24 00:55:55 +00:00
f436bacb6b
Move the special cases for constants out of getUnknown and into
...
createSCEV. Also, recognize UndefValue in createSCEV.
Change getIntegerSCEV's comment to avoid mentioning FP types,
and re-implement it in terms of getConstant instead of getUnknown.
llvm-svn: 74041
2009-06-24 00:54:57 +00:00
5a495fea07
Provide InitializeAllTargets and InitializeNativeTarget functions in the
...
C bindings. Change all the backend "Initialize" functions to have C linkage.
Change the "llvm/Config/Targets.def" header to use C-style comments to avoid
compile warnings.
llvm-svn: 74026
2009-06-23 23:59:40 +00:00
7d80d29187
Test instructions operands were printed in the wrong order.
...
llvm-svn: 73990
2009-06-23 19:56:37 +00:00
4983e4550e
Proper patterns for thumb2 shift and rotate instructions.
...
llvm-svn: 73987
2009-06-23 19:39:13 +00:00
8d21e9c4e6
Code clean up.
...
llvm-svn: 73986
2009-06-23 19:38:34 +00:00
bec1dba896
Add IsThumb1Only to most 16-bit thumb instructions since we want to isel 32-bit instructions when they are available.
...
llvm-svn: 73985
2009-06-23 19:38:13 +00:00
e379107cdc
Rename SelectShifterOperand to SelectThumb2ShifterOperandReg.
...
llvm-svn: 73975
2009-06-23 18:14:38 +00:00
85fedbe081
Eliminate object-relinking support from CMake. Fixes PR 4429 and
...
cleans up the CMake-based build system a bit. Started by a patch from
Xerxes Rånby.
llvm-svn: 73969
2009-06-23 17:57:35 +00:00
b45cebabc9
Obvious typo.
...
llvm-svn: 73967
2009-06-23 17:54:26 +00:00
431cf567de
Initial Thumb2 support. Majority of the work is done by David Goodwin. There are
...
also some contribution from Jim Grosbach, Bob Wilson, and Evan Cheng.
I've done my best to consolidate the patches with those that were done by
Viktor Kutuzov and Anton Korzh from Access Softek, Inc. Let me know if missed
anything. I've completely reorganized the thumb2 td file, made more extensive
uses of multiclass, etc.
Test cases will be contributed later after I re-organize what's in svn first.
llvm-svn: 73965
2009-06-23 17:48:47 +00:00
6a42ec3e70
Minor reorg.
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llvm-svn: 73948
2009-06-23 05:25:29 +00:00
022a726a25
Replace isTwoAddress with operand constraint.
...
llvm-svn: 73947
2009-06-23 05:23:49 +00:00
2e076c4e02
Add support for ARM's Advanced SIMD (NEON) instruction set.
...
This is still a work in progress but most of the NEON instruction set
is supported.
llvm-svn: 73919
2009-06-22 23:27:02 +00:00
e67b77028e
Add explicit types for shift count constants. This is in preparation for
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another change that makes the types ambiguous (at least as far as tablegen
is concerned).
llvm-svn: 73909
2009-06-22 22:08:29 +00:00
482495695e
Use thumb2 for ARM architectures V6T2 and later. Fix a bug in checking
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for "thumb" and add a check for V6T2.
llvm-svn: 73905
2009-06-22 21:28:22 +00:00
4582530a2c
For Darwin on ARMv6 and newer, make register r9 available for use as a
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caller-saved register.
llvm-svn: 73901
2009-06-22 21:01:46 +00:00
3d75d6af57
hasFP should return true if frame address is taken.
...
llvm-svn: 73893
2009-06-22 18:38:48 +00:00
360eef0782
Fix llvm-gcc build for armv6t2 and later architectures. The hasV6T2Ops
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predicate does not check if Thumb mode is enabled, and when in ARM mode
there are still some checks for constant-pool use that need to run.
llvm-svn: 73887
2009-06-22 17:29:13 +00:00
79ef65a271
Remove unused field.
...
llvm-svn: 73815
2009-06-20 01:07:54 +00:00
b4b20bbb7d
Enable arm pre-allocation load / store multiple optimization pass.
...
llvm-svn: 73791
2009-06-19 23:17:27 +00:00
33f4eb462f
Move up dwarf writer initialization in common AsmPrinter class.
...
llvm-svn: 73784
2009-06-19 21:54:26 +00:00
d305869ca2
Add comments.
...
llvm-svn: 73761
2009-06-19 07:06:07 +00:00
1592035e67
Should be using Bcc (average) latency to determine if-conversion threshold, not BL.
...
llvm-svn: 73759
2009-06-19 06:56:26 +00:00
5d8df7ff34
Transfer dead markers when a ldrd is changed into a ldm or a pair of ldr.
...
llvm-svn: 73749
2009-06-19 01:59:04 +00:00
4e712de541
Latency information for ARM v6. It's rough and not yet hooked up. Right now we are only using branch latency to determine if-conversion limits.
...
llvm-svn: 73747
2009-06-19 01:51:50 +00:00
d984158320
Mark a few Thumb instructions commutable; just happened to spot this
...
while experimenting. I'm reasonably sure this is correct, but please
tell me if these instructions have some strange property which makes this
change unsafe.
llvm-svn: 73746
2009-06-19 01:43:08 +00:00
8284b66264
merge the common darwin settings from the X86/PPC/ARM targets
...
into DarwinTargetAsmInfo.cpp. The remaining differences should
be evaluated. It seems strange that x86/arm has .zerofill but ppc
doesn't, etc.
llvm-svn: 73742
2009-06-19 00:08:39 +00:00
b84764516d
move mangler quote handling from asm printers to TargetAsmInfo.
...
llvm-svn: 73738
2009-06-18 23:41:35 +00:00
09081b25a5
simplify macro debug info directive handling.
...
llvm-svn: 73736
2009-06-18 23:31:37 +00:00
a0ca298f8a
Remove UseThumbBacktraces. Just check if subtarget is darwin.
...
llvm-svn: 73734
2009-06-18 23:14:30 +00:00
de9e36a74e
On Darwin, ams printer should output a second label before a jump table so the linker knows it's a new atom. But this is only needed if the jump table is put in a separate section from the function body.
...
llvm-svn: 73720
2009-06-18 20:37:15 +00:00
0e79603588
- Update register allocation hint after coalescing. This is done by the target since the hint is target dependent. This is important for ARM register pair hints.
...
- Register allocator should resolve the second part of the hint (register number) before passing it to the target since it knows virtual register to physical register mapping.
- More fixes to get ARM load / store double word working.
llvm-svn: 73671
2009-06-18 02:04:01 +00:00
86c12d7bc4
ARM unified syntax is not specific to ELF; use it for Darwin, too.
...
llvm-svn: 73665
2009-06-18 00:36:17 +00:00
5658086052
Fix asm string from MOVi16
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llvm-svn: 73661
2009-06-17 23:43:36 +00:00
f687a828b2
Thumb2 instructions are enabled only in unified assembler mode.
...
Emit switch directive for it. I have no idea whether this is
requirement for Darwin or not.
llvm-svn: 73660
2009-06-17 23:43:18 +00:00
02bb33c58d
Initial support for some Thumb2 instructions.
...
Patch by Viktor Kutuzov and Anton Korzh from Access Softek, Inc.
llvm-svn: 73622
2009-06-17 18:13:58 +00:00
1b731d5dbe
Introduce new headers whose inclusion forces linking and
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initialization of all targets (InitializeAllTargets.h) or assembler
printers (InitializeAllAsmPrinters.h). This is a step toward the
elimination of relinked object files, so that we can build normal
archives.
llvm-svn: 73543
2009-06-16 20:12:29 +00:00
a8fd40b50a
Address review comments: add 3 ARM calling conventions.
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Dispatch C calling conv. to one of these conventions based on
target triple and subtarget features.
llvm-svn: 73530
2009-06-16 18:50:49 +00:00
5d28cb204f
GNU as refuses to assemble "pop {}" instruction. Do not emit such
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(this is the case when we have thumb vararg function with single
callee-saved register, which is handled separately).
llvm-svn: 73529
2009-06-16 18:49:08 +00:00
f691b829ab
On Darwin, frame pointer r7 is never available.
...
llvm-svn: 73434
2009-06-15 22:32:01 +00:00
409105fc95
Rename methods for the sake of consistency.
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llvm-svn: 73428
2009-06-15 21:46:20 +00:00
ad0dba582f
Typo.
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llvm-svn: 73422
2009-06-15 21:18:20 +00:00
eba57e41b3
Do not form ldrd / strd if the two dests / srcs are the same. Code clean up.
...
llvm-svn: 73413
2009-06-15 20:54:56 +00:00
1cf0f193b0
Silence a warning.
...
llvm-svn: 73406
2009-06-15 19:36:32 +00:00
1283c6a066
Part 1.
...
- Change register allocation hint to a pair of unsigned integers. The hint type is zero (which means prefer the register specified as second part of the pair) or entirely target dependent.
- Allow targets to specify alternative register allocation orders based on allocation hint.
Part 2.
- Use the register allocation hint system to implement more aggressive load / store multiple formation.
- Aggressively form LDRD / STRD. These are formed *before* register allocation. It has to be done this way to shorten live interval of base and offset registers. e.g.
v1025 = LDR v1024, 0
v1026 = LDR v1024, 0
=>
v1025,v1026 = LDRD v1024, 0
If this transformation isn't done before allocation, v1024 will overlap v1025 which means it more difficult to allocate a register pair.
- Even with the register allocation hint, it may not be possible to get the desired allocation. In that case, the post-allocation load / store multiple pass must fix the ldrd / strd instructions. They can either become ldm / stm instructions or back to a pair of ldr / str instructions.
This is work in progress, not yet enabled.
llvm-svn: 73381
2009-06-15 08:28:29 +00:00
185c9ef0a2
Add a ARM specific pre-allocation pass that re-schedule loads / stores from
...
consecutive addresses togther. This makes it easier for the post-allocation pass
to form ldm / stm.
This is step 1. We are still missing a lot of ldm / stm opportunities because
of register allocation are not done in the desired order. More enhancements
coming.
llvm-svn: 73291
2009-06-13 09:12:55 +00:00
d93b5b672f
Mark some pattern-less instructions as neverHasSideEffects.
...
llvm-svn: 73252
2009-06-12 20:46:18 +00:00
5b1b5b2a8a
Typo
...
llvm-svn: 73098
2009-06-08 22:59:50 +00:00
3708883bfe
Revert hunk commited by accident
...
llvm-svn: 73097
2009-06-08 22:57:18 +00:00
77d1943637
The attached patches implement most of the ARM AAPCS-VFP hard float
...
ABI. The missing piece is support for putting "homogeneous aggregates"
into registers.
Patch by Sandeep Patel!
llvm-svn: 73095
2009-06-08 22:53:56 +00:00
c82b282b34
Separate V6 from V6T2 since the latter has some extra nice instructions
...
llvm-svn: 73085
2009-06-08 21:20:36 +00:00
cd41a9019e
Add helper for checking of Thumb1 mode
...
llvm-svn: 73080
2009-06-08 20:31:02 +00:00
d185a7a629
Add explicit keywords.
...
llvm-svn: 72969
2009-06-05 23:05:51 +00:00
3158790e32
Changing allocation ordering from r3 ... r0 back to r0 ... r3. The order change no longer make sense after the coalescing changes we have made since then.
...
llvm-svn: 72955
2009-06-05 19:08:58 +00:00
7fce2cf0ba
When merging multiple load / store instructions. Use the DebugLoc of the first one.
...
llvm-svn: 72952
2009-06-05 18:19:23 +00:00
c154c1185c
Code clean up: return vector by reference rather than by value. No functionality changes.
...
llvm-svn: 72950
2009-06-05 17:56:14 +00:00
d9ef48a73e
Remove some unnecessary #includes.
...
llvm-svn: 72948
2009-06-05 16:32:58 +00:00
7f5976e11b
Re-apply 72756 with fixes. One of those was introduced by we changed MachineInstrBuilder::addReg() interface.
...
llvm-svn: 72826
2009-06-04 01:15:28 +00:00
ab0c710fae
Temporarily revert 72756 for now.
...
llvm-svn: 72757
2009-06-03 07:40:47 +00:00
dfe6e689fd
Fold preceding / trailing base inc / dec into the single load / store as well.
...
llvm-svn: 72756
2009-06-03 06:14:58 +00:00
12694bd8ac
Implement review feedback. Make thumb2 'normal' subtarget feature
...
llvm-svn: 72698
2009-06-01 20:00:48 +00:00
9fd794bebf
Fix new CodeEmitter stuff to follow LLVM codying style. Patch by Aaron Gray
...
llvm-svn: 72697
2009-06-01 19:57:37 +00:00
2afc641e04
Do not emit "generic" CPU string. This fixes PR4291.
...
llvm-svn: 72696
2009-06-01 19:03:17 +00:00
a194c3a69e
First patch in the direction of splitting MachineCodeEmitter in two subclasses:
...
JITCodeEmitter and ObjectCodeEmitter. No functional changes yet. Patch by Aaron Gray
llvm-svn: 72631
2009-05-30 20:51:52 +00:00
09f17a8479
Untabification.
...
llvm-svn: 72604
2009-05-30 01:09:53 +00:00
b6f4538683
Add placeholder for thumb2 stuff
...
llvm-svn: 72593
2009-05-29 23:41:08 +00:00
9a3f3a5c3d
fix typo
...
llvm-svn: 72395
2009-05-25 19:51:07 +00:00
0b91cc4260
Add ARMv7 architecture, Cortex processors and different FPU modes handling.
...
llvm-svn: 72337
2009-05-23 19:51:43 +00:00
fa6f1eea36
Emit ARM Build Attributes
...
llvm-svn: 72336
2009-05-23 19:51:20 +00:00
08bf4c0f5a
Propagate CPU string out of SubtargetFeatures
...
llvm-svn: 72335
2009-05-23 19:50:50 +00:00
ccbc17b3a3
Only 64-bit targets support TImode libcalls. Disable the TImode shift libcalls
...
for ARM. This fixes rdar://6908807.
llvm-svn: 72269
2009-05-22 17:38:41 +00:00
dd0e23610a
Minor formatting fixes.
...
llvm-svn: 72172
2009-05-20 16:30:25 +00:00
335fa435dd
Fix pr4227: Handle large immediate values in inline assembly.
...
llvm-svn: 72138
2009-05-19 21:27:57 +00:00
840e3281ff
Follow up on new support for memory operands in ARM inline assembly.
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This fixes pr4233.
llvm-svn: 72115
2009-05-19 18:33:02 +00:00
e666cc5206
Fix pr4058 and pr4059. Do not split i64 or double arguments between r3 and
...
the stack. Patch by Sandeep Patel.
llvm-svn: 72106
2009-05-19 10:02:36 +00:00
a2c462bbe9
Fix pr4091: Add support for "m" constraint in ARM inline assembly.
...
llvm-svn: 72105
2009-05-19 05:53:42 +00:00
320d54a2d8
Fix pr4202: Disable CodePlacementOpt for ARM. The ARMConstantIslandPass has
...
to run last because it needs to know the exact size and position of every
basic block. Currently CodePlacementOpt is set up to run last. It might be
worthwhile to investigate reordering these passes, but for now, let's just
make it work.
llvm-svn: 72037
2009-05-18 20:55:32 +00:00
06928192ae
Update the names of the exception handling sjlj instrinsics to
...
llvm.eh.sjlj.* for better clarity as to their purpose and scope. Add
a description of llvm.eh.sjlj.setjmp to ExceptionHandling.html.
(llvm.eh.sjlj.longjmp documentation coming when that implementation is
added).
llvm-svn: 71758
2009-05-14 00:46:35 +00:00
91fa781df3
Spelling correction s/builting/builtin/ and remove trailing whitespace in a few places
...
llvm-svn: 71735
2009-05-13 22:32:43 +00:00
ab0d23396a
Run code placement optimization for targets that want it (arm and x86 for now).
...
llvm-svn: 71726
2009-05-13 21:42:09 +00:00
f7b83c7ae7
Change MachineInstrBuilder::addReg() to take a flag instead of a list of
...
booleans. This gives a better indication of what the "addReg()" is
doing. Remembering what all of those booleans mean isn't easy, especially if you
aren't spending all of your time in that code.
I took Jakob's suggestion and made it illegal to pass in "true" for the
flag. This should hopefully prevent any unintended misuse of this (by reverting
to the old way of using addReg()).
llvm-svn: 71722
2009-05-13 21:33:08 +00:00
aeca45dd6f
Add support for GCC compatible builtin setjmp and longjmp intrinsics. This is
...
a supporting preliminary patch for GCC-compatible SjLJ exception handling. Note that these intrinsics are not designed to be invoked directly by the user, but
rather used by the front-end as target hooks for exception handling.
llvm-svn: 71610
2009-05-12 23:59:14 +00:00
46632d89bb
correct register class for tADDspi to GPR since the register will always be SP
...
llvm-svn: 71602
2009-05-12 22:30:18 +00:00
ce8cfb41e8
Fix up a few minor typos in comments.
...
llvm-svn: 71563
2009-05-12 17:35:29 +00:00
2f4e56fd2e
Fix 80-col violations and remove trailing whitespace. No functional changes.
...
llvm-svn: 71562
2009-05-12 17:09:30 +00:00
af9eaa830a
Rename PaddedSize to AllocSize, in the hope that this
...
will make it more obvious what it represents, and stop
it being confused with the StoreSize.
llvm-svn: 71349
2009-05-09 07:06:46 +00:00
026e5d7667
Instead of passing in an unsigned value for the optimization level, use an enum,
...
which better identifies what the optimization is doing. And is more flexible for
future uses.
llvm-svn: 70440
2009-04-29 23:29:43 +00:00
084669a1c9
Second attempt:
...
Massive check in. This changes the "-fast" flag to "-O#" in llc. If you want to
use the old behavior, the flag is -O0. This change allows for finer-grained
control over which optimizations are run at different -O levels.
Most of this work was pretty mechanical. The majority of the fixes came from
verifying that a "fast" variable wasn't used anymore. The JIT still uses a
"Fast" flag. I'll change the JIT with a follow-up patch.
llvm-svn: 70343
2009-04-29 00:15:41 +00:00
56f2987a87
r70270 isn't ready yet. Back this out. Sorry for the noise.
...
llvm-svn: 70275
2009-04-28 01:04:53 +00:00
d0ae15946c
Massive check in. This changes the "-fast" flag to "-O#" in llc. If you want to
...
use the old behavior, the flag is -O0. This change allows for finer-grained
control over which optimizations are run at different -O levels.
Most of this work was pretty mechanical. The majority of the fixes came from
verifying that a "fast" variable wasn't used anymore. The JIT still uses a
"Fast" flag. I'm not 100% sure if it's necessary to change it there...
llvm-svn: 70270
2009-04-28 00:21:31 +00:00
0041bd3523
Change LowerCallResult method so that CCValAssign::BCvt can be used with
...
f64 types. This is not used for anything yet.
llvm-svn: 70006
2009-04-25 00:33:20 +00:00
40e784ce69
Adjust a comment to reflect what the code does. Splitting a 64-bit argument
...
between registers and the stack may be required with the APCS ABI, but it
isn't tied to using a particular version of the ARM architecture.
llvm-svn: 69978
2009-04-24 17:05:01 +00:00
f134b2d212
Fix up some problems with getCopyToReg and getCopyFromReg nodes being
...
chained and "flagged" together. I also made a few changes to handle the
chain and flag values more consistently. I found these problems by
inspection so I'm not aware of anything that breaks because of them
(thus no testcase).
llvm-svn: 69977
2009-04-24 17:00:36 +00:00
62d47d2361
Remove unnecessary references to f32 types. After specifying that f32
...
should be bit-converted to i32, it is sufficient to list only i32 in
subsequent definitions.
llvm-svn: 69973
2009-04-24 16:55:25 +00:00
f8b85477ae
Move duplicated AddLiveIn function from X86 and ARM backends to be a method
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in the MachineFunction class, renaming it to addLiveIn for consistency with
the same method in MachineBasicBlock. Thanks for Anton for suggesting this.
llvm-svn: 69615
2009-04-20 18:36:57 +00:00
b0b10f8bf6
Move the AddLiveIn function definition closer to its uses.
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llvm-svn: 69382
2009-04-17 20:42:34 +00:00
deeaf70dad
Rearrange code to reduce indentation.
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llvm-svn: 69381
2009-04-17 20:40:45 +00:00
ea09d4aca8
Clean up formatting, remove trailing whitespace, fix comment typos and
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punctuation. No functional changes.
llvm-svn: 69378
2009-04-17 20:35:10 +00:00
a4c2290e5f
Use CallConvLower.h and TableGen descriptions of the calling conventions
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for ARM. Patch by Sandeep Patel.
llvm-svn: 69371
2009-04-17 19:07:39 +00:00
866c174f79
Fix PR3795: Apply Dan's suggested fix for
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ARMTargetLowering::isLegalAddressingMode.
llvm-svn: 68619
2009-04-08 17:55:28 +00:00
fde2110aa9
PR2985 / <rdar://problem/6584986>
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When compiling in Thumb mode, only the low (R0-R7) registers are available
for most instructions. Breaking the low registers into a new register class
handles this. Uses of R12, SP, etc, are handled explicitly where needed
with copies inserted to move results into low registers where the rest of
the code generator can deal with them.
llvm-svn: 68545
2009-04-07 20:34:09 +00:00
0669f6d295
Handle 'a' modifier in ARM inline assembly.
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Patch by Richard Pennington.
llvm-svn: 68464
2009-04-06 21:46:51 +00:00
6bedd59894
Wrap some lines to fix indentation problems.
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llvm-svn: 68405
2009-04-03 21:08:42 +00:00
David Goodwin