Commit Graph

104120 Commits

Author SHA1 Message Date
Adam Nemet 35b80eaef1 [X86] Remove AVX1 vbroadcast intrinsics
The corresponding CFE patch replaces these intrinsics with vector initializers
in avxintrin.h.  This patch removes the LLVM intrinsics from the backend.

We now stop lowering at X86ISD::VBROADCAST custom node rather than lowering
that further to the intrinsics.

The patch only changes VBROADCASTS* and leaves VBROADCAST[FI]128 to continue
to use intrinsics.  As explained in the CFE patch, the reason is that we
currently don't generate as good code for them without the intrinsics.

CodeGen/X86/avx-vbroadcast.ll already provides coverage for this change.  It
checks that for a series of insertelements we generate the appropriate
vbroadcast instruction.

Also verified that there was no assembly change in the test-suite before and
after this patch.

llvm-svn: 209864
2014-05-29 23:35:36 +00:00
Adam Nemet 39066800e9 [X86] Auto-upgrade AVX1 vbroadcast intrinsics
They are replaced with the same IR that is generated for the
vector-initializers in avxintrin.h.

The test verifies that we get back the original instruction.  I haven't seen
this approach to be used in other auto-upgrade tests (i.e. llc + FileCheck)
but I think it's the most direct way to test this case.  I believe this should
work because llc upgrades calls during parsing.  (Other tests mostly check
that assembling and disassembling yields the upgraded IR.)

llvm-svn: 209863
2014-05-29 23:35:33 +00:00
Chandler Carruth fdc0e0b478 And fix my fix to sink down through the type at the right time. My
original fix would actually trigger the *exact* same crasher as the
original bug for a different reason. Awesomesauce.

Working on test cases now, but wanted to get bots healthier.

llvm-svn: 209860
2014-05-29 23:21:12 +00:00
Chandler Carruth 3012a1b4cd Fix one bug in the latest incarnation of r209843 -- combining GEPs
across PHI nodes. The code was computing the Idxs from the 'GEP'
variable's indices when what it wanted was Op1's indices. This caused an
ASan heap-overflow for me that pin pointed the issue when Op1 had more
indices than GEP did. =] I'll let Louis add a specific test case for
this if he wants.

llvm-svn: 209857
2014-05-29 23:05:52 +00:00
Jeroen Ketema 09f054fe37 Sync list of targets with configure's reality
llvm-svn: 209855
2014-05-29 22:23:22 +00:00
Arnold Schwaighofer e2067680a6 LoopVectorizer: Add a check that the backedge taken count + 1 does not overflow
The loop vectorizer instantiates be-taken-count + 1 as the loop iteration count.
If this expression overflows the generated code was invalid.

In case of overflow the code now jumps to the scalar loop.

Fixes PR17288.

llvm-svn: 209854
2014-05-29 22:10:01 +00:00
Filipe Cabecinhas 229dc17610 Added tests for shufflevector lowering to blend instrs.
These tests ensure that a change I will propose in clang works as
expected.

Summary:
Added tests for the generation of blend+immediate instructions from a
shufflevector.
These tests were proposed along with a patch that was dropped. I'm
committing the tests anyway to protect against possible regressions in
codegen.

Reviewers: nadav, bkramer

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D3600

llvm-svn: 209853
2014-05-29 22:04:42 +00:00
Louis Gerbarg c6b506a0ae Add support for combining GEPs across PHI nodes
Currently LLVM will generally merge GEPs. This allows backends to use more
complex addressing modes. In some cases this is not happening because there
is PHI inbetween the two GEPs:

  GEP1--\
        |-->PHI1-->GEP3
  GEP2--/

This patch checks to see if GEP1 and GEP2 are similiar enough that they can be
cloned (GEP12) in GEP3's BB, allowing GEP->GEP merging (GEP123):

  GEP1--\                     --\                           --\
        |-->PHI1-->GEP3  ==>    |-->PHI2->GEP12->GEP3 == >    |-->PHI2->GEP123
  GEP2--/                     --/                           --/

This also breaks certain use chains that are preventing GEP->GEP merges that the
the existing instcombine would merge otherwise.

Tests included.

llvm-svn: 209843
2014-05-29 20:29:47 +00:00
Chad Rosier e9665095cb Update Credits.
llvm-svn: 209840
2014-05-29 19:59:58 +00:00
Sebastian Pop 20daf3276d implement missing SCEVDivision case
without this case we would end on an infinite recursion: the remainder is zero,
so Numerator - Remainder is equal to Numerator and so we would recursively ask
for the division of Numerator by Denominator.

llvm-svn: 209838
2014-05-29 19:44:09 +00:00
Sebastian Pop 5352408169 fail to find dimensions when ElementSize is nullptr
when ScalarEvolution::getElementSize returns nullptr it is safe to early return
in ScalarEvolution::findArrayDimensions such that we avoid later problems when
we try to divide the terms by ElementSize.

llvm-svn: 209837
2014-05-29 19:44:05 +00:00
Alexey Samsonov a02e66499b Use range-based for loops in ASan, TSan and MSan
llvm-svn: 209834
2014-05-29 18:40:48 +00:00
Reid Kleckner 07630933bc [ADT] Delete the Twine assignment operator
This makes it slightly harder to misuse Twines.  It is still possible to
refer to destroyed temporaries with the regular constructors, though.

Patch by Marco Alesiani!

llvm-svn: 209832
2014-05-29 17:12:05 +00:00
Adrian Prantl fef140df96 Debug Info: Remove unused code. The MInsn of an _abstract_ variable is
never used again and updating the abstract variable for each inlined
instance of it was questionable in the first place.

llvm-svn: 209829
2014-05-29 16:56:48 +00:00
Rafael Espindola 4d16e11922 Rename alias variables to make it easier to add new tests to the file.
llvm-svn: 209822
2014-05-29 16:16:12 +00:00
Rafael Espindola 04902862a8 [PPC] Use alias symbols in address computation.
This seems to match what gcc does for ppc and what every other llvm
backend does.

This is a fixed version of r209638. The difference is to avoid any change
in behavior for functions. The logic for using constant pools for function
addresseses is spread over a few places and we have to keep them in sync.

llvm-svn: 209821
2014-05-29 15:41:38 +00:00
Rafael Espindola 1613650e90 Add a test showing the ppc code sequence for getting a function pointer.
This would have found the miscompile in r209638.

llvm-svn: 209820
2014-05-29 15:13:23 +00:00
Rafael Espindola a248f536b3 Revert "Revert "Revert "InstCombine: Improvement to check if signed addition overflows."""
This reverts commit r209776.

It was miscompiling llvm::SelectionDAGISel::MorphNode.

llvm-svn: 209817
2014-05-29 14:39:16 +00:00
Artyom Skrobov 0d22e2afe7 Restore getInvertedCondCode() from the phased-out backend, fixing disassembly for NV
llvm-svn: 209803
2014-05-29 11:34:50 +00:00
Artyom Skrobov 7e9e31ebaf Add missing check when MatchInstructionImpl() reports failure
llvm-svn: 209802
2014-05-29 11:26:15 +00:00
Simon Atanasyan 8745993ec4 [elf2yaml][ELF] Move Info field to the RelocationSection structure. This
field represents ELF section header sh_info field and does not have any
sense for regular sections. Its interpretation depends on section type.

llvm-svn: 209801
2014-05-29 11:05:31 +00:00
Hao Liu d670c7eee0 Rename a test case to contain correct date info.
llvm-svn: 209799
2014-05-29 09:21:23 +00:00
Hao Liu 4091450181 Fix an assertion failure caused by v1i64 in DAGCombiner Shrink.
llvm-svn: 209798
2014-05-29 09:19:07 +00:00
Dinesh Dwivedi d266cb1a0b LCSSA should be performed on the outermost affected loop while unrolling loop.
During loop-unroll, loop exits from the current loop may end up in in different
outer loop. This requires to re-form LCSSA recursively for one level down from
the outer most loop where loop exits are landed during unroll. This fixes PR18861.

Differential Revision: http://reviews.llvm.org/D2976

llvm-svn: 209796
2014-05-29 06:47:23 +00:00
Michael J. Spencer f74aae2c2d [LoadCombine] Missed a file.
llvm-svn: 209792
2014-05-29 02:05:37 +00:00
Michael J. Spencer 289067cc3d Add LoadCombine pass.
This pass is disabled by default. Use -combine-loads to enable in -O[1-3]

Differential revision: http://reviews.llvm.org/D3580

llvm-svn: 209791
2014-05-29 01:55:07 +00:00
Alexey Samsonov dea76ee889 [ASan] Hoist blacklisting globals from init-order checking to Clang.
Clang knows about the sanitizer blacklist and it makes no sense to
add global to the list of llvm.asan.dynamically_initialized_globals if it
will be blacklisted in the instrumentation pass anyway. Instead, we should
do as much blacklisting as possible (if not all) in the frontend.

llvm-svn: 209790
2014-05-29 01:44:13 +00:00
Michael J. Spencer f375d80635 [x86] Fold extract_vector_elt of a load into the Load's address computation.
An address only use of an extract element of a load can be simplified to a
load. Without this the result of the extract element is spilled to the
stack so that an address is available.

llvm-svn: 209788
2014-05-29 01:42:45 +00:00
Matt Arsenault b5c4835502 R600/SI: Fix pattern variable names.
These are confusing enough since the order swaps,
so give them more useful names.

llvm-svn: 209787
2014-05-29 01:18:01 +00:00
Alexey Samsonov 1f64750258 Fix typo in variable name
llvm-svn: 209784
2014-05-29 01:10:14 +00:00
Alexey Samsonov 96e239f564 [ASan] Use llvm.global_ctors to insert init-order checking calls into ASan runtime.
Don't assume that dynamically initialized globals are all initialized from
_GLOBAL__<module_name>I_ function. Instead, scan the llvm.global_ctors and
insert poison/unpoison calls to each function there.

Patch by Nico Weber!

llvm-svn: 209780
2014-05-29 00:51:15 +00:00
Reid Kleckner c316e0fc25 Add a simple helper function to create a 64-bit integer.
Add a function to combine two 32-bit integers into a 64-bit integer.
There are no calls to this function yet, although a subsequent change
will add some in LLDB.

Reviewers: rnk

Differential Revision: http://reviews.llvm.org/D3941

llvm-svn: 209777
2014-05-28 22:49:12 +00:00
Rafael Espindola 6196b7430e Revert "Revert "InstCombine: Improvement to check if signed addition overflows.""
This reverts commit r209762, bringing back r209746. It was not responsible for the libc++ build failure

llvm-svn: 209776
2014-05-28 21:43:52 +00:00
Rafael Espindola 910528a3eb Revert "Add support for combining GEPs across PHI nodes"
This reverts commit r209755.

it was the real cause of the libc++ build failure.

llvm-svn: 209775
2014-05-28 21:41:21 +00:00
Matt Arsenault 3ee3746374 Fix wrong setcc result type when legalizing uaddo/usubo
No test because no in-tree targets change the bitwidth of the
setcc type depending on the bitwidth of the compared type.

Patch by Ke Bai

llvm-svn: 209771
2014-05-28 20:51:42 +00:00
Jim Grosbach 92f11f44c8 Update CREDITS to be at least moderately more current.
llvm-svn: 209770
2014-05-28 20:31:52 +00:00
Sanjay Patel 8cf3bb4fcb fixed a few typos
llvm-svn: 209768
2014-05-28 20:07:37 +00:00
Sanjay Patel 26b6edcf44 test check-in: added missing parenthesis in comment
llvm-svn: 209763
2014-05-28 19:03:33 +00:00
Rafael Espindola fb59b05ca4 Revert "InstCombine: Improvement to check if signed addition overflows."
This reverts commit r209746.

It looks it is causing a crash while building libcxx. I am trying to get a
reduced testcase.

llvm-svn: 209762
2014-05-28 18:48:10 +00:00
Reid Kleckner 8a03f53ce2 Fix standard integer definitions for MSVC in DataTypes.h
Previously, DataTypes.h would #define a variety of symbols any time
they weren't already defined.  However, some versions of Visual
Studio do provide the appropriate headers, so if those headers are
included after DataTypes.h, it can lead to macro redefinition
warnings.

The fix is to include the appropriate headers if they exist, and
only #define the symbols if the required header does not exist.

Patch by Zachary Turner!

---

The big change here is that we no longer have our own stdint.h
typedefs because now all supported toolchains have stdint.h.
Hooray!

llvm-svn: 209760
2014-05-28 18:19:55 +00:00
Rafael Espindola 59f7eba2b5 [pr19844] Add thread local mode to aliases.
This matches gcc's behavior. It also seems natural given that aliases
contain other properties that govern how it is accessed (linkage,
visibility, dll storage).

Clang still has to be updated to expose this feature to C.

llvm-svn: 209759
2014-05-28 18:15:43 +00:00
Louis Gerbarg 727f1cbb17 Add support for combining GEPs across PHI nodes
Currently LLVM will generally merge GEPs. This allows backends to use more
complex addressing modes. In some cases this is not happening because there
is PHI inbetween the two GEPs:

  GEP1--\
        |-->PHI1-->GEP3
  GEP2--/

This patch checks to see if GEP1 and GEP2 are similiar enough that they can be
cloned (GEP12) in GEP3's BB, allowing GEP->GEP merging (GEP123):

  GEP1--\                     --\                           --\
        |-->PHI1-->GEP3  ==>    |-->PHI2->GEP12->GEP3 == >    |-->PHI2->GEP123
  GEP2--/                     --/                           --/

This also breaks certain use chains that are preventing GEP->GEP merges that the
the existing instcombine would merge otherwise.

Tests included.

llvm-svn: 209755
2014-05-28 17:38:31 +00:00
Hal Finkel 2c77fe59d9 Revert "[DAGCombiner] Split up an indexed load if only the base pointer value is live"
This reverts r208640 (I've just XFAILed the test) because it broke ppc64/Linux
self-hosting. Because nearly every regression test triggers a segfault, I hope
this will be easy to fix.

llvm-svn: 209747
2014-05-28 15:33:19 +00:00
Rafael Espindola 085b57941f InstCombine: Improvement to check if signed addition overflows.
This patch implements two things:

1. If we know one number is positive and another is negative, we return true as
   signed addition of two opposite signed numbers will never overflow.

2. Implemented TODO : If one of the operands only has one non-zero bit, and if
   the other operand has a known-zero bit in a more significant place than it
   (not including the sign bit) the ripple may go up to and fill the zero, but
   won't change the sign. e.x -  (x & ~4) + 1

We make sure that we are ignoring 0 at MSB.

Patch by Suyog Sarda.

llvm-svn: 209746
2014-05-28 15:30:40 +00:00
Hal Finkel f5c07ada1d Revert "[PPC] Use alias symbols in address computation."
This reverts commit r209638 because it broke self-hosting on ppc64/Linux. (the
Clang-compiled TableGen would segfault because it jumped to an invalid address
from within _ZNK4llvm17ManagedStaticBase21RegisterManagedStaticEPFPvvEPFvS1_E
(which is within the command-line parameter registration process)).

llvm-svn: 209745
2014-05-28 15:25:06 +00:00
Joerg Sonnenberger e6aafbb242 Don't hard-code ld when extracting host linker version, use ${LD} if
it is set.

llvm-svn: 209742
2014-05-28 15:12:55 +00:00
Evgeniy Stepanov 386b58d056 [asancov] Don't emit extra runtime calls when compiling without coverage.
llvm-svn: 209721
2014-05-28 09:26:46 +00:00
Tilmann Scheller 7c747fc7c6 [AArch64] Add store post-index update folding regression tests for the load/store optimizer.
Add regression tests for the following transformation:

  str X, [x20]
   ...
  add x20, x20, 
   ->
  str X, [x20], 

with X being either w0, x0, s0, d0 or q0.

llvm-svn: 209715
2014-05-28 06:43:00 +00:00
Justin Bogner dc30fbf7b6 utils: Teach lldbDataFormatters to load automatically
Add an __lldb_init_module function so that importing the
lldbDataFormatters script automatically adds the formatters.

llvm-svn: 209712
2014-05-28 05:45:17 +00:00
Tilmann Scheller 35e451461f [AArch64] Add load post-index update folding regression tests for the load/store optimizer.
Add regression tests for the following transformation:

 ldr X, [x20]
  ...
 add x20, x20, 
  ->
 ldr X, [x20], 

 with X being either w0, x0, s0, d0 or q0.

llvm-svn: 209711
2014-05-28 05:44:14 +00:00
Alexey Samsonov bb2990df58 Change representation of instruction ranges where variable is accessible.
Use more straightforward way to represent the set of instruction
ranges where the location of a user variable is defined - vector of pairs
of instructions (defining start/end of each range),
instead of a flattened vector of instructions where some instructions
are supposed to start the range, and the rest are supposed to "clobber" it.

Simplify the code which generates actual .debug_loc entries.

No functionality change.

llvm-svn: 209698
2014-05-27 23:09:50 +00:00
Alexey Samsonov 8a86d6da26 Factor out looking for prologue end into a function
llvm-svn: 209697
2014-05-27 22:47:41 +00:00
Sebastian Pop f93ef12330 avoid type mismatch when building SCEVs
This is a corner case I have stumbled upon when dealing with ARM64 type
conversions. I was not able to extract a testcase for the community codebase to
fail on. The patch conservatively discards a division that would have ended up
in an ICE due to a type mismatch when building a multiply expression. I have
also added code to a place that builds add expressions and in which we should be
careful not to pass in operands of different types.

llvm-svn: 209694
2014-05-27 22:42:00 +00:00
Sebastian Pop e30bd351cc do not use the GCD to compute the delinearization strides
We do not need to compute the GCD anymore after we removed the constant
coefficients from the terms: the terms are now all parametric expressions and
there is no need to recognize constant terms that divide only a subset of the
terms. We only rely on the size of the terms, i.e., the number of operands in
the multiply expressions, to sort the terms and recognize the parametric
dimensions.

llvm-svn: 209693
2014-05-27 22:41:56 +00:00
Sebastian Pop 28e6b97b5d remove BasePointer before delinearizing
No functional change is intended: instead of relying on the delinearization to
come up with the base pointer as a remainder of the divisions in the
delinearization, we just compute it from the array access and use that value.
We substract the base pointer from the SCEV to be delinearized and that
simplifies the work of the delinearizer.

llvm-svn: 209692
2014-05-27 22:41:51 +00:00
Sebastian Pop a6e5860513 remove constant terms
The delinearization is needed only to remove the non linearity induced by
expressions involving multiplications of parameters and induction variables.
There is no problem in dealing with constant times parameters, or constant times
an induction variable.

For this reason, the current patch discards all constant terms and multipliers
before running the delinearization algorithm on the terms. The only thing
remaining in the term expressions are parameters and multiply expressions of
parameters: these simplified term expressions are passed to the array shape
recognizer that will not recognize constant dimensions anymore: these will be
recognized as different strides in parametric subscripts.

The only important special case of a constant dimension is the size of elements.
Instead of relying on the delinearization to infer the size of an element,
compute the element size from the base address type. This is a much more precise
way of computing the element size than before, as we would have mixed together
the size of an element with the strides of the innermost dimension.

llvm-svn: 209691
2014-05-27 22:41:45 +00:00
Alexey Samsonov f0e0cca0c7 Don't pre-populate the set of keys in the map with variable locations history.
Current implementation of calculateDbgValueHistory already creates the
keys in the expected order (user variables are listed in order of appearance),
and should do so later by contract.

No functionality change.

llvm-svn: 209690
2014-05-27 22:35:00 +00:00
Arnaud A. de Grandmaison de5ff26865 No need for those tests to go thru llvm-as and/or llvm-dis.
opt can handle them by itself.

llvm-svn: 209689
2014-05-27 22:03:28 +00:00
Arnaud A. de Grandmaison 6a90dc4f30 Factor out comparison of Instruction "special" states.
No functional change.

llvm-svn: 209688
2014-05-27 21:35:46 +00:00
Reid Kleckner bffbcc596f Wording fix for llvm.global_dtors docs.
llvm-svn: 209687
2014-05-27 21:35:17 +00:00
David Blaikie 6900674aaf DebugInfo: partially revert cleanup committed in r209680
I'm not sure exactly where/how we end up with an abstract DbgVariable
with a null DIE, but we do... looking into it & will add a test and/or
fix when I figure it out.

Currently shows up in selfhost or compiler-rt builds.

llvm-svn: 209683
2014-05-27 20:20:43 +00:00
David Blaikie b85f0080e7 DebugInfo: Simplify solution to avoid DW_AT_artificial on inlined parameters.
Originally committed in r207717, I clearly didn't look very closely at
the code to understand how existing things were working...

llvm-svn: 209680
2014-05-27 19:34:32 +00:00
Sasa Stankovic e41db2fe31 [mips] Optimize long branch for MIPS64 by removing %higher and %highest.
%higher and %highest can have non-zero values only for offsets greater
than 2GB, which is highly unlikely, if not impossible when compiling a
single function. This makes long branch for MIPS64 3 instructions smaller.

Differential Revision: http://llvm-reviews.chandlerc.com/D3281.diff

llvm-svn: 209678
2014-05-27 18:53:06 +00:00
David Blaikie 482097d098 DebugInfo: Create abstract function definitions even when concrete definitions preceed inline definitions.
After much puppetry, here's the major piece of the work to ensure that
even when a concrete definition preceeds all inline definitions, an
abstract definition is still created and referenced from both concrete
and inline definitions.

Variables are still broken in this case (see comment in
dbg-value-inlined-parameter.ll test case) and will be addressed in
follow up work.

llvm-svn: 209677
2014-05-27 18:37:55 +00:00
David Blaikie 2910f62084 DebugInfo: Avoid an extra map lookup when finding abstract subprogram DIEs.
llvm-svn: 209676
2014-05-27 18:37:51 +00:00
David Blaikie 3c2fff3fe6 DebugInfo: Lazily construct subprogram definition DIEs.
A further step to correctly emitting concrete out of line definitions
preceeding inlined instances of the same program.

To do this, emission of subprograms must be delayed until required since
we don't know which (abstract only (if there's no out of line
definition), concrete only (if there are no inlined instances), or both)
DIEs are required at the start of the module.

To reduce the test churn in the following commit that actually fixes the
bug, this commit introduces the lazy DIE construction and cleans up test
cases that are impacted by the changes in the resulting DIE ordering.

llvm-svn: 209675
2014-05-27 18:37:48 +00:00
David Blaikie f7221adb8e DebugInfo: Lazily attach definition attributes to definitions.
This is a precursor to fixing inlined debug info where the concrete,
out-of-line definition may preceed any inlined usage. To cope with this,
the attributes that may appear on the concrete definition or the
abstract definition are delayed until the end of the module. Then, if an
abstract definition was created, it is referenced (and no other
attributes are added to the out-of-line definition), otherwise the
attributes are added directly to the out-of-line definition.

In a couple of cases this causes not just reordering of attributes, but
reordering of types. When the creation of the attribute is delayed, if
that creation would create a type (such as for a DW_AT_type attribute)
then other top level DIEs may've been constructed during the delay,
causing the referenced type to be created and added after those
intervening DIEs. In the extreme case, in cross-cu-inlining.ll, this
actually causes the DW_TAG_basic_type for "int" to move from one CU to
another.

llvm-svn: 209674
2014-05-27 18:37:43 +00:00
David Blaikie 7f91686f07 DebugInfo: Separate out the addition of subprogram attribute additions so that they can be added later depending on whether or not the function is inlined.
llvm-svn: 209673
2014-05-27 18:37:38 +00:00
Jingyue Wu 76cbea6b6d Fixed a test in r209670
The test was outdated with r209537.

llvm-svn: 209671
2014-05-27 18:12:55 +00:00
Jingyue Wu 80a738dc62 Distribute sext/zext to the operands of and/or/xor
This is an enhancement to SeparateConstOffsetFromGEP. With this patch, we can
extract a constant offset from "s/zext and/or/xor A, B".

Added a new test @ext_or to verify this enhancement.

Refactoring the code, I also extracted some common logic to function
Distributable. 

llvm-svn: 209670
2014-05-27 18:00:00 +00:00
David Blaikie 66c3077470 DebugInfo: Fix argument ordering in test by adding argument numbering.
This old test didn't have the argument numbering that's now squirelled
away in the high bits of the line number in the DW_TAG_arg_variable
metadata.

Add the numbering and update the test to ensure arguments are in-order.

llvm-svn: 209669
2014-05-27 17:57:14 +00:00
Filipe Cabecinhas e8d6a1e82f Post-commit fixes for r209643
Detected by Daniel Jasper, Ilia Filippov, and Andrea Di Biagio
Fixed the argument order to select (the mask semantics to blendv* are the
inverse of select) and fixed the tests
Added parenthesis to the assert condition
Ran clang-format

llvm-svn: 209667
2014-05-27 16:54:33 +00:00
Tim Northover 9a6217b650 AArch64: add test for NZCV cross-copy save.
llvm-svn: 209665
2014-05-27 16:50:09 +00:00
Tim Northover de9402d345 AArch64: add AArch64-specific test for 'c' and 'n'.
llvm-svn: 209664
2014-05-27 16:50:03 +00:00
Bill Schmidt 71dddd51d9 [PATCH] Correct type used for VADD_SPLAT optimization on PowerPC
In PPCISelLowering.cpp: PPCTargetLowering::LowerBUILD_VECTOR(), there
is an optimization for certain patterns to generate one or two vector
splats followed by a vector add or subtract.  This operation is
represented by a VADD_SPLAT in the selection DAG.  Prior to this
patch, it was possible for the VADD_SPLAT to be assigned the wrong
data type, causing incorrect code generation.  This patch corrects the
problem.

Specifically, the code previously assigned the value type of the
BUILD_VECTOR node to the newly generated VADD_SPLAT node.  This is
correct much of the time, but not always.  The problem is that the
call to isConstantSplat() may return a SplatBitSize that is not the
same as the number of bits in the original element vector type.  The
correct type to assign is a vector type with the same element bit size
as SplatBitSize.

The included test case shows an example of this, where the
BUILD_VECTOR node has a type of v16i8.  The vector to be built is {0,
16, 0, 16, 0, 16, 0, 16, 0, 16, 0, 16, 0, 16, 0, 16}.  isConstantSplat
detects that we can generate a splat of 16 for type v8i16, which is
the type we must assign to the VADD_SPLAT node.  If we do not, we
generate a vspltisb of 8 and a vaddubm, which generates the incorrect
result {16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16,
16}.  The correct code generation is a vspltish of 8 and a vadduhm.

This patch also corrected code generation for
CodeGen/PowerPC/2008-07-10-SplatMiscompile.ll, which had been marked
as an XFAIL, so we can remove the XFAIL from the test case.

llvm-svn: 209662
2014-05-27 15:57:51 +00:00
Zoran Jovanovic b355e8f604 [mips][mips64r6] Add Relocations R_MIPS_PCHI16, R_MIPS_PCLO16
Differential Revision: http://reviews.llvm.org/D3860

llvm-svn: 209659
2014-05-27 14:58:51 +00:00
Amara Emerson ceeb1c4830 [ARM] Emit correct build attributes for the relocation models.
Patch by Asiri Rathnayake.

llvm-svn: 209656
2014-05-27 13:30:21 +00:00
Zoran Jovanovic 10e06da031 [mips][mips64r6] Add relocations R_MIPS_PC21_S2, R_MIPS_PC26_S2
Differential Revision: http://reviews.llvm.org/D3824

llvm-svn: 209655
2014-05-27 12:55:40 +00:00
Evgeniy Stepanov 47b1a95f1c [asancov] Emit an initializer passing number of coverage code locations in each module.
llvm-svn: 209654
2014-05-27 12:39:31 +00:00
Tim Northover 1bed9afd30 AArch64: implement copies to/from NZCV as a last ditch effort.
A test in test/Generic creates a DAG where the NZCV output of an ADCS is used
by multiple nodes. This makes LLVM want to save a copy of NZCV for later, which
it couldn't do before.

This should be the last fix required for the aarch64 buildbot.

llvm-svn: 209651
2014-05-27 12:16:02 +00:00
Tim Northover 4f1909f1da ARM: teach AAPCS-VFP to deal with Cortex-M4.
Cortex-M4 only has single-precision floating point support, so any LLVM
"double" type will have been split into 2 i32s by now. Fortunately, the
consecutive-register framework turns out to be precisely what's needed to
reconstruct the double and follow AAPCS-VFP correctly!

rdar://problem/17012966

llvm-svn: 209650
2014-05-27 10:43:38 +00:00
Daniel Jasper 73458c95ac Fix bad assert.
llvm-svn: 209648
2014-05-27 09:55:37 +00:00
Tim Northover 4719041db7 AArch64: support 'c' and 'n' inline asm modifiers.
These are tested by test/CodeGen/Generic, so we should probably know
how to deal with them. Fortunately generic code does it if asked.

llvm-svn: 209646
2014-05-27 07:37:21 +00:00
Dinesh Dwivedi c0e6703360 Adding testcase for PR18886.
Differential Revision: http://reviews.llvm.org/D3837

llvm-svn: 209645
2014-05-27 06:44:25 +00:00
Filipe Cabecinhas 82ac07c283 Convert some X86 blendv* intrinsics into IR.
Summary:
Implemented an InstCombine transformation that takes a blendv* intrinsic
call and translates it into an IR select, if the mask is constant.

This will eventually get lowered into blends with immediates if possible,
or pblendvb (with an option to further optimize if we can transform the
pblendvb into a blend+immediate instruction, depending on the selector).
It will also enable optimizations by the IR passes, which give up on
sight of the intrinsic.

Both the transformation and the lowering of its result to asm got shiny
new tests.

The transformation is a bit convoluted because of blendvp[sd]'s
definition:

Its mask is a floating point value! This forces us to convert it and get
the highest bit. I suppose this happened because the mask has type
__m128 in Intel's intrinsic and v4sf (for blendps) in gcc's builtin.

I will send an email to llvm-dev to discuss if we want to change this or
not.

Reviewers: grosbach, delena, nadav

Differential Revision: http://reviews.llvm.org/D3859

llvm-svn: 209643
2014-05-27 03:42:20 +00:00
Rafael Espindola 3bc64d54a9 Fix link.
llvm-svn: 209640
2014-05-26 21:30:40 +00:00
Rafael Espindola 19913ee160 Use existing helper function.
No functionality change.

llvm-svn: 209639
2014-05-26 19:57:55 +00:00
Rafael Espindola ac69cee6a2 [PPC] Use alias symbols in address computation.
This seems to match what gcc does for ppc and what every other llvm
backend does.

llvm-svn: 209638
2014-05-26 19:08:19 +00:00
Tim Northover 68ae503de9 AArch64: force i1 to be zero-extended at an ABI boundary.
This commit is debatable. There are two possible approaches, neither
of which is really satisfactory:

1. Use "@foo(i1 zeroext)" to mean an extension to 32-bits on Darwin,
   and 8 bits otherwise.
2. Redefine "@foo(i1)" to mean that the i1 is extended by the caller
   to 8 bits. This goes against the spirit of "zeroext" I think, but
   it's a bit of a vague construct anyway (by definition you're going
   to extend to the amount required by the ABI, that's why it's the
   ABI!).

This implements option 2. The DAG machinery really isn't setup for the
first (there's a fairly strong assumption that "zeroext" goes to at
least the smallest register size), and even if it was the resulting
DAG looks like it would be inferior in many cases.

Theoretically we could add AssertZext nodes in the consumers of
ABI-passed values too now, but this actually seems to make the code
worse in practice by making truncation proceed in two steps. The code
produced is equally valid if we continue to assume only the low bit is
defined.

Should fix PR19850

llvm-svn: 209637
2014-05-26 17:22:07 +00:00
Tim Northover 47e003c65d AArch64: simplify calling conventions slightly.
We can eliminate the custom C++ code in favour of some TableGen to
check the same things. Functionality should be identical, except for a
buffer overrun that was present in the C++ code and meant webkit
failed if any small argument needed to be passed on the stack.

llvm-svn: 209636
2014-05-26 17:21:53 +00:00
Michael Zolotukhin 265dfa411c Some cleanup for r209568.
llvm-svn: 209634
2014-05-26 14:49:46 +00:00
Rafael Espindola acef6c776b Convert a few loops to use ranges.
llvm-svn: 209628
2014-05-26 13:38:51 +00:00
Tilmann Scheller cc3ebc8a98 [AArch64] Add store + add folding regression tests for the load/store optimization pass.
Add tests for the following transform:

 str X, [x0, ]
  ...
 add x0, x0, 
  ->
 str X, [x0, ]!

with X being either w1, x1, s0, d0 or q0.

llvm-svn: 209627
2014-05-26 13:36:47 +00:00
Tilmann Scheller 112ada831f [AArch64] Add more regression tests for the load/store optimization pass.
Cover the following cases:

  ldr X, [x0, ]
   ...
  add x0, x0, 
   ->
  ldr X, [x0, ]!

with X being either w1, x1, s0, d0 or q0.

llvm-svn: 209624
2014-05-26 12:15:51 +00:00
Kostya Serebryany 4d237a8503 [asan] decrease asan-instrumentation-with-call-threshold from 10000 to 7000, see PR17409
llvm-svn: 209623
2014-05-26 11:57:16 +00:00
Tilmann Scheller 968d599dc4 Remove accidentally committed whitespace.
llvm-svn: 209619
2014-05-26 09:40:40 +00:00
Tilmann Scheller 2d746bcda3 [AArch64] Add a regression test for the load store optimizer.
We have a couple of regression tests for load/store pairing, but (to my knowledge) there are no regression tests for the load/store + add/sub folding.

As a first step towards increased test coverage of this area, this commit adds a test for one instance of a load + add to pre-indexed load transformation.

llvm-svn: 209618
2014-05-26 09:37:19 +00:00
Owen Anderson 115aa160e6 Make the LoopRotate pass's maximum header size configurable both programmatically
and via the command line, mirroring similar functionality in LoopUnroll.  In
situations where clients used custom unrolling thresholds, their intent could
previously be foiled by LoopRotate having a hardcoded threshold.

llvm-svn: 209617
2014-05-26 08:58:51 +00:00
David Blaikie 10743a9e6d DebugInfo: Test linkonce-odr functions under LTO.
This was previously regressed/broken by r192749 (reverted due to this
issue in r192938) and I was about to break it again by accident with
some more invasive changes that deal with the subprogram lists. So to
avoid that and further issues - here's a test.

It's a pretty basic test - in both r192749 and my impending case, this
test would crash, but checking the basics (that we put a subprogram in
just one of the two CUs) seems like a good start.

We still get this wrong in weird ways if the linkonce-odr function
happens to not be identical in the metadata (because it's defined in two
different files (hence the # line directives in this test), etc) even
though it meets the language requirements (identical token stream) for
such a thing. That results in two subprogram DIEs, but only one of them
gets the parameter and high/low pc information, etc. We probably need to
use the DIRef infrastructure to deduplicate functions as we do types to
address this issue - or perhaps teach the BC linker to remove the
duplicate entries in subprogram lists?

llvm-svn: 209614
2014-05-26 06:44:52 +00:00
David Blaikie ab53c91010 DwarfUnit: Remove some misleading no-op code introduced in r204162.
Post commit review feedback from Manman called this out, but it looks
like it slipped through the cracks.

llvm-svn: 209611
2014-05-26 05:32:21 +00:00
Rafael Espindola f557536f56 Just check the entire string.
Thanks to David Blaikie for the suggestion.

llvm-svn: 209610
2014-05-26 04:08:51 +00:00
NAKAMURA Takumi f1b81c6e04 Reformat linefeeds.
llvm-svn: 209609
2014-05-26 00:25:26 +00:00
NAKAMURA Takumi 2667c3eac5 Trailing whitespace.
llvm-svn: 209608
2014-05-26 00:25:09 +00:00
Saleem Abdulrasool 65dbbb5dd6 tools: avoid use of std::function
Remove the use of the std::function and replace the capturing lambda with a
non-capturing one, opting to pass the user data down to the context.  This is
needed as std::function is not yet available on all hosted platforms (it
requires RTTI, which breaks on Windows).

Thanks to Nico Rieck for pointing this out!

llvm-svn: 209607
2014-05-25 21:37:59 +00:00
Saleem Abdulrasool e8839a755a tools: split out Win64EHDumper from COFFDumper
Move the implementation of the Win64 EH printer from the COFFDumper into its own
class.  This is in preparation for adding support to print ARM EH information.
The only real change here is in printUnwindInfo where we now lambda lift the
implicit this parameter for the resolveFunction.  Also setup the printing to
handle ARM.  This now has set the stage to introduce ARM EH printing.

llvm-svn: 209606
2014-05-25 20:26:45 +00:00
Saleem Abdulrasool 4e08f62775 tools: inline simple single-use function
This inlines the single use function in preparation for splitting the Win64EH
printing out of the COFFDumper into its own entity.

llvm-svn: 209605
2014-05-25 20:26:40 +00:00
Saleem Abdulrasool 5dd27f42f9 tools: refactor COFFDumper symbol resolution logic
Make the use of the cache more transparent to the users.  There is no reason
that the cached entries really need to be passed along.  The overhead for doing
so is minimal: a single extra parameter.  This requires that some standalone
functions be brought into the COFFDumper class so that they may access the
cache.

llvm-svn: 209604
2014-05-25 20:26:37 +00:00
Saleem Abdulrasool 3617c96d46 tools: use references rather than out pointers in COFFDumper
Switch to use references for parameters that are guaranteed to be non-null.
Simplifies the code a slight bit in preparation for another change.

llvm-svn: 209603
2014-05-25 20:26:33 +00:00
David Blaikie ea86226774 DebugInfo: Fix inlining with #file directives a little harder
Seems my previous fix was insufficient - we were still not adding the
inlined function to the abstract scope list. Which meant it wasn't
flagged as inline, didn't have nested lexical scopes in the abstract
definition, and didn't have abstract variables - so the inlined variable
didn't reference an abstract variable, instead being described
completely inline.

llvm-svn: 209602
2014-05-25 18:11:35 +00:00
David Blaikie 69d3406a2d Streamline test case by avoiding a temporary file and piping llc output straight to llvm-dwarfdump
We still do temporary files in many cases, just updating this particular
one because I was debugging it and made this change while doing so.

llvm-svn: 209601
2014-05-25 15:38:52 +00:00
Rafael Espindola 4a04c4b69c Emit data or code export directives based on the type.
Currently we look at the Aliasee to decide what type of export
directive to use. It seems better to use the type of the alias
directly. This is similar to how we handle the alias having the
same address but other attributes (linkage, visibility) from the
aliasee.

With this patch it is now possible to do things like

target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-pc-windows-msvc"
@foo = global [6 x i8] c"\B8*\00\00\00\C3", section ".text", align 16
@f = dllexport alias i32 (), [6 x i8]* @foo
!llvm.module.flags = !{!0}
 = metadata !{i32 6, metadata !"Linker Options", metadata !1}
 = metadata !{metadata , metadata !3}
 = metadata !{metadata !"/DEFAULTLIB:libcmt.lib"}
 = metadata !{metadata !"/DEFAULTLIB:oldnames.lib"}

llvm-svn: 209600
2014-05-25 12:49:07 +00:00
Rafael Espindola d234b0f08c Make these CHECKs a bit more strict.
The " at the end of the line makes sure we matched the entire directive.

llvm-svn: 209599
2014-05-25 12:43:13 +00:00
Peter Collingbourne 0a4376190f Add an extension point for peephole optimizers.
This extension point allows adding passes that perform peephole optimizations
similar to the instruction combiner. These passes will be inserted after
each instance of the instruction combiner pass.

Differential Revision: http://reviews.llvm.org/D3905

llvm-svn: 209595
2014-05-25 10:27:02 +00:00
Hans Wennborg 12d1e24da2 Fix some misplaced spaces around 'override'
llvm-svn: 209589
2014-05-24 20:19:40 +00:00
Saleem Abdulrasool 443264c51f build: sort llvm-readobj sources
Sort the source files.  NFC.

llvm-svn: 209587
2014-05-24 20:04:21 +00:00
Saleem Abdulrasool 12688f40c1 llvm-readobj: remove some dead code
llvm-svn: 209586
2014-05-24 19:54:28 +00:00
Tim Northover 391f93a554 AArch64: disable FastISel for large code model.
The code emitted is what would be expected for the small model, so it
shouldn't be used when objects can be the full 64-bits away.

This fixes MCJIT tests on Linux.

llvm-svn: 209585
2014-05-24 19:45:41 +00:00
Benjamin Kramer 5256ce37ac MachineVerifier: Clean up some syntactic weirdness left behind by find&replace.
No functionality change.

llvm-svn: 209581
2014-05-24 13:31:10 +00:00
Benjamin Kramer 389cec0d3e CodeGen: Make MachineBasicBlock::back skip to the beginning of the last bundle.
This makes front/back symmetric with begin/end, avoiding some confusion.
Added instr_front/instr_back for the old behavior, corresponding to
instr_begin/instr_end. Audited all three in-tree users of back(), all
of them look like they don't want to look inside bundles.

Fixes an assertion (PR19815) when generating debug info on mips, where a
delay slot was bundled at the end of a branch.

llvm-svn: 209580
2014-05-24 13:13:17 +00:00
Tim Northover 3b0846e8f7 AArch64/ARM64: move ARM64 into AArch64's place
This commit starts with a "git mv ARM64 AArch64" and continues out
from there, renaming the C++ classes, intrinsics, and other
target-local objects for consistency.

"ARM64" test directories are also moved, and tests that began their
life in ARM64 use an arm64 triple, those from AArch64 use an aarch64
triple. Both should be equivalent though.

This finishes the AArch64 merge, and everyone should feel free to
continue committing as normal now.

llvm-svn: 209577
2014-05-24 12:50:23 +00:00
Tim Northover cc08e1fe1b AArch64/ARM64: remove AArch64 from tree prior to renaming ARM64.
I'm doing this in two phases for a better "git blame" record. This
commit removes the previous AArch64 backend and redirects all
functionality to ARM64. It also deduplicates test-lines and removes
orphaned AArch64 tests.

The next step will be "git mv ARM64 AArch64" and rewire most of the
tests.

Hopefully LLVM is still functional, though it would be even better if
no-one ever had to care because the rename happens straight
afterwards.

llvm-svn: 209576
2014-05-24 12:42:26 +00:00
NAKAMURA Takumi e8faaa0c58 llvm/test/Object/ar-error.test: Don't check the message "No such file or directory".
It didn't match on non-English version of Windows.

llvm-svn: 209570
2014-05-24 08:47:11 +00:00
Michael Zolotukhin d4c724625a Implement sext(C1 + C2*X) --> sext(C1) + sext(C2*X) and
sext{C1,+,C2} --> sext(C1) + sext{0,+,C2} transformation in Scalar
Evolution.

That helps SLP-vectorizer to recognize consecutive loads/stores.

<rdar://problem/14860614>

llvm-svn: 209568
2014-05-24 08:09:57 +00:00
Tim Northover e471e43484 ARM64: extract a 32-bit subreg when selecting an inreg extend
After the load/store refactoring, we were sometimes trying to feed a
GPR64 into a 32-bit register offset operand. This failed in
copyPhysReg.

llvm-svn: 209566
2014-05-24 07:05:42 +00:00
David Blaikie 2f75351c02 DebugInfo: Generalize some tests to handle variations in attribute ordering.
In an effort to fix inlined debug info in situations where the out of
line definition of a function preceeds any inlined usage, the order in
which some attributes are added to subprogram DIEs may change. (in
essence, definition-necessary attributes like DW_AT_low_pc/high_pc will
be added immediately, but the names, types, and other features will be
delayed to module end where they may either be added to the subprogram
DIE or instead reference an abstract definition for those values)

These tests can be generalized to be resilient to this change. 5 or so
tests actually have to be incompatibly changed to cope with this
reordering and will go along with the change that affects the order.

llvm-svn: 209554
2014-05-23 21:11:46 +00:00
David Blaikie 71ed20f671 DebugInfo: Generalize a test case to not depend on abbreviation numbering.
It's an unnecessary detail for this test and just gets in the way when
making unrelated changes to the output in this test.

llvm-svn: 209553
2014-05-23 21:07:01 +00:00
Andrew Trick b429083aff Test case comments. Fix sloppiness.
llvm-svn: 209551
2014-05-23 20:46:21 +00:00
Rafael Espindola ef2c4fb25b clang-format function.
llvm-svn: 209550
2014-05-23 20:39:23 +00:00
Rafael Espindola d246759973 Remove a confusing use of a static method.
No functionality change.

llvm-svn: 209548
2014-05-23 20:35:47 +00:00
David Blaikie 169ffe41af DebugInfo: Put concrete definitions referencing abstract definitions in the same scope as the abstract definition.
This seems like a simple cleanup/improved consistency, but also helps
lay the foundation to fix the bug mentioned in the test case: concrete
definitions preceeding any inlined usage aren't properly split into
concrete + abstract (because they're not known to need it until it's too
late).

Once we start deferring this choice until later, we won't have the
choice to put concrete definitions for inlined subroutines in a
different scope from concrete definitions for non-inlined subroutines
(since we won't know at time-of-construction which one it'll be). This
change brings those two cases into alignment ahead of that future
chaneg/fix.

llvm-svn: 209547
2014-05-23 20:25:15 +00:00
Andrew Trick 839e30b2c0 Fix and improve SCEV ComputeBackedgeTankCount.
This is a follow-up to r209358: PR19799: Indvars miscompile due to an
incorrect max backedge taken count from SCEV.

That fix was incomplete as pointed out by Arnold and Michael Z. The
code was also too confusing. It needed a careful rewrite with more
unit tests. This version will also happen to optimize more cases.

<rdar://17005101> PR19799: Indvars miscompile...

llvm-svn: 209545
2014-05-23 19:47:13 +00:00
Nico Rieck fe2413692f Revert part of "Fix broken FileCheck prefixes"
This reverts part of commit r209538.

llvm-svn: 209544
2014-05-23 19:33:49 +00:00
Rafael Espindola a5bb2f61cf Use alias linkage and visibility to decide tls access mode.
This matches both what we do for the non-thread case and what gcc does.

With this patch clang would match gcc's behaviour in

static __thread int a = 42;
extern __thread int b __attribute__((alias("a")));
int *f(void) { return &a; }
int *g(void) { return &b; }

if not for pr19843. Manually writing the IL does produce the same access modes.

It is also a step in the direction of fixing pr19844.

llvm-svn: 209543
2014-05-23 19:16:56 +00:00
Nico Rieck fb4c55fb64 Remove unused CHECK lines
llvm-svn: 209539
2014-05-23 19:06:44 +00:00
Nico Rieck bd15945ab2 Fix broken FileCheck prefixes
llvm-svn: 209538
2014-05-23 19:06:24 +00:00
Jingyue Wu bbb6e4a885 Add the extracted constant offset using GEP
Fixed a TODO in r207783.

Add the extracted constant offset using GEP instead of ugly
ptrtoint+add+inttoptr. Using GEP simplifies future optimizations and makes IR
easier to understand. 

Updated all affected tests, and added a new test in split-gep.ll to cover a
corner case where emitting uglygep is necessary.

llvm-svn: 209537
2014-05-23 18:39:40 +00:00
Lang Hames 8e30e4b9b7 [RuntimeDyld] Remove relocation bounds check introduced in r208375 (MachO only).
We do all of our address arithmetic in 64-bit, and operations involving
logically negative 32-bit offsets (actually represented as unsigned 64 bit ints)
often overflow into higher bits. The overflow check could be preserved by
casting to uint32 at the callsite for applyRelocationValue, but this would
eliminate the value of the check.

The right way to handle overflow in relocations is to make relocation processing
target specific, and compute the values for RelocationEntry objects in the
appropriate types (32-bit for 32-bit targets, 64-bit for 64-bit targets). This
is coming as part of the cleanup I'm working on.

This fixes another i386 regression test.

<rdar://problem/16889891>

llvm-svn: 209536
2014-05-23 18:35:44 +00:00
David Blaikie 05b8584f16 Add FIXME comment based on code review feedback by Hal Finkel on r209338
llvm-svn: 209529
2014-05-23 16:53:14 +00:00
Rafael Espindola fbe44200ce Convert test to use FileCheck.
llvm-svn: 209528
2014-05-23 16:51:13 +00:00
Aaron Ballman 3892013a8a Teach the table generated emitPseudoExpansionLowering function to not emit a switch statement containing only a default statement (and no cases). Updated some of the code to use range-based for loops as well. No functional changes.
llvm-svn: 209521
2014-05-23 15:33:39 +00:00
Rafael Espindola 6314ad41d1 Aliases are always definition, delete dead code.
While at it, use a range loop.

llvm-svn: 209519
2014-05-23 15:18:06 +00:00
Rafael Espindola a31f3e50dc Delete dead code.
GV is never used past this point. This was probably a copy and paste error.

llvm-svn: 209518
2014-05-23 15:07:51 +00:00
Daniel Sanders 683ed961e1 [mips] Work around inconsistency in llvm-mc's placement of fixup markers
Summary:
Add a second fixup table to MipsAsmBackend::getFixupKindInfo() to correctly
position llvm-mc's fixup placeholders for big-endian.

See PR19836 for full details of the issue. To summarize, the fixup placeholders
do not account for endianness properly and the implementations of
getFixupKindInfo() for each target are measuring MCFixupKindInfo.TargetOffset
from different ends of the instruction encoding to compensate.

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3889

llvm-svn: 209514
2014-05-23 13:35:24 +00:00
Daniel Sanders 8966caab05 [mips][mips64r6] t(eq|ge|lt|ne)i and t(ge|lt)iu are not available in MIPS32r6/MIPS64r6
Summary: Depends on D3872

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3891

llvm-svn: 209513
2014-05-23 13:24:08 +00:00
Daniel Sanders ac27263512 [mips][mips64r6] [ls][dw][lr] are not available in MIPS32r6/MIPS64r6
Summary:
Instead the system is required to provide some means of handling unaligned
load/store without special instructions. Options include full hardware
support, full trap-and-emulate, and hybrids such as hardware support within
a cache line and trap-and-emulate for multi-line accesses.

MipsSETargetLowering::allowsUnalignedMemoryAccesses() has been configured to
assume that unaligned accesses are 'fast' on the basis that I expect few
hardware implementations will opt for pure-software handling of unaligned
accesses. The ones that do handle it purely in software can override this.

mips64-load-store-left-right.ll has been merged into load-store-left-right.ll

The stricter testing revealed a Bits!=Bytes bug in passByValArg(). This has
been fixed and the variables renamed to clarify the units they hold.

Reviewers: zoran.jovanovic, jkolek, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3872

llvm-svn: 209512
2014-05-23 13:18:02 +00:00
Kostya Serebryany c7895a83d2 [asan] properly instrument memory accesses that have small alignment (smaller than min(8,size)) by making two checks instead of one. This may slowdown some cases, e.g. long long on 32-bit or wide loads produced after loop unrolling. The benefit is higher sencitivity.
llvm-svn: 209508
2014-05-23 11:52:07 +00:00
Pekka Jaaskelainen 23b222cc50 Updated the llvm.mem.parallel_loop_access semantics to include the possibility
to have only some of the loop's memory instructions be annotated and still _help_
the loop carried dependence analysis. 

This was discussed in the llvmdev ML (topic: "parallel loop metadata question").

llvm-svn: 209507
2014-05-23 11:35:46 +00:00
Bradley Smith 63c8b1bcb3 Fixup sys::getHostCPUFeatures crypto names so it doesn't clash with kernel headers
llvm-svn: 209506
2014-05-23 10:14:13 +00:00
Simon Atanasyan 84242dc774 [YAML] Add an optional argument `EnumMask` to the `yaml::IO::bitSetCase()`.
Some bit-set fields used in ELF file headers in fact contain two parts.
The first one is a regular bit-field. The second one is an enumeraion.
For example ELF header `e_flags` for MIPS target might contain the
following values:

Bit-set values:

  EF_MIPS_NOREORDER = 0x00000001
  EF_MIPS_PIC       = 0x00000002
  EF_MIPS_CPIC      = 0x00000004
  EF_MIPS_ABI2      = 0x00000020

Enumeration:

  EF_MIPS_ARCH_32   = 0x50000000
  EF_MIPS_ARCH_64   = 0x60000000
  EF_MIPS_ARCH_32R2 = 0x70000000
  EF_MIPS_ARCH_64R2 = 0x80000000

For printing bit-sets we use the `yaml::IO::bitSetCase()`. It does not
support bit-set/enumeration combinations and prints too many flags from
an enumeration part. This patch fixes this problem. New method
`yaml::IO::maskedBitSetCase()` handle "enumeration" part of bitset
defined by provided mask.

Patch reviewed by Nick Kledzik and Sean Silva.

llvm-svn: 209504
2014-05-23 08:07:09 +00:00
Yaron Keren 683b7e0874 Typedef NumeredTypesMapTy is not used anywhere.
llvm-svn: 209502
2014-05-23 07:31:25 +00:00
Jingyue Wu 69a6685c8d Test commit.
The keyword "virtual" is not necessary.

llvm-svn: 209501
2014-05-23 06:30:12 +00:00
Filipe Cabecinhas b498859228 llvm-ar: Output the file we errored on.
llvm-svn: 209500
2014-05-23 05:52:12 +00:00
David Blaikie 4860225570 Rename a couple of variables to be more accurate.
It's not really a "ScopeDIE", as such - it's the abstract function
definition's DIE. And we usually use "SP" for subprograms, rather than
"Sub".

llvm-svn: 209499
2014-05-23 05:03:23 +00:00
David Blaikie 96fb9024f2 DebugInfo: Fix cross-CU references for scopes (and variables within those scopes) in abstract definitions of cross-CU inlined functions
Found by Adrian Prantl during post-commit review of r209335.

llvm-svn: 209498
2014-05-23 04:23:06 +00:00
Saleem Abdulrasool a4f1ec043c MC: remove unnecessary restriction on tests
Rafael correctly pointed out that the restriction is unnecessary.  Although the
tests are intended to ensure that we dont abort due to an assertion, running the
tests in all modes is better since it also ensures that we dont crash without
assertions.  Always run these tests to ensure that we can handle invalid input
correctly.

llvm-svn: 209496
2014-05-23 02:56:51 +00:00
Jiangning Liu 4b5b757d65 [ARM64] Fix a bug in shuffle vector lowering to generate corect vext ISD with swapped input vectors.
llvm-svn: 209495
2014-05-23 02:54:50 +00:00
Richard Smith 36e1295a2b Attempt to placate compilers that warn on casts between pointer-to-object and
pointer-to-function types.

llvm-svn: 209490
2014-05-23 01:22:46 +00:00
Justin Bogner cbb8438bb3 ScalarEvolution: Fix handling of AddRecs in isKnownPredicate
ScalarEvolution::isKnownPredicate() can wrongly reduce a comparison
when both the LHS and RHS are SCEVAddRecExprs. This checks that both
LHS and RHS are guarded in the case when both are SCEVAddRecExprs.

The test case is against indvars because I could not find a way to
directly test SCEV.

Patch by Sanjay Patel!

llvm-svn: 209487
2014-05-23 00:06:56 +00:00
Michael J. Spencer 6a0bc99542 [Graph Writer] Limit the length of the graph name because Windows can't handle it.
Windows can't handle paths longer than 260 code points without \\?\. Even
with \\?\ it can't handle path components longer than 255 code points. So
limit graph names to the arbitrary length of 140. Random characters are still
added to the end, so it's ok if graph names collide.

Differential Revision: http://reviews.llvm.org/D3883

llvm-svn: 209483
2014-05-22 23:32:18 +00:00
Eric Christopher 276d7a1434 Make these bool bitfields.
llvm-svn: 209481
2014-05-22 23:09:57 +00:00
Lang Hames 7f9fc2b339 [RuntimeDyld] Teach RuntimeDyldMachO how to handle scattered VANILLA relocs on
i386.

This fixes two more MCJIT regression tests on i386:

  ExecutionEngine/MCJIT/2003-05-06-LivenessClobber.ll
  ExecutionEngine/MCJIT/2013-04-04-RelocAddend.ll

The implementation of processScatteredVANILLA is tasteless (*ba-dum-ching*),
but I'm working on a substantial tidy-up of RuntimeDyldMachO that should
improve things.

This patch also fixes a type-o in RuntimeDyldMachO::processSECTDIFFRelocation,
and teaches that method to skip over the PAIR reloc following the SECTDIFF.

<rdar://problem/16961886>

llvm-svn: 209478
2014-05-22 22:30:13 +00:00
Eric Christopher d328db1318 Update some AliasAnalysis pass docs for getAdjustedAnalysisPointer.
Patch by George Burgess.

llvm-svn: 209467
2014-05-22 19:38:25 +00:00
Matt Arsenault 46b51b7f62 R600: Add definition for flat address space ID.
Use 4 since that's probably what it will be for spir.
Move ADDRESS_NONE to the end to keep the constant_buffer_* values
unchanged, since apparently a bunch of r600 tests use those directly.

llvm-svn: 209463
2014-05-22 18:27:07 +00:00
Matt Arsenault 05e96f4444 R600: Try to convert BFE back to standard bit ops when possible.
This allows existing DAG combines to work on them, and then
we can re-match to BFE if necessary during instruction selection.

llvm-svn: 209462
2014-05-22 18:09:12 +00:00
Matt Arsenault 5565f65e13 R600: Add dag combine for BFE
llvm-svn: 209461
2014-05-22 18:09:07 +00:00
Matt Arsenault bf8694d36d R600: Implement ComputeNumSignBitsForTargetNode for BFE
llvm-svn: 209460
2014-05-22 18:09:03 +00:00
Matt Arsenault af6df9d943 R600: Implement computeMaskedBitsForTargetNode for BFE
llvm-svn: 209459
2014-05-22 18:09:00 +00:00
Matt Arsenault 493c5f1bc4 R600: Expand mul24 for GPUs without it
llvm-svn: 209458
2014-05-22 18:00:24 +00:00
Matt Arsenault f15a05623e R600: Expand mad24 for GPUs without it
llvm-svn: 209457
2014-05-22 18:00:20 +00:00
Matt Arsenault eb260206c3 R600: Add intrinsics for mad24
llvm-svn: 209456
2014-05-22 18:00:15 +00:00
Eric Christopher 9eff5178f1 Return false if we're not going to do anything.
llvm-svn: 209455
2014-05-22 17:49:33 +00:00
Matt Arsenault f37abc71de R600/SI: Move instruction pattern to instruction definition
llvm-svn: 209454
2014-05-22 17:45:20 +00:00
Diego Novillo 0b761a48cf Remove LLVMContextImpl::optimizationRemarkEnabledFor.
Summary:
This patch moves the handling of -pass-remarks* over to
lib/DiagnosticInfo.cpp. This allows the removal of the
optimizationRemarkEnabledFor functions from LLVMContextImpl, as they're
not needed anymore.

Reviewers: qcolombet

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D3878

llvm-svn: 209453
2014-05-22 17:19:01 +00:00
Andrea Di Biagio c8dd1ad85b [X86] Improve the lowering of BITCAST from MVT::f64 to MVT::v4i16/MVT::v8i8.
This patch teaches the x86 backend how to efficiently lower ISD::BITCAST dag
nodes from MVT::f64 to MVT::v4i16 (and vice versa), and from MVT::f64 to
MVT::v8i8 (and vice versa).

This patch extends the logic from revision 208107 to also handle MVT::v4i16
and MVT::v8i8. Also, this patch correctly propagates Undef values when
performing the widening of a vector (example: when widening from v2i32 to
v4i32, the upper 64bits of the resulting vector are 'undef').

llvm-svn: 209451
2014-05-22 16:21:39 +00:00
Tim Northover b2a6fdb11a ARM64: remove '#' from annotation of add/sub immediate
The full string used to be "// =#12" for example, which looks too
busy.

llvm-svn: 209443
2014-05-22 14:20:05 +00:00
Diego Novillo 7f8af8bf91 Add support for missed and analysis optimization remarks.
Summary:
This adds two new diagnostics: -pass-remarks-missed and
-pass-remarks-analysis. They take the same values as -pass-remarks but
are intended to be triggered in different contexts.

-pass-remarks-missed is used by LLVMContext::emitOptimizationRemarkMissed,
which passes call when they tried to apply a transformation but
couldn't.

-pass-remarks-analysis is used by LLVMContext::emitOptimizationRemarkAnalysis,
which passes call when they want to inform the user about analysis
results.

The patch also:

1- Adds support in the inliner for the two new remarks and a
   test case.

2- Moves emitOptimizationRemark* functions to the llvm namespace.

3- Adds an LLVMContext argument instead of making them member functions
   of LLVMContext.

Reviewers: qcolombet

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D3682

llvm-svn: 209442
2014-05-22 14:19:46 +00:00
Tim Northover f9e798ba6a Segmented stacks: omit __morestack call when there's no frame.
Patch by Florian Zeitz

llvm-svn: 209436
2014-05-22 13:03:43 +00:00
Tim Northover 2dce43c26f ARM64: these work too
llvm-svn: 209430
2014-05-22 12:14:49 +00:00
Tim Northover 5949b60550 Yes they do
llvm-svn: 209429
2014-05-22 12:14:02 +00:00
Tim Northover 4a3ab28ac7 ARM64: model pre/post-indexed operations properly.
We should be keeping track of the writeback on these instructions,
otherwise we're relying on LLVM's stupidity for correct code.

Fortunately, the MC layer can now handle all required constraints,
which means we can get rid of the CodeGen only PseudoInsts too.

llvm-svn: 209426
2014-05-22 11:56:20 +00:00
Tim Northover c350acfda5 ARM64: separate load/store operands to simplify assembler
This changes ARM64 to use separate operands for each component of an
address, and look for separate '[', '$Rn, ..., ']' tokens when
parsing.

This allows us to do away with quite a bit of special C++ code to
handle monolithic "addressing modes" in the MC components. The more
incremental matching of the assembler operands also allows for better
diagnostics when LLVM is presented with invalid input.

Most of the complexity here is with the register-offset instructions,
which were extremely dodgy beforehand: even when the instruction used
wM, LLVM's model had xM as an operand. We papered over this
discrepancy before, but that approach doesn't work now so I split them
into separate X and W variants.

llvm-svn: 209425
2014-05-22 11:56:09 +00:00
Daniel Sanders 18b68e16af [mips] Make unalignedload.ll test stricter and easier to modify for MIPS32r6/MIPS64r6
Summary:
* Split into two functions, one to test each struct.
* R0 and R2 must be defined by an lw with a %got reference to the correct
  symbol.
* Test for $4 (first argument) where appropriate instead of accepting any
  register.
* Test that the two lbu's are correctly combined into $4

Depends on D3844

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3845

llvm-svn: 209424
2014-05-22 11:55:04 +00:00
Daniel Sanders e1f46e58c9 [mips] Change lwl and lwr in inlineasm_constraint.ll to lw
Summary:
lwl and lwr are not available in MIPS32r6/MIPS64r6. The purpose of the test
is to check that the '$1' expands to '0($x)' rather than to test something related
to the lwl or lwr instructions so we can simply switch to lw.

Depends on D3842

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3844

llvm-svn: 209423
2014-05-22 11:51:06 +00:00
Daniel Sanders b230595839 [mips] Use addiu in inline assembly tests since addi is not available in all ISA's
Summary:
This patch is necessary so that they do not fail on MIPS32r6/MIPS64r6 when
-integrated-as is enabled by default and we correctly detect the host CPU.

No functional change since these tests are testing the behaviour of the
constraint used for the third operand rather than the mnemonic.

Depends on D3842

Reviewers: zoran.jovanovic, jkolek, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3843

llvm-svn: 209421
2014-05-22 11:46:58 +00:00
Bradley Smith 9288b2181f Extend sys::getHostCPUFeatures to work on AArch64 platforms
llvm-svn: 209420
2014-05-22 11:44:34 +00:00
Daniel Sanders 36ff7c2adc [mips][mips64r6] addi is not available on MIPS32r6/MIPS64r6
Summary: Depends on D3787. Tablegen will raise an assertion without it.

Reviewers: zoran.jovanovic, jkolek, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3842

llvm-svn: 209419
2014-05-22 11:42:31 +00:00
Daniel Sanders a3566c633d [mips][mips64r6] Test that paired single instructions are invalid
Summary:
These emit the 'unknown instruction' instead of the correct error
because they have not been implemented in LLVM for any MIPS ISA.

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3841

llvm-svn: 209418
2014-05-22 11:37:38 +00:00
Daniel Sanders 5c582b2f6d [mips][mips64r6] Add b[on]vc
Summary:
This required me to implement the disassembler for MIPS64r6 since the encodings
are ambiguous with other instructions. This in turn revealed a few
assembly/disassembly bugs which I have fixed.

* da[ht]i only take two operands according to the spec, not three.
* DecodeBranchTarget2[16] correctly handles wider immediates than simm16
  * Also made non-functional change to DecodeBranchTarget and
    DecodeBranchTargetMM to keep implementation style consistent between
    them.
* Difficult encodings are handled by a custom decode method on the most
  general encoding in the group. This method will convert the MCInst to a
  different opcode if necessary.

DecodeBranchTarget is not currently the inverse of getBranchTargetOpValue
so disassembling some branch instructions emit incorrect output. This seems
to affect branches with delay slots on all MIPS ISA's. I've left this bug
for now and temporarily removed the check for the immediate on
bc[12]eqz/bc[12]nez in the MIPS32r6/MIPS64r6 tests.

jialc and jic crash the disassembler for some reason. I've left these
instructions commented out for the moment.

Depends on D3760

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3761

llvm-svn: 209415
2014-05-22 11:23:21 +00:00
Tim Northover 0f6272271e ARM64: assert if we see i64 -> i64 extend in the DAG.
Should be no change in behaviour, but it makes the intended
functionality a bit clearer and means we only have to reason about
real extend operations.

llvm-svn: 209409
2014-05-22 07:41:37 +00:00
Tim Northover 71d04225cf AArch64/ARM64: enable more AArch64 tests.
llvm-svn: 209408
2014-05-22 07:40:55 +00:00
Saleem Abdulrasool 9dd60cfb64 MC: initialise MCAsmParser variable
Properly initialise HadError to false during construction.  Detected as
use-of-uninitialised variable by MSan!

llvm-svn: 209393
2014-05-22 06:02:59 +00:00
Eric Christopher 65382d7316 Remove unused variable.
llvm-svn: 209391
2014-05-22 05:33:03 +00:00
Saleem Abdulrasool 2bd1262a32 ARM: introduce llvm.arm.undefined intrinsic
This intrinsic permits the emission of platform specific undefined sequences.
ARM has reserved the 0xde opcode which takes a single integer parameter (ignored
by the CPU).  This permits the operating system to implement custom behaviour on
this trap.  The llvm.arm.undefined intrinsic is meant to provide a means for
generating the target specific behaviour from the frontend.  This is
particularly useful for Windows on ARM which has made use of a series of these
special opcodes.

llvm-svn: 209390
2014-05-22 04:46:46 +00:00
Matt Arsenault c3a73c3087 R600/SI: Match fp_to_uint / uint_to_fp for f64
llvm-svn: 209388
2014-05-22 03:20:30 +00:00
Saleem Abdulrasool 6663f8f2c0 MC: formalise some assertions into proper errors
Now that clang can be used as an assembler via the IAS, invalid assembler inputs
would cause the assertions to trigger.  Although we cannot recover from the
errors here, nor provide caret diagnostics, attempt to handle them slightly more
gracefully by reporting a fatal error.

llvm-svn: 209387
2014-05-22 02:18:10 +00:00
Eric Christopher 0e6e7cf385 Override runOnMachineFunction for ARMISelDAGToDAG so that we can
reset the subtarget on each function.

llvm-svn: 209386
2014-05-22 02:00:27 +00:00
Eric Christopher 4f09c59243 Override runOnMachineFunction for X86ISelDAGToDAG so that we can
reset the subtarget on each function.

llvm-svn: 209384
2014-05-22 01:53:26 +00:00
Eric Christopher 0d5c99eb08 Avoid using subtarget features when adding X86 specific passes to
the pass pipeline.

llvm-svn: 209382
2014-05-22 01:46:02 +00:00
Eric Christopher e0bd2fa927 Remove extra local variable.
llvm-svn: 209381
2014-05-22 01:45:59 +00:00
Eric Christopher 463b84b48b Rename createGlobalBaseRegPass -> createX86GlobalBaseRegPass to make
it obvious that it's a target specific pass.

llvm-svn: 209380
2014-05-22 01:45:57 +00:00