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391 Commits

Author SHA1 Message Date
Evan Cheng 4704baa555 Fix assembly code for atomic operations. 
llvm-svn: 49869
 2008-04-17 21:26:35 +00:00
Nate Begeman 7417348a7e 80 col fix 
llvm-svn: 49569
 2008-04-12 00:47:57 +00:00
Evan Cheng 29e62a59f3 Allow certain lea instructions to be rematerialized. 
llvm-svn: 48855
 2008-03-27 01:41:09 +00:00
Arnold Schwaighofer 7da2bceb3b Don't loose incoming argument registers. Fix documentation style. 
llvm-svn: 48545
 2008-03-19 16:39:45 +00:00
Evan Cheng 0e7b00d79f Replace all target specific implicit def instructions with a target independent one: TargetInstrInfo::IMPLICIT_DEF. 
llvm-svn: 48380
 2008-03-15 00:03:38 +00:00
Christopher Lamb dd55d3f1b2 Get rid of a pseudo instruction and replace it with subreg based operation on real instructions, ridding the asm printers of the hack used to do this previously. In the process, update LowerSubregs to be careful about eliminating copies that have side affects. 
Note: the coalescer will have to be careful about this too, when it starts coalescing insert_subreg nodes.
llvm-svn: 48329
 2008-03-13 05:47:01 +00:00
Christopher Lamb aa7c2105de Recommitting parts of r48130. These do not appear to cause the observed failures. 
llvm-svn: 48223
 2008-03-11 10:09:17 +00:00
Chris Lattner 1bd44363f2 Change the model for FP Stack return to use fp operands on the 
RET instruction instead of using FpSET_ST0_32.  This also generalizes
the code to handling returning of multiple FP results.

llvm-svn: 48209
 2008-03-11 03:23:40 +00:00
Evan Cheng d4e1d9eeb2 Revert 48125, 48126, and 48130 for now to unbreak some x86-64 tests. 
llvm-svn: 48167
 2008-03-10 19:31:26 +00:00
Christopher Lamb 4ba3f0430b Allow insert_subreg into implicit, target-specific values. 
Change insert/extract subreg instructions to be able to be used in TableGen patterns.
Use the above features to reimplement an x86-64 pseudo instruction as a pattern.

llvm-svn: 48130
 2008-03-10 06:12:08 +00:00
Andrew Lenharth 357061a74d 64bit CAS on 32bit x86. 
llvm-svn: 47929
 2008-03-05 01:15:49 +00:00
Evan Cheng 59d58ab8c4 80 column violations. 
llvm-svn: 47878
 2008-03-04 03:20:06 +00:00
Evan Cheng 33ff36321e Remove -always-fold-and-in-test. 
llvm-svn: 47871
 2008-03-04 00:40:35 +00:00
Andrew Lenharth 20bcdba9ca good catch anton 
llvm-svn: 47800
 2008-03-01 23:18:21 +00:00
Andrew Lenharth f5c90ec12c make CAS work 
llvm-svn: 47799
 2008-03-01 22:27:48 +00:00
Andrew Lenharth d032c33300 all but CAS working on x86 
llvm-svn: 47798
 2008-03-01 21:52:34 +00:00
Andrew Lenharth 0070dd1de3 Add lock prefix support to x86. Also add the instructions necessary for the atomic ops. They are still marked pseudo, since I cannot figure out what format to use, but they are the correct opcode. 
llvm-svn: 47795
 2008-03-01 13:37:02 +00:00
Andrew Lenharth 95528943e9 Atomic op support. If any gcc test uses __sync builtins, it might start failing on archs that haven't implemented them yet 
llvm-svn: 47430
 2008-02-21 06:45:13 +00:00
Evan Cheng b6b69208ba Poorly named option. 
llvm-svn: 47400
 2008-02-20 20:57:32 +00:00
Evan Cheng 5ce8dd93ef Add hidden option -x86-fold-and-in-test to test the effect the test / and folding change. 
llvm-svn: 47351
 2008-02-19 23:36:51 +00:00
Chris Lattner 97b9662f78 Don't fold and's into test instructions if they have multiple uses. 
This compiles test-nofold.ll into:

_test:
	movl	$15, %ecx
	andl	4(%esp), %ecx
	testl	%ecx, %ecx
	movl	$42, %eax
	cmove	%ecx, %eax
	ret

instead of:
_test:
	movl	4(%esp), %eax
	movl	%eax, %ecx
	andl	$15, %ecx
	testl	$15, %eax
	movl	$42, %eax
	cmove	%ecx, %eax
	ret

llvm-svn: 47330
 2008-02-19 17:37:35 +00:00
Evan Cheng a20a773654 Fix a x86-64 codegen deficiency. Allow gv + offset when using rip addressing mode. 
Before:
_main:
        subq    $8, %rsp
        leaq    _X(%rip), %rax
        movsd   8(%rax), %xmm1
        movss   _X(%rip), %xmm0
        call    _t
        xorl    %ecx, %ecx
        movl    %ecx, %eax
        addq    $8, %rsp
        ret
Now:
_main:
        subq    $8, %rsp
        movsd   _X+8(%rip), %xmm1
        movss   _X(%rip), %xmm0
        call    _t
        xorl    %ecx, %ecx
        movl    %ecx, %eax
        addq    $8, %rsp
        ret

Notice there is another idiotic codegen issue that needs to be fixed asap:
xorl    %ecx, %ecx
movl    %ecx, %eax

llvm-svn: 46850
 2008-02-07 08:53:49 +00:00
Nate Begeman e14fdfaecd SSE 4.1 Intrinsics and detection 
llvm-svn: 46681
 2008-02-03 07:18:54 +00:00
Duncan Sands 95d46ef887 The last pieces needed for loading arbitrary 
precision integers.  This won't actually work
(and most of the code is dead) unless the new
legalization machinery is turned on.  While
there, I rationalized the handling of i1, and
removed some bogus (and unused) sextload patterns.
For i1, this could result in microscopically
better code for some architectures (not X86).
It might also result in worse code if annotating
with AssertZExt nodes turns out to be more harmful
than helpful.

llvm-svn: 46280
 2008-01-23 20:39:46 +00:00
Chris Lattner 1ea55cf816 This commit changes: 
1. Legalize now always promotes truncstore of i1 to i8. 
2. Remove patterns and gunk related to truncstore i1 from targets.
3. Rename the StoreXAction stuff to TruncStoreAction in TLI.
4. Make the TLI TruncStoreAction table a 2d table to handle from/to conversions.
5. Mark a wide variety of invalid truncstores as such in various targets, e.g.
   X86 currently doesn't support truncstore of any of its integer types.
6. Add legalize support for truncstores with invalid value input types.
7. Add a dag combine transform to turn store(truncate) into truncstore when
   safe.

The later allows us to compile CodeGen/X86/storetrunc-fp.ll to:

_foo:
	fldt	20(%esp)
	fldt	4(%esp)
	faddp	%st(1)
	movl	36(%esp), %eax
	fstps	(%eax)
	ret

instead of:

_foo:
	subl	$4, %esp
	fldt	24(%esp)
	fldt	8(%esp)
	faddp	%st(1)
	fstps	(%esp)
	movl	40(%esp), %eax
	movss	(%esp), %xmm0
	movss	%xmm0, (%eax)
	addl	$4, %esp
	ret

llvm-svn: 46140
 2008-01-17 19:59:44 +00:00
Chris Lattner 9a249b0ce5 rename SDTRet -> SDTNone. 
Move definition of 'trap' sdnode up from x86 instrinfo to targetselectiondag.td.

llvm-svn: 46017
 2008-01-15 22:02:54 +00:00
Chris Lattner 3c3fefde06 no need to expand ISD::TRAP to X86ISD::TRAP, just match ISD::TRAP. 
llvm-svn: 46015
 2008-01-15 21:58:22 +00:00
Anton Korobeynikov 59e6d533bd Fix JIT encoding of trap/ud2 instruction 
llvm-svn: 46012
 2008-01-15 21:40:02 +00:00
Anton Korobeynikov 6bbbc4cbfa For PR1839: add initial support for __builtin_trap. llvm-gcc part is missed 
as well as PPC codegen

llvm-svn: 46001
 2008-01-15 07:02:33 +00:00
Chris Lattner 806dd0e2ac remove xchg and shift-reg-by-1 instructions, which are dead. 
llvm-svn: 45870
 2008-01-11 18:00:50 +00:00
Chris Lattner 9283173061 more flags set right 
llvm-svn: 45860
 2008-01-11 07:18:17 +00:00
Chris Lattner 8e60f2c996 IMPLICIT_USE and IMPLICIT_DEF are dead, remove them. 
llvm-svn: 45838
 2008-01-10 19:27:54 +00:00
Chris Lattner 317332fc2a Start inferring side effect information more aggressively, and fix many bugs in the 
x86 backend where instructions were not marked maystore/mayload, and perf issues where
instructions were not marked neverHasSideEffects.  It would be really nice if we could
write patterns for copy instructions.

I have audited all the x86 instructions down to MOVDQAmr.  The flags on others and on
other targets are probably not right in all cases, but no clients currently use this
info that are enabled by default.

llvm-svn: 45829
 2008-01-10 07:59:24 +00:00
Chris Lattner 2e38f2458c rename X86InstrX86-64.td -> X86Instr64bit.td 
llvm-svn: 45826
 2008-01-10 05:50:42 +00:00
Chris Lattner aca7ca3730 remove explicit sets of 'neverHasSideEffects' that can now be 
inferred from the instr patterns.

llvm-svn: 45824
 2008-01-10 05:45:39 +00:00
Chris Lattner 94de7bc3aa get def use info more correct. 
llvm-svn: 45821
 2008-01-10 05:12:37 +00:00
Chris Lattner b296b0f1c1 The pic base can't be duplicated. 
llvm-svn: 45668
 2008-01-06 23:49:32 +00:00
Chris Lattner a4ce4f6987 rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate. 
llvm-svn: 45667
 2008-01-06 23:38:27 +00:00
Chris Lattner 9fa8ae6c6b getting the pic base has no side effects. 
llvm-svn: 45618
 2008-01-05 03:54:32 +00:00
Evan Cheng f55b7381af Combine MovePCtoStack + POP32r into one instruction MOVPC32r so it can be moved if needed. 
llvm-svn: 45605
 2008-01-05 00:41:47 +00:00
Chris Lattner f3ebc3f3d2 Remove attribution from file headers, per discussion on llvmdev. 
llvm-svn: 45418
 2007-12-29 20:36:04 +00:00
Evan Cheng f4f52dbc8c Fix JIT code emission of X86::MovePCtoStack. 
llvm-svn: 45307
 2007-12-22 02:26:46 +00:00
Bill Wendling b3d85a5d4b Add "mayHaveSideEffects" and "neverHasSideEffects" flags to some instructions. I 
based what flag to set on whether it was already marked as
"isRematerializable". If there was a further check to determine if it's "really"
rematerializable, then I marked it as "mayHaveSideEffects" and created a check
in the X86 back-end similar to the remat one.

llvm-svn: 45132
 2007-12-17 23:07:56 +00:00
Evan Cheng a56e6ff9a7 Fix bsf / bsr jit encoding. 
llvm-svn: 45037
 2007-12-14 18:49:43 +00:00
Dan Gohman 9d2e9e376f Fix Intel asm syntax for the bsr and bsf instructions. 
llvm-svn: 45030
 2007-12-14 15:10:00 +00:00
Evan Cheng 0e6408124e Fix ctlz and cttz. llvm definition requires them to return number of bits in of the src type when value is zero. 
llvm-svn: 45029
 2007-12-14 08:30:15 +00:00
Evan Cheng e9fbc3f014 Implement ctlz and cttz with bsr and bsf. 
llvm-svn: 45024
 2007-12-14 02:13:44 +00:00
Evan Cheng 827d30db19 Fold some and + shift in x86 addressing mode. 
llvm-svn: 44970
 2007-12-13 00:43:27 +00:00
Evan Cheng 6e68381e02 Implicit def instructions, e.g. X86::IMPLICIT_DEF_GR32, are always re-materializable and they should not be spilled. 
llvm-svn: 44960
 2007-12-12 23:12:09 +00:00
Bill Wendling 77b13af9a6 Unifacalize the CALLSEQ{START,END} stuff. 
llvm-svn: 44045
 2007-11-13 09:19:02 +00:00