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341 Commits

Author SHA1 Message Date
Joey Gouly e6d165ccb4 [ARMv8] Add MC support for the new load/store acquire/release instructions. 
llvm-svn: 189388
 2013-08-27 17:38:16 +00:00
Tim Northover 421804420d ARM: use TableGen patterns to select CMOV operations. 
Back in the mists of time (2008), it seems TableGen couldn't handle the
patterns necessary to match ARM's CMOV node that we convert select operations
to, so we wrote a lot of fairly hairy C++ to do it for us.

TableGen can deal with it now: there were a few minor differences to CodeGen
(see tests), but nothing obviously worse that I could see, so we should
probably address anything that *does* come up in a localised manner.

llvm-svn: 188995
 2013-08-22 09:57:11 +00:00
Joey Gouly 943dd59ed5 [ARMv8] Add NEON instructions VCVT{A, N, P, M}. 
llvm-svn: 186574
 2013-07-18 11:53:22 +00:00
Joey Gouly df68600f44 [ARMv8] Add support for the NEON instructions vmaxnm/vminnm. 
This adds a new class for non-predicable NEON instructions and a
new DecoderNamespace for v8 NEON instructions.

llvm-svn: 186504
 2013-07-17 13:59:38 +00:00
Joey Gouly 0f12aa2b0f Add MC assembly/disassembly support for VRINT{A, N, P, M} to V8FP. 
llvm-svn: 185929
 2013-07-09 11:26:18 +00:00
Joey Gouly 2d0175e8fb Add MC assembly/disassembly support for VCVT{A, N, P, M} to V8FP. 
llvm-svn: 185922
 2013-07-09 09:59:04 +00:00
Joey Gouly 2efaa733a2 Add MC support for the v8fp instructions: vmaxnm and vminnm. 
llvm-svn: 185767
 2013-07-06 20:50:18 +00:00
Joey Gouly cc4ff9e907 Add support for MC assembling and disassembling of vsel{ge, gt, eq, vs} instructions. 
This adds a new decoder table/namespace 'VFPV8', as these instructions have their
top 4 bits as 0b1111, while other Thumb instructions have 0b1110.

llvm-svn: 185642
 2013-07-04 14:57:20 +00:00
Tim Northover 2c45a383a8 ARM: fix more cases where predication may or may not be allowed 
Unfortunately this addresses two issues (by the time I'd disentangled the logic
it wasn't worth putting it back to half-broken):

+ Coprocessor instructions should all be predicable in Thumb mode.
+ BKPT should never be predicable.

llvm-svn: 184965
 2013-06-26 16:52:40 +00:00
Tim Northover 4173e29a98 ARM: add fstmx and fldmx instructions for assembly 
These instructions are deprecated oddities, but we still need to be able to
disassemble (and reassemble) them if and when they're encountered.

Patch by Amaury de la Vieuville.

llvm-svn: 183011
 2013-05-31 15:55:51 +00:00
Bob Wilson e8a549cd92 Add LLVM support for Swift. 
llvm-svn: 164899
 2012-09-29 21:43:49 +00:00
Silviu Baranga ddc67a7655 Added the missing bit definition for the 4th bit of the STR (post reg) instruction. It is now set to 0. The patch also sets the unpredictable mask for SEL and SXTB-type instructions. 
llvm-svn: 156609
 2012-05-11 09:28:27 +00:00
Jim Grosbach 2937df45a8 ARM: Update NEON assembly two-operand aliases. 
Use the new TwoOperandAliasConstraint to handle lots of the two-operand aliases
for NEON instructions. There's still more to go, but this is a good chunk of
them.

llvm-svn: 155210
 2012-04-20 18:12:54 +00:00
Silviu Baranga ca45af9a75 Added support for disassembling unpredictable swp/swpb ARM instructions. 
llvm-svn: 155004
 2012-04-18 14:18:57 +00:00
Jia Liu b22310fda6 Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 
llvm-svn: 150878
 2012-02-18 12:03:15 +00:00
James Molloy d9ba4fd48f Teach the MC and disassembler about SoftFail, and hook it up to UNPREDICTABLE on ARM. Wire this to tBLX in order to provide test coverage. 
llvm-svn: 150169
 2012-02-09 10:56:31 +00:00
Jim Grosbach 681db34eae NEON add correct predicates for some asm aliases. 
llvm-svn: 148815
 2012-01-24 17:23:29 +00:00
Jim Grosbach d28ef9ac46 Simplify some NEON assembly pseudo definitions. 
Let the generic token alias definitions handle the data subtype
suffices. We don't need explicit versions for each.

llvm-svn: 148718
 2012-01-23 19:39:08 +00:00
Jim Grosbach f0d25117c6 ARM VFP add encoding of the bitcount to fixed-point<-->floating point. insns. 
The value from the operands isn't right yet, but we weren't encoding it at
all previously. The parser needs to twiddle the values when building the
instruction.

Partial for: rdar://10558523

llvm-svn: 147170
 2011-12-22 19:55:21 +00:00
Jim Grosbach 9227f39c53 ARM add more 'gas' compatibility aliases for NEON instructions. 
llvm-svn: 146507
 2011-12-13 20:08:32 +00:00
Jim Grosbach ba7d6ed05d ARM VSHR implied destination operand form aliases. 
llvm-svn: 146192
 2011-12-08 22:06:06 +00:00
Jim Grosbach 2cf294a213 ARM tidy up and remove no longer needed InstAlias definitions. 
The TokenAlias handling of data type suffices renders these unnecessary.

llvm-svn: 146010
 2011-12-07 01:50:36 +00:00
Jim Grosbach 585ce30b8b ARM Implement ARM ARM Table A7-3 via TokenAlias. 
Data type suffix aliasing. Previously handled via lots of instruction
aliases. Cleanup of those forthcoming.

rdar://10435076

llvm-svn: 146007
 2011-12-07 01:17:58 +00:00
Jim Grosbach fdf9e1587a ARM assembly parsing for the rest of the VMUL data type aliases. 
Finish up rdar://10522016.

llvm-svn: 145846
 2011-12-05 20:29:59 +00:00
Jim Grosbach 0a978ef715 ARM assmebler parsing for two-operand VMUL instructions. 
Combined destination and first source operand for f32 variant of the VMUL
(by scalar) instruction.

rdar://10522016

llvm-svn: 145842
 2011-12-05 19:55:46 +00:00
Jim Grosbach dda976b804 ARM VLD1 single lane assembly parsing. 
llvm-svn: 145712
 2011-12-02 22:01:52 +00:00
Jim Grosbach e7dcbc8691 Clean up aliases for ARM VLD1 single-lane assembly parsing a bit. 
Add the 16-bit lane variants while I'm at it.

llvm-svn: 145693
 2011-12-02 18:52:30 +00:00
Jim Grosbach 003cea6011 ARM assembly parsing for data type suffices on NEON VMOV aliases. 
llvm-svn: 144722
 2011-11-15 22:54:42 +00:00
Jim Grosbach 9c2d9d597b Split out the plain '.{8|16|32|64}' suffix handling. 
Make it easier to deal with aliases for instructions that do require a suffix
but accept more specific variants of the same size.

llvm-svn: 144588
 2011-11-14 23:20:14 +00:00
Jim Grosbach 3d6c0e0bb2 ARM parsing optional datatype suffix for VAND/VEOR/VORR instructions. 
rdar://10435076

llvm-svn: 144587
 2011-11-14 23:11:19 +00:00
Jim Grosbach 3e2c6f380c ARM VLDR/VSTR instructions don't need a size suffix. 
Canonicallize on the non-suffixed form, but continue to accept assembly that
has any correctly sized type suffix.

llvm-svn: 144583
 2011-11-14 23:03:21 +00:00
Jim Grosbach 7996b15724 ARM assembly parsing type suffix options for VLDR/VSTR. 
rdar://10435076

llvm-svn: 144575
 2011-11-14 22:28:39 +00:00
Jim Grosbach 3a3d8e82bc ARM refactor simple immediate asm operand render methods. 
These immediate operands all use the same simple logic for rendering to
MCInst, so have them share the method for doing so.

llvm-svn: 144439
 2011-11-12 00:58:43 +00:00
Jim Grosbach 61db5a59f7 ARM assembly parsing for ASR(immediate). 
Start of rdar://9704684

llvm-svn: 144293
 2011-11-10 16:44:55 +00:00
Jim Grosbach fb2f1d61f4 ARM VLD/VST assembly parsing for symbolic address operands. 
llvm-svn: 143413
 2011-11-01 01:24:45 +00:00
Owen Anderson dde461c8b1 Reapply r143202, with a manual decoding hook for SWP. This change inadvertantly exposed a decoding ambiguity between SWP and CPS that the auto-generated decoder can't handle. 
llvm-svn: 143208
 2011-10-28 18:02:13 +00:00
Jim Grosbach d0637bfc68 ARM NEON assembly parsing and encoding for VDUP(scalar). 
llvm-svn: 141446
 2011-10-07 23:56:00 +00:00
Jim Grosbach 4ab23b5273 ARM assembly parsing and encoding for VMRS/FMSTAT. 
llvm-svn: 141025
 2011-10-03 21:12:43 +00:00
Owen Anderson a9ebf6fb64 Port more encoding tests to decoding tests, and correct an improper Thumb2 pre-indexed load decoding this uncovered. 
llvm-svn: 139522
 2011-09-12 18:56:30 +00:00
Jim Grosbach 7db8d697cf Thumb2 assembly parsing and encoding for LDRD(immediate). 
Refactor operand handling for STRD as well. Tests for that forthcoming.

llvm-svn: 139322
 2011-09-08 22:07:06 +00:00
Jim Grosbach 3343da5424 Thumb2 assembly parsing and encoding for LDR post-indexed. 
More cleanup of the general indexed addressing T2 instructions. Still more to
do, especially for stores.

llvm-svn: 139272
 2011-09-08 01:01:32 +00:00
Jim Grosbach c086f689f8 Thumb2 assembly parsing and encoding for LDR pre-indexed w/ writeback. 
Adjust encoding of writeback load/store instructions to better reflect the
way the operand types are represented.

llvm-svn: 139270
 2011-09-08 00:39:19 +00:00
Owen Anderson 9b7bd15d0b Fix Thumb2 decoding of CPS instructions to mirror ARM decoding of the same instructions. 
llvm-svn: 138339
 2011-08-23 17:45:18 +00:00
Owen Anderson eb1367b2b8 Reject invalid imod values in t2CPS instructions. 
llvm-svn: 138306
 2011-08-22 23:44:04 +00:00
Jim Grosbach 6caa557ae6 Clean up predicates on ARM target instruction aliases. 
llvm-svn: 138249
 2011-08-22 18:04:24 +00:00
Jim Grosbach f86cd37bef Thumb assembly parsing and encoding for MOV. 
llvm-svn: 138076
 2011-08-19 20:46:54 +00:00
Jim Grosbach dbb60f960a Tidy up. Tab character. 
llvm-svn: 138072
 2011-08-19 20:30:19 +00:00
Jim Grosbach 9c92049069 Tab characters. 
llvm-svn: 138066
 2011-08-19 19:41:46 +00:00
Owen Anderson 91a8f9be20 Separate out Thumb1 instructions that need an S bit operand from those that do not, for the purposes of decoding them. 
llvm-svn: 137787
 2011-08-16 23:45:44 +00:00
Jim Grosbach 3e941aee69 ARM thumb assembly parsing for arithmetic flag setting instructions. 
Thumb one requires that many arithmetic instruction forms have an 'S'
suffix. For Thumb2, the whether the suffix is required or precluded depends
on whether the instruction is in an IT block. Use target parser predicates
to check for these sorts of context-sensitive constraints.

llvm-svn: 137746
 2011-08-16 20:45:50 +00:00