Commit Graph

6942 Commits

Author SHA1 Message Date
Arnold Schwaighofer d7e8d92606 Swift: Only build vldm/vstm with q register aligned register lists
Unaligned vldm/vstm need more uops and therefore are slower in general on swift.

radar://14522102

llvm-svn: 189961
2013-09-04 17:41:16 +00:00
Silviu Baranga 5cba070ce2 Fix scheduling for vldm/vstm instructions that load/store more than 32 bytes on Cortex-A9. This also makes the existing code more compact.
llvm-svn: 189958
2013-09-04 17:05:18 +00:00
Jim Grosbach 20c925dbf2 Revert "Revert "ARM: Improve pattern for isel mul of vector by scalar.""
This reverts commit r189648.

Fixes for the previously failing clang-side arm_neon_intrinsics test
cases will be checked in separately.

llvm-svn: 189841
2013-09-03 20:08:17 +00:00
Tilmann Scheller 63872ce19f ARM: Default to the Swift CPU when targeting armv7s/thumbv7s.
Test cases adjusted accordingly.

This fixes rdar://14871821.

llvm-svn: 189766
2013-09-02 17:09:01 +00:00
Tilmann Scheller 8f79ee99be Revert 189756 for now, it doesn't match what rdar://14871821 really wants.
What we really want is to enable Swift by default for *v7s triples (and there already seems to be some logic which attempts to do that). In that case the iOS version doesn't matter. 

llvm-svn: 189763
2013-09-02 15:48:17 +00:00
Tilmann Scheller f49c80178e ARM: Default to Swift when compiling for iOS 6 or later.
Test cases adjusted accordingly.

This fixes rdar://14871821.

llvm-svn: 189756
2013-09-02 12:01:58 +00:00
Charles Davis 8bdfafd505 Move everything depending on Object/MachOFormat.h over to Support/MachO.h.
llvm-svn: 189728
2013-09-01 04:28:48 +00:00
Michael Gottesman b7ecc3e6af Revert "ARM: Improve pattern for isel mul of vector by scalar."
This reverts commit r189619.

The commit was breaking the arm_neon_intrinsic test.

llvm-svn: 189648
2013-08-30 05:36:14 +00:00
Jim Grosbach 04cc76dd53 ARM: Improve pattern for isel mul of vector by scalar.
In addition to recognizing when the multiply's second argument is
coming from an explicit VDUPLANE, also look for a plain scalar
f32 reference and reference it via the corresponding vector
lane.

rdar://14870054

llvm-svn: 189619
2013-08-29 22:41:46 +00:00
Cameron Esfahani 943908b78d Clean up some usage of Triple. The base class has methods for determining if the target is iOS and Linux.
llvm-svn: 189604
2013-08-29 20:23:14 +00:00
Joey Gouly daf0e378d2 [ARMv8]
Fix a few things in one swoop.

# Add some negative tests.
# Fix some formatting issues.
# Add some missing IsThumb / ARMv8
# Fix some outs / ins mistakes.

llvm-svn: 189490
2013-08-28 16:39:20 +00:00
Tim Northover f5769880d9 ARM: Use "dmb sy" for barriers on M-class CPUs
The usual default of "dmb ish" (inner-shareable) isn't even a valid instruction
on v6M or v7M (well, it does the same thing but software is strongly
discouraged from using it) so we should emit a full-system barrier there.

llvm-svn: 189483
2013-08-28 14:39:19 +00:00
Joey Gouly 179e2c0b14 [ARMv8] Add a missing IsThumb to t2LDAEXD.
llvm-svn: 189482
2013-08-28 14:33:35 +00:00
Tim Northover 2e02ed253a ARM: remove unused v(add|sub)hn and vqdml[as]l intrinsics.
Clang is now generating cleaner IR, so this removes the old variants which
should be completely unused.

llvm-svn: 189481
2013-08-28 14:33:33 +00:00
Tim Northover 8854ba7837 ARM: add patterns for vqdmlal with separate vqdmull and vqadds
The vqdmlal and vqdmlls instructions are really just a fused pair consisting of
a vqdmull.sN and a vqadd.sN. This adds patterns to LLVM so that we can switch
Clang's CodeGen over to generating these instead of the special vqdmlal
intrinsics.

llvm-svn: 189480
2013-08-28 12:15:16 +00:00
Joey Gouly e6d165ccb4 [ARMv8] Add MC support for the new load/store acquire/release instructions.
llvm-svn: 189388
2013-08-27 17:38:16 +00:00
Joey Gouly a710d810f5 [ARMv8] Add some negative tests for the recent VFP/NEON instructions.
Fix two issues I found while writing these tests.

llvm-svn: 189341
2013-08-27 11:24:16 +00:00
Tim Northover 449d390f40 ARM: add natural patterns for vaddhl and vsubhl.
These instructions aren't particularly complicated and it's well worth having
patterns for some reasonably useful LLVM IR that will match them. Soon we
should be able to switch Clang over to producing this natural version.

llvm-svn: 189335
2013-08-27 10:31:36 +00:00
Charles Davis 1827bd8a6c Revert "Fix the build broken by r189315." and "Move everything depending on Object/MachOFormat.h over to Support/MachO.h."
This reverts commits r189319 and r189315. r189315 broke some tests on what I
believe are big-endian platforms.

llvm-svn: 189321
2013-08-27 05:38:30 +00:00
Charles Davis 0c6f71b40d Move everything depending on Object/MachOFormat.h over to Support/MachO.h.
llvm-svn: 189315
2013-08-27 05:00:43 +00:00
Jim Grosbach 667b147dba ARM: Constrain regclass for TSTri instruction.
Get the register class right for the TST instruction. This keeps the
machine verifier happy, enabling us to turn it on for another test.

rdar://12594152

llvm-svn: 189274
2013-08-26 20:22:05 +00:00
Jim Grosbach 5f71aab12e ARM: FastISel verifier error cleanup.
Constant pool and global value reference instructions need more
restricted register classes than plain GPR.

rdar://12594152

llvm-svn: 189270
2013-08-26 20:07:29 +00:00
Jim Grosbach 08aa534239 ARM: Fix ELF global base reg intialization.
The create machine code wasn't properly in SSA, which the machine verifier
properly complains about. Now that fast-isel is closer to verifier clean,
errors like this show up more clearly.

Additionally, the Thumb pseudo tPICADD was used for both ARM and Thumb
mode functions, which is obviously wrong. Fix that along the way.

Test case is part of the following commit which will finish making an
additional fast-isel test verifier clean an enable it for the
regression test suite. This commit is separate since its not just
a verifier cleanup, but an actual correctness issue.

rdar://12594152 (for the fast-isel verifier aspects)

llvm-svn: 189269
2013-08-26 20:07:25 +00:00
Joey Gouly c7cda1c59e [ARM] Fix another ARM FastISel -verify-machineinstrs issue.
llvm-svn: 189109
2013-08-23 15:20:56 +00:00
Joey Gouly e3dd684aad [ARMv8] Add CodeGen for VMAXNM/VMINNM.
llvm-svn: 189103
2013-08-23 12:01:13 +00:00
Tim Northover 1f1b2756a4 ARM: make sure ARM-mode pseudo-inst requires IsARM
I'd forgotten that "Requires" blocks override rather than add to the
constraints, so my pseudo-instruction was being selected in Thumb mode leading
to nonsense instructions.

rdar://problem/14817358

llvm-svn: 189096
2013-08-23 10:16:39 +00:00
Joey Gouly 881eab53be [ARMv8] Add CodeGen support for VSEL.
This uses the ARMcmov pattern that Tim cleaned up in r188995.

Thanks to Simon Tatham for his floating point help!

llvm-svn: 189024
2013-08-22 15:29:11 +00:00
Mihai Popa 5500c0ff89 Fix ARM vcvt encoding when the number of fractional bits is zero.
The instruction to convert between floating point and fixed point representations
takes an immediate operand for the number of fractional bits of the fixed point
value. ARMARM specifies that when that number of bits is zero, the assembler
should encode floating point/integer conversion instructions. 

This patch adds the necessary instruction aliases to achieve this behaviour.

llvm-svn: 189009
2013-08-22 13:16:07 +00:00
Joey Gouly e1de9e9c33 [ARM] Constrain some register classes in EmitAtomicBinary64 so that
we pass these tests with -verify-machineinstrs.

llvm-svn: 189006
2013-08-22 12:19:24 +00:00
Logan Chien 2361f51e82 Fix ARM FastISel PIC function call.
The function call to external function should come with PLT relocation
type if the PIC relocation model is used.

llvm-svn: 189002
2013-08-22 12:08:04 +00:00
Tim Northover 421804420d ARM: use TableGen patterns to select CMOV operations.
Back in the mists of time (2008), it seems TableGen couldn't handle the
patterns necessary to match ARM's CMOV node that we convert select operations
to, so we wrote a lot of fairly hairy C++ to do it for us.

TableGen can deal with it now: there were a few minor differences to CodeGen
(see tests), but nothing obviously worse that I could see, so we should
probably address anything that *does* come up in a localised manner.

llvm-svn: 188995
2013-08-22 09:57:11 +00:00
Tim Northover 2ddeeed096 ARM: respect tied 64-bit inlineasm operands when printing
The code for 'Q' and 'R' operand modifiers needs to look through tied
operands to discover the register class.

llvm-svn: 188990
2013-08-22 06:51:04 +00:00
Jim Grosbach 6a7a727174 ARM: R9 is not safe to use for tcGPR.
Indirect tail-calls shouldn't use R9 for the branch destination, as
it's not reliably a call-clobbered register.

rdar://14793425

llvm-svn: 188967
2013-08-22 00:14:24 +00:00
Mihai Popa ae1112bae5 Make "mov" work for all Thumb2 MOV encodings
According to the ARM specification, "mov" is a valid mnemonic for all Thumb2 MOV encodings.
To achieve this, the patch adds one instruction alias with a special range condition to avoid collision with the Thumb1 MOV.

llvm-svn: 188901
2013-08-21 13:14:58 +00:00
Jim Grosbach 71a78f962b ARM: Fix fast-isel copy/paste-o.
Update testcase to be more careful about checking register
values. While regexes are general goodness for these sorts of
testcases, in this example, the registers are constrained by
the calling convention, so we can and should check their
explicit values.

rdar://14779513

llvm-svn: 188819
2013-08-20 19:12:42 +00:00
Tim Northover f79c3a5aef ARM: implement some simple f64 materializations.
Previously we used a const-pool load for virtually all 64-bit floating values.
Actually, we can get quite a few common values (including 0.0, 1.0) via "vmov"
instructions of one stripe or another.

llvm-svn: 188773
2013-08-20 08:57:11 +00:00
Mihai Popa 4a9df8a768 Thumb2 add immediate alias for SP
The Thumb2 add immediate is in fact defined for SP. The manual is misleading as it points to a different section for add immediate with SP, however the encoding is the same as for add immediate with register only with the SP operand hard coded. As such add immediate with SP and add immediate with register can safely be treated as the same instruction.

All the patch does is adjust a register constraint on an instruction alias.

llvm-svn: 188676
2013-08-19 15:02:25 +00:00
Tim Northover 55349a29c6 ARM: make sure we keep inline asm operands tied.
When patching inlineasm nodes to use GPRPair for 64-bit values, we
were dropping the information that two operands were tied, which
effectively broke the live-interval of vregs affected.

llvm-svn: 188643
2013-08-18 18:06:03 +00:00
Jim Grosbach d786679049 ARM: Properly constrain comparison fastisel register classes.
Ongoing 'make the verifier happy' improvements to ARM fast-isel.

rdar://12594152

llvm-svn: 188595
2013-08-16 23:37:40 +00:00
Jim Grosbach 3fa749102a ARM: Fast-isel register class constrain for extends.
Properly constrain the operand register class for instructions used
in [sz]ext expansion. Update more tests to use the verifier now that
we're getting the register classes correct.

rdar://12594152

llvm-svn: 188594
2013-08-16 23:37:36 +00:00
Jim Grosbach 06c2a68125 ARM: Fix more fast-isel verifier failures.
Teach the generic instruction selection helper functions to constrain
the register classes of their input operands. For non-physical register
references, the generic code needs to be careful not to mess that up
when replacing references to result registers. As the comment indicates
for MachineRegisterInfo::replaceRegWith(), it's important to call
constrainRegClass() first.

rdar://12594152

llvm-svn: 188593
2013-08-16 23:37:31 +00:00
Jim Grosbach d69f3ed947 ARM: Clean up fast-isel machine verifier errors.
Lots of machine verifier errors result from using a plain GPR regclass
for incoming argument copies. A more restrictive rGPR class is more
appropriate since it more accurately represents what's happening, plus
it lines up better with isel later on so the verifier is happier.
Reduces the number of ARM fast-isel tests not running with the verifier
enabled by over half.

rdar://12594152

llvm-svn: 188592
2013-08-16 23:37:23 +00:00
Benjamin Kramer 309206667d When initializing the PIC global base register on ARM/ELF add pc to fix the address.
This unbreaks PIC with fast isel on ELF targets (PR16717). The output matches
what GCC and SDag do for PIC but may not cover all of the many flavors of PIC
that exist.

llvm-svn: 188551
2013-08-16 12:52:08 +00:00
Mihai Popa 46c1bcb4e9 Add support for Thumb2 literal loads with negative zero offset
Thumb2 literal loads use an offset encoding which allows for 
negative zero. This fixes parsing and encoding so that #-0 
is correctly processed. The parser represents #-0 as INT32_MIN.

llvm-svn: 188549
2013-08-16 12:03:00 +00:00
Mihai Popa cf276b2c88 Fix Thumb2 aliasing complementary instructions taking modified immediates
There are many Thumb instructions which take 12-bit immediates encoded in a special
8-byte value + 4-byte rotator form. Not all numbers are represented, and it's legal
to transform an assembly instruction to be able to encode the immediate.

For example: AND and BIC are complementary instructions; one can switch the AND
to a BIC as long as the immediate is complemented. 

The intent is to switch one instruction into its complementary one when the immediate
cannot be encoded in the form requested in the original assembly and when the 
complementary immediate is encodable.

The patch addresses two issues:
1. definition of t2SOImmNot immediate - it has to check that the orignal value is
not encoded naturally
2. t2AND and t2BIC instruction aliases which should use the Thumb2 SOImm operand 
rather than the ARM one.

llvm-svn: 188548
2013-08-16 11:55:44 +00:00
Renato Golin ca570633c5 make arm-use-movt available for all ARM
Before this patch this flag is IOS specific, but is also
useful for bare project like bootloaders / kernels etc,
since movw / movt prevents simple relocation. Therefore
make this flag more commonly available.

note: this patch depends on a similiar rename in clang

Patch by Jeroen Hofstee.

llvm-svn: 188487
2013-08-15 20:54:38 +00:00
Renato Golin 0a41d9ae7f make arm-reserve-r9 available for all ARM
r9 is defined as a platform-specific register in the ARM EABI.
It can be reserved for a special purpose or be used as a general
purpose register. Add support for reserving r9 for all ARM, while
leaving the IOS usage unchanged.

Patch by Jeroen Hofstee.

llvm-svn: 188485
2013-08-15 20:45:13 +00:00
Mihai Popa d79f00ba68 This fixes three issues related to Thumb literal loads:
1. The offset range for Thumb1 PC relative loads is [0..1020] and not [-1024..1020]
2. Thumb2 PC relative loads may define the PC, so the restriction placed on target register is removed
3. Removes unneeded alias between "ldr.n" and t1LDRpci. ".n" is actually stripped by both tablegen
and the ASM parser, so this alias rule really does nothing

llvm-svn: 188466
2013-08-15 15:43:06 +00:00
Craig Topper 5671010cbb Replace getValueType().getSimpleVT() with getSimpleValueType(). Also remove one weird cast from MVT->EVT just to call getSimpleVT().
llvm-svn: 188441
2013-08-15 02:33:50 +00:00
Renato Golin b184cd99ba Let t2LDRBi8 and t2LDRBi12 have same Base Pointer
When determining if two different loads are from the same base address,
this patch allows one load to use a t2LDRi8 address mode and another to
use a t2LDRi12 address mode. The current implementation is very
conservative and this allows the case of differing Thumb2 byte loads to
be considered. Allowing these differing modes instead of forcing the exact
same opcode is useful for situations where one opcodes loads from a base
address+1 and a second opcode loads for a base address-1.

Patch by Daniel Stewart.

llvm-svn: 188385
2013-08-14 16:35:29 +00:00