Commit Graph

129751 Commits

Author SHA1 Message Date
Ulrich Weigand 79391ee0f2 [SystemZ] Fix build break from r265689
Fix build error seen on some build bots due to:
error: default label in switch which covers all enumeration values

llvm-svn: 265693
2016-04-07 16:33:25 +00:00
Kevin B. Smith 3802c4af59 [X86]: Fix for PR27251.
Differential Revision: http://reviews.llvm.org/D18850

llvm-svn: 265690
2016-04-07 16:15:34 +00:00
Ulrich Weigand 2eb027d21f [SystemZ] Implement conditional returns
Return is now considered a predicable instruction, and is converted
to a newly-added CondReturn (which maps to BCR to %r14) instruction by
the if conversion pass.

Also, fused compare-and-branch transform knows about conditional
returns, emitting the proper fused instructions for them.

This transform triggers on a *lot* of tests, hence the huge diffstat.
The changes are mostly jX to br %r14 -> bXr %r14.

Author: koriakin

Differential Revision: http://reviews.llvm.org/D17339

llvm-svn: 265689
2016-04-07 16:11:44 +00:00
Davide Italiano 14e351a553 [IR/Verifier] Merge two ifs into one. NFC.
llvm-svn: 265688
2016-04-07 15:55:28 +00:00
Ulrich Weigand fc23907673 [GVN] Address review comments for D18662
As suggested by Chandler in his review comments for D18662, this
follow-on patch renames some variables in GetLoadValueForLoad and
CoerceAvailableValueToLoadType to hopefully make it more obvious
which variables hold value sizes and which hold load/store sizes.

No functional change intended.

llvm-svn: 265687
2016-04-07 15:55:11 +00:00
JF Bastien e1951092ff NFC: disallow comparison of AtomicOrdering
Follow-up to D18775 and related clang change. AtomicOrdering is a lattice, 'stronger' is the right thing to do, direct comparison is fraught with peril.

llvm-svn: 265685
2016-04-07 15:50:05 +00:00
Ulrich Weigand 6e6966460a [GVN] Fix handling of sub-byte types in big-endian mode
When GVN wants to re-interpret an already available value in a smaller
type, it needs to right-shift the value on big-endian systems to ensure
the correct bytes are accessed.  The shift value is the difference of
the sizes of the two types.

This is correct as long as both types occupy multiples of full bytes.
However, when one of them is a sub-byte type like i1, this no longer
holds true: we still need to shift, but only to access the correct
*byte*.  Accessing bits within the byte requires no shift in either
endianness; e.g. an i1 resides in the least-significant bit of its
containing byte on both big- and little-endian systems.

Therefore, the appropriate shift value to be used is the difference of
the *storage* sizes of the two types.  This is already handled correctly
in one place where such a shift takes place (GetStoreValueForLoad), but
is incorrect in two other places: GetLoadValueForLoad and
CoerceAvailableValueToLoadType.

This patch changes both places to use the storage size as well.

Differential Revision: http://reviews.llvm.org/D18662

llvm-svn: 265684
2016-04-07 15:45:02 +00:00
Ehsan Amiri 4701a91e59 [PPC] Enable transformations in PPCPassConfig::addIRPasses at O2
http://reviews.llvm.org/D18562

A large number of testcases has been modified so they pass after this test.
One testcase is deleted, because I realized even after undoing the original
change that was committed with this testcase, the testcase still passes. So
I removed it. The change to one other testcase (test/CodeGen/PowerPC/pr25802.ll)
is an arbitrary change to keep it passing. Given the original intention of the
testcase, and the fact that fixing it will require some time to change the testcase,
we concluded that this quick change will be enough.

llvm-svn: 265683
2016-04-07 15:30:55 +00:00
Tom Stellard d37630e461 AMDGPU/SI: Add MachineBasicBlock parameter to SIInstrInfo::insertWaitStates
Summary: This makes it possible to insert nops at the end of blocks.

Reviewers: arsenm

Subscribers: arsenm, llvm-commits

Differential Revision: http://reviews.llvm.org/D18549

llvm-svn: 265678
2016-04-07 14:47:07 +00:00
Valery Pykhtin e23b6deb01 [AMDGPU] fix readlane/readfirstlane src vgpr operand type.
For VGPR_32 operand disassembler expects a VGPR register encoded as 0..255 (enum8 src operand).
readfirstlane/readline actually has enum9 operand and this change fixes VGPR_32 to VS_32 (enum9 encoding).

Differential Revision: http://reviews.llvm.org/D18696

llvm-svn: 265670
2016-04-07 13:41:51 +00:00
Dmitry Polukhin af16b958c0 Fix test/Assembler/ifunc-asm.ll test on hexagon-elf bots
Temporary disable llc test, it seems that such test should be in some
other directory.

llvm-svn: 265669
2016-04-07 13:18:43 +00:00
Dmitry Polukhin a1feff7024 [GCC] Attribute ifunc support in llvm
This patch add support for GCC attribute((ifunc("resolver"))) for
targets that use ELF as object file format. In general ifunc is a
special kind of function alias with type @gnu_indirect_function. Patch
for Clang http://reviews.llvm.org/D15524

Differential Revision: http://reviews.llvm.org/D15525

llvm-svn: 265667
2016-04-07 12:32:19 +00:00
NAKAMURA Takumi e546211492 InlineSpiller.cpp: Escap \@ in r265547. [-Wdocumentation]
llvm-svn: 265657
2016-04-07 11:30:06 +00:00
Benjamin Kramer 4fb78518f1 Make helper functions static. NFC.
llvm-svn: 265653
2016-04-07 10:10:09 +00:00
Valery Pykhtin 8e79f5be0c fix r265645: target dependent printf formatting flags.
llvm-svn: 265649
2016-04-07 08:38:20 +00:00
Jeroen Ketema a689721003 [CMake] Check for sys/types.h in config-ix.cmake
`sys/types.h` has a related define in `config.h.cmake`, but was never
checked for in CMake. Sync this.

Differential Revision: http://reviews.llvm.org/D18825

llvm-svn: 265648
2016-04-07 08:36:13 +00:00
Simon Pilgrim d54bae6525 [X86][SSE] Add support for VZEXT constant folding
llvm-svn: 265646
2016-04-07 07:52:45 +00:00
Valery Pykhtin de04805e9f [AMDGPU] llvm-objdump: Minimal HSA Code Object disassembler support.
Reenable reverted r265550 with endianness issue fixed. Variables of
endian-aware types such as ulittle32_t should be explicitly casted
to their natural equivalent types before passing it as vararg to
printf like functions (format in my case). Added lit config file
depending on AMDGPU target as the testcase uses assembler.

Differential revision: http://reviews.llvm.org/D16998

llvm-svn: 265645
2016-04-07 07:24:01 +00:00
Amaury Sechet 33c161c02f [BlockPlacement] Remove an unnecessary continue
NFC.

llvm-svn: 265643
2016-04-07 06:35:00 +00:00
Amaury Sechet 9ee4ddd710 [MBP] Remove an unused function parameter
NFC.

llvm-svn: 265642
2016-04-07 06:34:47 +00:00
Amaury Sechet 4949131065 Do some refactoring in the LLVM C API echo test to remove duplication. NFC
llvm-svn: 265641
2016-04-07 05:56:20 +00:00
Wei Mi 979e9756ec Fix the sanitizer bootstrap error in r265547.
The iterators of SmallPtrSet SpillsInSubTreeMap[Child].first may be
invalidated when SpillsInSubTreeMap grows. Rearrange the code to
ensure the grow of SpillsInSubTreeMap only happens before getting
the iterators of the SmallPtrSet.

llvm-svn: 265639
2016-04-07 05:27:17 +00:00
Amaury Sechet 41474a52e7 Revert "[BlockPlacement] Remove an unnecessary continue" and "[MBP] Remove an unused function parameter"
llvm-svn: 265638
2016-04-07 04:28:40 +00:00
Duncan P. N. Exon Smith 45601e867d Revert "ValueMapper: Make LocalAsMetadata match function-local Values"
This reverts commit r265631, since it caused bot failures:
http://lab.llvm.org:8011/builders/clang-ppc64be-linux/builds/3256
http://lab.llvm.org:8011/builders/clang-cmake-aarch64-42vma/builds/7272

Looks like something is depending on the old behaviour.  I'll try to
track it down and recommit.

llvm-svn: 265637
2016-04-07 02:10:50 +00:00
Ahmed Bougacha 1cf67fb9cb [X86] Reuse EFLAGS and form LOCKed ops when only user is SETCC.
Re-apply r265450 which caused PR27245 and was reverted in r265559
because of a wrong generalization: the fetch_and_add->add_and_fetch
combine only works in specific, but pretty common, cases:
  (icmp slt x, 0) -> (icmp sle (add x, 1), 0)
  (icmp sge x, 0) -> (icmp sgt (add x, 1), 0)
  (icmp sle x, 0) -> (icmp slt (sub x, 1), 0)
  (icmp sgt x, 0) -> (icmp sge (sub x, 1), 0)

Original Message:

We only generate LOCKed versions of add/sub when the result is unused.
It often happens that the result is used, but only by a comparison. We
can optimize those out by reusing EFLAGS, which lets us use the proper
instructions, instead of having to fallback to LXADD.

Instead of doing this as an MI peephole (as we do for the other
non-LOCKed (really, non-MR) forms), do it in ISel. It becomes quite
tricky later.

This also makes it eventually possible to stop expanding and/or/xor
if the only user is an icmp (also see D18141).

This uses the LOCK ISD opcodes added by r262244.

Differential Revision: http://reviews.llvm.org/D17633

llvm-svn: 265636
2016-04-07 02:07:10 +00:00
Ahmed Bougacha 70bde5445b [X86] Refresh and tweak EFLAGS reuse tests. NFC.
The non-1 and EQ/NE tests were misguided.

llvm-svn: 265635
2016-04-07 02:06:53 +00:00
Duncan P. N. Exon Smith fdccad925c ValueMapper: Allow RF_IgnoreMissingLocals and RF_NullMapMissingGlobalValues
Remove the assertion that disallowed the combination, since
RF_IgnoreMissingLocals should have no effect on globals.  As it happens,
RF_NullMapMissingGlobalValues asserted in MapValue(Constant*,...), so I
also changed a cast to a cast_or_null to get my test passing.

llvm-svn: 265633
2016-04-07 01:22:45 +00:00
Duncan P. N. Exon Smith c1e4070708 ValueMapper: Make LocalAsMetadata match function-local Values
Start treating LocalAsMetadata similarly to function-local members of
the Value hierarchy in MapValue and MapMetadata.

  - Don't memoize them.
  - Return nullptr if they are missing.

This also cleans up ConstantAsMetadata to stop listening to the
RF_IgnoreMissingLocals flag.

llvm-svn: 265631
2016-04-07 01:08:39 +00:00
Quentin Colombet b073c12912 [AArch64] Teach RegisterBankInfo about the CC register bank.
We need to cover each register class with a register bank.

llvm-svn: 265629
2016-04-07 00:39:29 +00:00
Duncan P. N. Exon Smith da68cbc4ad IR: RF_IgnoreMissingValues => RF_IgnoreMissingLocals, NFC
Clarify what this RemapFlag actually means.

  - Change the flag name to match its intended behaviour.
  - Clearly document that it's not supposed to affect globals.
  - Add a host of FIXMEs to indicate how to fix the behaviour to match
    the intent of the flag.

RF_IgnoreMissingLocals should only affect the behaviour of
RemapInstruction for function-local operands; namely, for operands of
type Argument, Instruction, and BasicBlock.  Currently, it is *only*
passed into RemapInstruction calls (and the transitive MapValue calls
that it makes).

When I split Metadata from Value I didn't understand the flag, and I
used it in a bunch of places for "global" metadata.

This commit doesn't have any functionality change, but prepares to
cleanup MapMetadata and MapValue.

llvm-svn: 265628
2016-04-07 00:26:43 +00:00
Quentin Colombet cbc353a422 [AArch64] Teach RegisterBankInfo about the mapping of register classes
on register banks.

llvm-svn: 265626
2016-04-07 00:14:30 +00:00
Michael Zolotukhin 56ad4048ae Follow-up for r265605: don't mutate vector we're iterating.
llvm-svn: 265625
2016-04-07 00:09:42 +00:00
Quentin Colombet 4359784c1b [RegisterBankInfo] Implement a target independent version of
getInstrMapping.

This implementation requires that the target implemented
getRegBankFromRegClass.
Indeed, the implementation uses the register classes for the encoding
constraints for the instructions to deduce the mapping of a value.

llvm-svn: 265624
2016-04-07 00:07:50 +00:00
Hans Wennborg ab16be799c Re-commit r265039 "[X86] Merge adjacent stack adjustments in eliminateCallFramePseudoInstr (PR27140)"
Third time's the charm? The previous attempt (r265345) caused ASan test
failures on X86, as broken CFI caused stack traces to not work.

This version of the patch makes sure not to merge with stack adjustments
that have CFI, and to not add merged instructions' offests to the CFI
about to be generated.

This is already covered by the lit tests; I just got the expectations
wrong previously.

llvm-svn: 265623
2016-04-07 00:05:49 +00:00
Quentin Colombet 8c0d66bc54 [RegisterBankInfo] Add an helper function to get the size of a register.
The previous method to get the size was too simple and could fail for
physical registers.

llvm-svn: 265620
2016-04-06 23:59:53 +00:00
Justin Lebar 9e479e4763 Fix a race condition in support library ThreadPool.
By running TSAN on the ThreadPool unit tests it was discovered that the
threads in the pool can pop tasks off the queue at the same time the
"wait" routine is trying to check if the task queue is empty. This patch
fixes this problem by checking for active threads in the waiter before
checking whether the queue is empty.

Patch by Jason Henline.

Differential Revision: http://reviews.llvm.org/D18811

Reviewers: joker.eph, jlebar
llvm-svn: 265618
2016-04-06 23:46:40 +00:00
Mike Aizatsky 70ea45306a [sancov] enabling coverage edge pruning by default.
Differential Revision: http://reviews.llvm.org/D18844

llvm-svn: 265615
2016-04-06 23:24:37 +00:00
Duncan P. N. Exon Smith 669a33f0ce ValueMapper: clang-format ValueMapper.h, NFC
Also remove duplicated identifiers from comments.

llvm-svn: 265611
2016-04-06 22:37:30 +00:00
Wei Mi 284fa0bd71 Fix the compare-clang diff error introduced by r265547.
Use MapVector instead of DenseMap for MergeableSpillsMap so it will be
iterated in determined order.

llvm-svn: 265610
2016-04-06 22:31:17 +00:00
Peter Zotov 3e4561cec5 [llvm-c] Add LLVMGetValueKind.
Patch by Nicole Mazzuca <npmazzuca@gmail.com>.

Differential Revision: http://reviews.llvm.org/D18729

llvm-svn: 265608
2016-04-06 22:21:29 +00:00
Kevin Enderby 3fcdf6ae2a Thread Expected<...> up from createMachOObjectFile() to allow llvm-objdump to produce a real error message
Produce the first specific error message for a malformed Mach-O file describing
the problem instead of the generic message for object_error::parse_failed of
"Invalid data was encountered while parsing the file”.  Many more good error
messages will follow after this first one.

This is built on Lang Hames’ great work of adding the ’Error' class for
structured error handling and threading Error through MachOObjectFile
construction.  And making createMachOObjectFile return Expected<...> .

So to to get the error to the llvm-obdump tool, I changed the stack of
these methods to also return Expected<...> :

  object::ObjectFile::createObjectFile()
  object::SymbolicFile::createSymbolicFile()
  object::createBinary()

Then finally in ParseInputMachO() in MachODump.cpp the error can
be reported and the specific error message can be printed in llvm-objdump
and can be seen in the existing test case for the existing malformed binary
but with the updated error message.

Converting these interfaces to Expected<> from ErrorOr<> does involve
touching a number of places. To contain the changes for now use of
errorToErrorCode() and errorOrToExpected() are used where the callers
are yet to be converted.

Also there some were bugs in the existing code that did not deal with the
old ErrorOr<> return values.  So now with Expected<> since they must be
checked and the error handled, I added a TODO and a comment:
“// TODO: Actually report errors helpfully” and a call something like
consumeError(ObjOrErr.takeError()) so the buggy code will not crash
since needed to deal with the Error.

Note there is one fix also needed to lld/COFF/InputFiles.cpp that goes along
with this that I will commit right after this.  So expect lld not to built
after this commit and before the next one.

llvm-svn: 265606
2016-04-06 22:14:09 +00:00
Michael Zolotukhin 97567e141e [LoopUnroll] Fix the way we update DT after complete unrolling.
Updating dominators for exit-blocks of the unrolled loops is not enough,
as shown in PR27157. The proper way is to update dominators for all
dominance-children of original loop blocks.

llvm-svn: 265605
2016-04-06 21:47:12 +00:00
Quentin Colombet c916204a81 [RegisterBankInfo] Add methods to get the possible mapping of an instruction on a register bank.
This will be used by the register bank select pass to assign register banks
for generic virtual registers.

This was originally committed as r265573 but broke at least one windows bot.
The problem with the windows bot was that it was using a copy constructor for
the InstructionMappings class and could not synthesize it. Actually, the fact
that this class is not copy constructable is expected and the compiler should
use the move assignment constructor. Marking the problematic assignment
explicitly as using the move constructor has its own problems.

Indeed, with recent clang we get a warning that we may prevent the elision of
the copy by the compiler. A proper fix for both compilers would be to change the
API of getPossibleInstrMapping to take a InstructionMappings as input/output
parameter. This does not feel natural and since GISel is not used on windows
yet, I chose to workaround the problem by not compiling the problematic code on
windows.

llvm-svn: 265604
2016-04-06 21:37:22 +00:00
JF Bastien 800f87a871 NFC: make AtomicOrdering an enum class
Summary:
In the context of http://wg21.link/lwg2445 C++ uses the concept of
'stronger' ordering but doesn't define it properly. This should be fixed
in C++17 barring a small question that's still open.

The code currently plays fast and loose with the AtomicOrdering
enum. Using an enum class is one step towards tightening things. I later
also want to tighten related enums, such as clang's
AtomicOrderingKind (which should be shared with LLVM as a 'C++ ABI'
enum).

This change touches a few lines of code which can be improved later, I'd
like to keep it as NFC for now as it's already quite complex. I have
related changes for clang.

As a follow-up I'll add:
  bool operator<(AtomicOrdering, AtomicOrdering) = delete;
  bool operator>(AtomicOrdering, AtomicOrdering) = delete;
  bool operator<=(AtomicOrdering, AtomicOrdering) = delete;
  bool operator>=(AtomicOrdering, AtomicOrdering) = delete;
This is separate so that clang and LLVM changes don't need to be in sync.

Reviewers: jyknight, reames

Subscribers: jyknight, llvm-commits

Differential Revision: http://reviews.llvm.org/D18775

llvm-svn: 265602
2016-04-06 21:19:33 +00:00
Haicheng Wu 1951cf24a7 [MBP] Remove an unused function parameter
NFC.

llvm-svn: 265596
2016-04-06 20:38:20 +00:00
Ehsan Amiri 322eca3849 [PPC] Use VSX/FP Facility integer load when an integer load's only users are conversion to FP
http://reviews.llvm.org/D18405

When the integer value loaded is never used directly as integer we should use VSX 
or Floating Point Facility integer loads and avoid extra direct move

llvm-svn: 265593
2016-04-06 20:12:29 +00:00
Sanjay Patel 6cc488004d regenerate checks
llvm-svn: 265591
2016-04-06 19:58:06 +00:00
James Y Knight 037b9894bd Put quotes around #error string.
GCC reports "missing terminating ' character", even when it's being
skipped by preprocessing.

llvm-svn: 265590
2016-04-06 19:52:32 +00:00
Nicolai Haehnle df3a20cd80 AMDGPU: Add a shader calling convention
This makes it possible to distinguish between mesa shaders
and other kernels even in the presence of compute shaders.

Patch By: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

Differential Revision: http://reviews.llvm.org/D18559

llvm-svn: 265589
2016-04-06 19:40:20 +00:00
Quentin Colombet fb000583aa Revert "[RegisterBankInfo] Add methods to get the possible mapping of an
instruction on a register bank. This will be used by the register bank select
pass to assign register banks for generic virtual registers." and the follow-on
commits while I find out a way to fix the win7 bot:
http://lab.llvm.org:8011/builders/sanitizer-windows/builds/19882

This reverts commit r265578, r265581, r265584, and r265585.

llvm-svn: 265587
2016-04-06 19:04:58 +00:00
Davide Italiano 5f1c87bf07 [IRVerifier] Don't crash on invalid DIFile inside DISubprogram.
r265515, this time with the correct fix. file inside DISubprogram is not
mandatory.

llvm-svn: 265586
2016-04-06 18:46:39 +00:00
Quentin Colombet 6ac88cc1ec [RegisterBankInfo] Get rid of the assert in the constructor of InstructionMapping.
The default constructor now uses the regular constructor and the assert
is not valid anymore.

llvm-svn: 265585
2016-04-06 18:43:46 +00:00
Quentin Colombet 6bdc41a33b [RegisterBankInfo] Call the other constructor of InstructionMapping from the
default constructor, instead of relying on the default constructor of
unique_ptr.

Second attempt at fixing the windows bot.

llvm-svn: 265584
2016-04-06 18:37:44 +00:00
Evgeniy Stepanov 268826a287 [gold] Save bitcode for module partitions (save-temps + split codegen).
llvm-svn: 265583
2016-04-06 18:32:13 +00:00
Quentin Colombet df4aee09f8 [RegisterBankInfo] Provide a default constructor for InstructionMapping
helper class.

The default constructor creates invalid (isValid() == false) instances
and may be used to communicate that a mapping was not found.

llvm-svn: 265581
2016-04-06 18:24:34 +00:00
Davide Italiano 18c968688e [IRVerifier] Prefer dyn_cast<> over isa<> + cast<>.
Thanks to Rafael for the suggestion!

llvm-svn: 265579
2016-04-06 18:13:44 +00:00
Quentin Colombet bb756dbf39 [RegisterBankInfo] Add an helper function to get the size of a register.
The previous method to get the size was too simple and could fail for
physical registers.

llvm-svn: 265578
2016-04-06 18:04:35 +00:00
Duncan P. N. Exon Smith ef06d445e0 IR: Use DenseSet instead of DenseMap for ConstantUniqueMap; NFC
Use a DenseSet instead of a DenseMap for constants in LLVMContextImpl.
Last time I looked at this was some time before r223588, when
DenseSet<V> had no advantage over DenseMap<V,char>.  After r223588,
there's a 50% memory savings.

This is all mechanical.  There were little bits of missing API from
DenseSet so I added the trivial implementations:

  - iterator::operator++(int)
  - template <class LookupKeyT> insert_as(ValueTy, LookupKeyT)

There should be no functionality change, just reduced memory consumption
(this wasn't on a profile or anything; just a cleanup I stumbled on).

llvm-svn: 265577
2016-04-06 17:56:08 +00:00
Duncan P. N. Exon Smith f3d08ef59a IR: Stop explicitly clearing the MDStringCache
The MDStringCache doesn't need to be explicitly cleared before
destruction.  The destructor handles it at least as efficiently.

llvm-svn: 265576
2016-04-06 17:56:05 +00:00
Quentin Colombet 615aca1a25 [RegisterBankInfo] Add a method to get the mapping RegClass -> RegBank.
This should be TableGen'ed at some point.

llvm-svn: 265574
2016-04-06 17:51:41 +00:00
Quentin Colombet 9af77135e5 [RegisterBankInfo] Add methods to get the possible mapping of an instruction on a register bank.
This will be used by the register bank select pass to assign register banks
for generic virtual registers.

llvm-svn: 265573
2016-04-06 17:45:40 +00:00
Saleem Abdulrasool 8e1524e225 vim: add missing keyword
`source_filename` was introduced as a keyword in SVN r264884, but the syntax
file was not updated.

llvm-svn: 265572
2016-04-06 17:42:16 +00:00
Quentin Colombet 4f03c0b806 [AArch64] Change the CMake to avoid to build GlobalISel related APIs
when GISel is not built.
The positive side effects are:
- We do not have to define dummy implementation
- We do not have to do weird gymnastic to avoid like issues (like
  missing constructor or vtable for the base classes)

llvm-svn: 265570
2016-04-06 17:38:12 +00:00
Quentin Colombet c17f744001 [AArch64] Teach the subtarget how to get to the RegisterBankInfo.
Rework the access to GlobalISel APIs to contain how much of
the APIs we need to access for the final executable to build when
GlobalISel is not built.

This prevents massive usage of ifdefs in various places. Now, all the
GlobalISel ifdefs will be happing only in AArch64TargetMachine.cpp.

llvm-svn: 265567
2016-04-06 17:26:03 +00:00
Quentin Colombet 4c85bdb701 [RegisterBankInfo] Make the destructor public... that may be useful!
llvm-svn: 265565
2016-04-06 17:09:34 +00:00
Quentin Colombet 4812c91f56 [RegisterBankInfo] Implement the verify method of the InstructionMapping helper class.
This checks that all the register operands get a proper mapping.

llvm-svn: 265563
2016-04-06 17:01:43 +00:00
Fiona Glaser 045afc4f66 Loop Unroll: add options and tweak to make Partial unrolling more useful
1. Add FullUnrollMaxCount option that works like MaxCount, but also limits
   the unroll count for fully unrolled loops. So if a loop has an iteration
   count over this, it won't fully unroll.
2. Add CLI options for MaxCount and the new option, so they can be tested
   (plus a test).
3. Make partial unrolling obey MaxCount.

An example use-case (the out of tree one this is originally designed for) is
a target’s TTI can analyze a loop and decide on a max unroll count separate
from the size threshold, e.g. based on register pressure, then constrain
LoopUnroll to not exceed that, regardless of the size of the unrolled loop.

llvm-svn: 265562
2016-04-06 16:57:25 +00:00
Quentin Colombet a1ca39d310 [MachineRegisterInfo] Document what is the expected metric for the size of generic registers
llvm-svn: 265561
2016-04-06 16:51:04 +00:00
Hans Wennborg 6849f8f15f Revert r265450 "[X86] Reuse EFLAGS and form LOCKed ops when only user is SETCC."
It caused ASan 32-bit tests to hang (PR27245).

llvm-svn: 265559
2016-04-06 16:44:38 +00:00
Fiona Glaser 16332ba861 LoopUnroll: only allow non-modulo Partial unrolling when Runtime=true
Patch by Evgeny Stupachenko <evstupac@gmail.com>.

llvm-svn: 265558
2016-04-06 16:43:45 +00:00
Quentin Colombet 3768f7005d [RegisterBankInfo] Implement the verify method for the ValueMapping helper class.
The method checks that the value is fully defined accross the different partial
mappings and that the partial mappings are compatible between each other.

llvm-svn: 265556
2016-04-06 16:40:23 +00:00
Quentin Colombet 2423fc419c [RegisterBankInfo] Add a verify method for the PartialMapping helper class.
This verifies that the PartialMapping can be accomadated into the related
register bank.

llvm-svn: 265555
2016-04-06 16:33:26 +00:00
Valery Pykhtin 1dcb91b4de Revert "[AMDGPU] llvm-objdump: Minimal HSA Code Object disassembler support."
This reverts commit r265550. There're problems with endianness on dumping instruction bytes. Need to find out how to use support::ulittle32_t type properly.

llvm-svn: 265554
2016-04-06 16:30:21 +00:00
Quentin Colombet 89c33caee3 [RegisterBankInfo] Add a couple of helper classes for the future cost model.
llvm-svn: 265553
2016-04-06 16:27:01 +00:00
Hans Wennborg a7e396b5ef Revert "Re-commit r265039 "[X86] Merge adjacent stack adjustments in eliminateCallFramePseudoInstr (PR27140)""
It seems to be causing ASan tests to crash, probably due to
miscompiling the run-time somehow.

llvm-svn: 265551
2016-04-06 16:10:20 +00:00
Valery Pykhtin bd90c60afb [AMDGPU] llvm-objdump: Minimal HSA Code Object disassembler support.
Differential revision: http://reviews.llvm.org/D16998

llvm-svn: 265550
2016-04-06 15:55:10 +00:00
Quentin Colombet d1d324b2ae [AArch64] Use the default constructor of RegisterBankInfo when GlobalISel is not built.
This will avoid link-time error as the defautl constructor of RegisterBankInfo is
the only one available when GlobalISel is not built.

llvm-svn: 265549
2016-04-06 15:53:13 +00:00
Quentin Colombet 911181882e [RegisterBankInfo] Inline the destructor to avoid link-time error when GlobalISel is not built.
llvm-svn: 265548
2016-04-06 15:47:17 +00:00
Wei Mi 18293bef4e Recommit r265309 after fixed an invalid memory reference bug happened
when DenseMap growed and moved memory. I verified it fixed the bootstrap
problem on x86_64-linux-gnu but I cannot verify whether it fixes
the bootstrap error on clang-ppc64be-linux. I will watch the build-bot
result closely.

Replace analyzeSiblingValues with new algorithm to fix its compile
time issue. The patch is to solve PR17409 and its duplicates.

analyzeSiblingValues is a N x N complexity algorithm where N is
the number of siblings generated by reg splitting. Although it
causes siginificant compile time issue when N is large, it is also
important for performance since it removes redundent spills and
enables rematerialization.

To solve the compile time issue, the patch removes analyzeSiblingValues
and replaces it with lower cost alternatives containing two parts. The
first part creates a new spill hoisting method in postOptimization of
register allocation. It does spill hoisting at once after all the spills
are generated instead of inside every instance of selectOrSplit. The
second part queries the define expr of the original register for
rematerializaiton and keep it always available during register allocation
even if it is already dead. It deletes those dead instructions only in
postOptimization. With the two parts in the patch, it can remove
analyzeSiblingValues without sacrificing performance.

Differential Revision: http://reviews.llvm.org/D15302

llvm-svn: 265547
2016-04-06 15:41:07 +00:00
Silviu Baranga a393baf1fd Revert r265535 until we know how we can fix the bots
llvm-svn: 265541
2016-04-06 14:06:32 +00:00
Sam Kolton ff90c60a78 [AMDGPU] AsmParser: disable DPP for unsupported instructions. New dpp tests. Fix v_nop_dpp.
Summary:
1. Disable DPP encoding for instructions that do not support it:
    - VOP1:
        - v_readfirstlane_b32
        - v_clrexcp
        - v_movreld_b32
        - v_movrels_b32
        - v_movrelsd_b32
    - VOP2:
        - v_madmk_f16/32
        - v_madak_f16/32
    - VOPC, VINTRP, VOP3
2. Fix DPP for v_nop
3. New DPP tests for VOP1 and VOP2 instructions

Reviewers: nhaustov, tstellarAMD, vpykhtin

Subscribers: tstellarAMD, arsenm

Differential Revision: http://reviews.llvm.org/D18552

llvm-svn: 265538
2016-04-06 13:29:59 +00:00
Chad Rosier 074ce836f0 Simplify logic. NFC.
llvm-svn: 265537
2016-04-06 13:27:13 +00:00
Silviu Baranga 72b4a4a330 [SCEV] Introduce a guarded backedge taken count and use it in LAA and LV
Summary:
When the backedge taken codition is computed from an icmp, SCEV can
deduce the backedge taken count only if one of the sides of the icmp
is an AddRecExpr. However, due to sign/zero extensions, we sometimes
end up with something that is not an AddRecExpr.

However, we can use SCEV predicates to produce a 'guarded' expression.
This change adds a method to SCEV to get this expression, and the
SCEV predicate associated with it.

In HowManyGreaterThans and HowManyLessThans we will now add a SCEV
predicate associated with the guarded backedge taken count when the
analyzed SCEV expression is not an AddRecExpr. Note that we only do
this as an alternative to returning a 'CouldNotCompute'.

We use new feature in Loop Access Analysis and LoopVectorize to analyze
and transform more loops.

Reviewers: anemet, mzolotukhin, hfinkel, sanjoy

Subscribers: flyingforyou, mcrosier, atrick, mssimpso, sanjoy, mzolotukhin, llvm-commits

Differential Revision: http://reviews.llvm.org/D17201

llvm-svn: 265535
2016-04-06 13:18:26 +00:00
Evgeny Astigeevich 9c24ebfa6d [AArch64][CodeGen] NFC refactor AArch64InstrInfo::optimizeCompareInstr to prepare it for fixing a bug in it
AArch64InstrInfo::optimizeCompareInstr has a bug which causes generation of incorrect code (PR#27158).
The patch refactors the function to simplify reviewing the fix of the bug.

1. Function name ‘modifiesConditionCode’ is changed to ‘areCFlagsAccessedBetweenInstrs’
   to reflect that the function can check modifying accesses, reading accesses or both.
2. Function ‘AArch64InstrInfo::optimizeCompareInstr’
   - Documented the function
   - Cmp_NZCV is DeadNZCVIdx to reflect that it is an operand index of dead NZCV
   - The code for the case of substituting CmpInstr is put into separate
     functions the main of them is ‘substituteCmpInstr’.

Differential Revision: http://reviews.llvm.org/D18609

llvm-svn: 265531
2016-04-06 11:39:00 +00:00
Chuang-Yu Cheng 6e1408a891 [ppc64] Temporary disable sibling call optimization on ppc64 due to breaking test case
r265506 breaks print-stack-trace.cc test case of compiler-rt in bootstrap
test.

http://lab.llvm.org:8011/builders/clang-ppc64be-linux-multistage/builds/1708

llvm-svn: 265528
2016-04-06 10:48:36 +00:00
David Majnemer 12fd50410d [SLPVectorizer] Vectorizing the libm sqrt to llvm's sqrt intrinsic requires nnan
To quote the langref "Unlike sqrt in libm, however, llvm.sqrt has
undefined behavior for negative numbers other than -0.0 (which allows
for better optimization, because there is no need to worry about errno
being set). llvm.sqrt(-0.0) is defined to return -0.0 like IEEE sqrt."

This means that it's unsafe to replace sqrt with llvm.sqrt unless the
call is annotated with nnan.

Thanks to Hal Finkel for pointing this out!

llvm-svn: 265521
2016-04-06 07:04:53 +00:00
Duncan P. N. Exon Smith 3e0430e0a8 IR: Move MDStrings to a BumpPtrAllocator
We never delete any MDString until the context is destroyed.  Might as
well throw them onto a BumpPtrAllocator.

llvm-svn: 265520
2016-04-06 06:41:54 +00:00
Duncan P. N. Exon Smith bdfc984679 IRMover: Steal arguments when moving functions, NFC
Instead of copying arguments from the source function to the
destination, steal them.  This has a few advantages.

  - The ValueMap doesn't need to be seeded with (or cleared of)
    Arguments.

  - Often the destination function won't have created any arguments yet,
    so this avoids malloc traffic.

  - Argument names don't need to be copied.

Because argument lists are lazy, this required a new
Function::stealArgumentListFrom helper.

llvm-svn: 265519
2016-04-06 06:38:15 +00:00
Davide Italiano 22680e1c5c Revert "[IRVerifier] Don't crash on invalid DIFile inside DISubprogram."
This reverts commit r265515 as lots of tests need to be fixed before
this actually can go in.

llvm-svn: 265517
2016-04-06 04:34:38 +00:00
Richard Trieu f35d4b0928 Add parentheses to silence warning.
llvm-svn: 265516
2016-04-06 04:22:00 +00:00
Davide Italiano 2deceb0339 [IRVerifier] Don't crash on invalid DIFile inside DISubprogram.
llvm-svn: 265515
2016-04-06 03:57:47 +00:00
Davide Italiano 8dc23a3cb5 [IRVerifier] Avoid crashing on an invalid compile unit.
llvm-svn: 265514
2016-04-06 03:07:58 +00:00
Matthias Braun 8e594fdf19 AArch64: Fix compile error
Fixed to adapt a use of enterBasicBlock() in my last commit (because I
had follow on patches in my repository that change the code).

llvm-svn: 265513
2016-04-06 02:59:44 +00:00
Matthias Braun 7dc03f060e RegisterScavenger: Take a reference as enterBasicBlock() argument.
Make it obvious that the argument cannot be nullptr.
Remove an unnecessary nullptr check in initRegState.

llvm-svn: 265511
2016-04-06 02:47:09 +00:00
Matthias Braun 61da4cef6c LivePhysRegs: removeReg() must remove aliased registers
We must remove all aliased registers which may be more than the all sub
and super registers combined.

Bug found while reading the code. The bug does not affect any existing
target as the only use of register aliases I could found were control
registers on ARM and Hexagon which are all reserved.

llvm-svn: 265510
2016-04-06 02:46:35 +00:00
Matthias Braun 3bb0fcc118 LivePhysRegs: Remove redundant check
llvm-svn: 265509
2016-04-06 02:46:04 +00:00
Duncan P. N. Exon Smith 6f2e37429a ValueMapper: Fix delayed blockaddress handling after r265273
r265273 added Mapper::mapBlockAddress, which delays mapping a
blockaddress value until the function has a body.  The condition was
backwards, and should be checking Function::empty instead of
GlobalValue::isDeclaration.

llvm-svn: 265508
2016-04-06 02:25:12 +00:00
Duncan P. N. Exon Smith 29883866a4 AsmParser: Don't crash on unresolved !tbaa
Instead of crashing, give a nice error.  As a drive-by, fix the location
associated with the errors for unresolved metadata (the location was off
by one token).

llvm-svn: 265507
2016-04-06 02:06:40 +00:00
Chuang-Yu Cheng 2e5973ef74 [ppc64] Enable sibling call optimization on ppc64 ELFv1/ELFv2 abi
This patch enable sibling call optimization on ppc64 ELFv1/ELFv2 abi, and
add a couple of test cases. This patch also passed llvm/clang bootstrap
test, and spec2006 build/run/result validation.

Original issue: https://llvm.org/bugs/show_bug.cgi?id=25617

Great thanks to Tom's (tjablin) help, he contributed a lot to this patch.
Thanks Hal and Kit's invaluable opinions!

Reviewers: hfinkel kbarton

http://reviews.llvm.org/D16315

llvm-svn: 265506
2016-04-06 02:04:38 +00:00
Chuang-Yu Cheng 024a623c55 [Power9] Implement add-pc, multiply-add, modulo, extend-sign-shift, random number, set bool, and dfp test significance
This patch implement the following instructions:
- addpcis subpcis
- maddhd maddhdu maddld
- modsw moduw modsd modud
- darn
- extswsli extswsli.
- setb
- dtstsfi dtstsfiq

Total 15 instructions

Reviewers: nemanjai hfinkel tjablin amehsan kbarton

http://reviews.llvm.org/D17885

llvm-svn: 265505
2016-04-06 01:47:02 +00:00