Commit Graph

52 Commits

Author SHA1 Message Date
Reed Kotler 4416cdadd5 Expand mips16 SelT form pseudso/macros.
llvm-svn: 175862
2013-02-22 05:10:51 +00:00
Reed Kotler 97ba5f2772 Expand the sel pseudo/macro. This generates basic blocks where previously
there were inline br .+4 instructions. Soon everything can enjoy the
full instruction scheduling experience.

llvm-svn: 175718
2013-02-21 04:22:38 +00:00
Reed Kotler 7b503c2b03 Expand pseudos/macros:
SltCCRxRy16, SltiCCRxImmX16, SltiuCCRxImmX16, SltuCCRxRy16
$T8 shows up as register $24 when emitted from C++ code so we had
to change some tests that were already there for this functionality.

llvm-svn: 175593
2013-02-20 05:45:15 +00:00
Reed Kotler 3e457f505e Expand pseudos/macros BteqzT8SltiX16, BteqzT8SltiuX16,
BtnezT8SltiX16, BtnezT8SltiuX16 .

llvm-svn: 175486
2013-02-19 03:56:57 +00:00
Reed Kotler d82171990f Expand pseudos BteqzT8CmpiX16 and BtnezT8CmpiX16.
llvm-svn: 175474
2013-02-19 00:20:58 +00:00
Reed Kotler 6879e56dc7 Expand pseudo/macro BteqzT8SltuX16 . There is no test case because
at this time, llvm is generating a different but equivalent pattern
that would lead to this instruction. I am trying to think of a way
to get it to generate this. If I can't, I may just remove the pseudo.

llvm-svn: 175419
2013-02-18 04:55:38 +00:00
Reed Kotler cb37409b92 Beginning of expanding all current mips16 macro/pseudo instruction sequences.
This expansion will be moved to expandISelPseudos as soon as I can figure
out how to do that. There are other instructions which use this 
ExpandFEXT_T8I816_ins and as soon as I have finished expanding them all,
I will delete the macro asm string text so it has no way to be used
in the future.

llvm-svn: 175413
2013-02-18 00:59:04 +00:00
Reed Kotler 61b474f97d Clean up mips16 td file in preparation for massive pseudo lowering work.
llvm-svn: 175379
2013-02-16 23:39:52 +00:00
Reed Kotler ec8a54904e Remove the form field from Mips16 instruction formats and set things
up so that we can apply the direct object emitter patch. This patch
should be a nop right now and it's test is to not break what is already
there.
 

llvm-svn: 175126
2013-02-14 03:05:25 +00:00
Reed Kotler f662cff689 For Mips 16, add the optimization where the 16 bit form of addiu sp can be used
if the offset fits in 11 bits. This makes use of the fact that the abi
requires sp to be 8 byte aligned so the actual offset can fit in 8
bits. It will be shifted left and sign extended before being actually used.
The assembler or direct object emitter will shift right the 11 bit
signed field by 3 bits. We don't need to deal with that here.

llvm-svn: 175073
2013-02-13 20:28:27 +00:00
Reed Kotler 9cb8e7b9f5 Make jumptables work for -static
llvm-svn: 175044
2013-02-13 08:32:14 +00:00
Reed Kotler b9bf8dca47 Add the 16 bit version of addiu. To the assembler, the 16 and 32 bit are the
same so we put in the comment field an indicator when we think we are
emitting the 16 bit version. For the direct object emitter, the difference is 
important as well as for other passes which need an accurate count of 
program size. There will be other similar putbacks to this for various
instructions.

llvm-svn: 174747
2013-02-08 21:42:56 +00:00
Reed Kotler 4a230ffa96 Make sure we call externals from libraries properly when -static.
For example, when we are doing mips16 hard float or soft float.

llvm-svn: 174583
2013-02-07 04:34:51 +00:00
Reed Kotler ec60f7d335 Enable jumps when in -static mode.
llvm-svn: 174580
2013-02-07 03:49:51 +00:00
Reed Kotler f8933f83f0 Start static relocation implementation for mips16.
This checkin makes hello world work. 

llvm-svn: 174264
2013-02-02 04:07:35 +00:00
Jack Carter 7ab15fafe3 This is a resubmittal. For some reason it broke the bots yesterday
but I cannot reproduce the problem and have scrubed my sources and
even tested with llvm-lit -v --vg.
Formatting fixes. Mostly long lines and 
blank spaces at end of lines.

Contributer: Jack Carter
 
llvm-svn: 172882
2013-01-19 02:00:40 +00:00
Reed Kotler d019dbf75e fix most of remaining issues with large frames.
these patches are tested a lot by test-suite but
make check tests are forthcoming once the next
few patches that complete this are committed.
with the next few patches the pass rate for mips16 is
near 100%

llvm-svn: 170656
2012-12-20 04:07:42 +00:00
Reed Kotler 3aad762d1d Add some missing Defs and Uses.
llvm-svn: 170493
2012-12-19 04:06:15 +00:00
Chandler Carruth f12e3a67db Switch LLVM_USE_RVALUE_REFERENCES to LLVM_HAS_RVALUE_REFERENCES.
Rationale:
1) This was the name in the comment block. ;]
2) It matches Clang's __has_feature naming convention.
3) It matches other compiler-feature-test conventions.

Sorry for the noise. =]

I've also switch the comment block to use a \brief tag and not duplicate
the name.

llvm-svn: 168996
2012-11-30 11:45:22 +00:00
Reed Kotler 27a7229c47 Implement ADJCALLSTACKUP and ADJCALLSTACKDOWN
llvm-svn: 167107
2012-10-31 05:21:10 +00:00
Reed Kotler a811753716 Change mips16 delay slot jumps to non delay slot forms by default.
We will make them delay slot forms if there is something that can be
placed in the delay slot during a separate pass. Mips16 extended instructions
cannot be placed in delay slots.

llvm-svn: 166990
2012-10-30 00:54:49 +00:00
Reed Kotler 740981e35c Implement patterns for extloadi8 and extloadi16
llvm-svn: 166960
2012-10-29 19:39:04 +00:00
Reed Kotler e6c31579be Implement brind operator for mips16.
llvm-svn: 166903
2012-10-28 23:08:07 +00:00
Reed Kotler 3589dd74ac This patch is for the implementation of mips16 complex pattern addr16.
Previously mips16 was sharing the pattern addr which is used for mips32
and mips64. This had a number of problems:
1) Storing and loading byte and halfword quantities for mips16 has particular
problems due to the primarily non mips16 nature of SP. When we must
load/store byte/halfword stack objects in a function, we must create a mips16
alias register for SP. This functionality is tested in stchar.ll.
2) We need to have an FP register under certain conditions (such as 
dynamically sized alloca). We use mips16 register S0 for this purpose.
In this case, we also use this register when accessing frame objects so this
issue also affects the complex pattern addr16. This functionality is
tested in alloca16.ll.

The Mips16InstrInfo.td has been updated to use addr16 instead of addr.

The complex pattern C++ function for addr has been copied to addr16 and
updated to reflect the above issues.

llvm-svn: 166897
2012-10-28 06:02:37 +00:00
Reed Kotler 7e4d9969cb Implement MipsHi for mips16
llvm-svn: 166852
2012-10-27 00:57:14 +00:00
Reed Kotler b650f6bbe7 implement mips16 tls global addr
llvm-svn: 166827
2012-10-26 22:57:32 +00:00
Reed Kotler 4e1c629567 (no commit message)
llvm-svn: 166780
2012-10-26 16:18:19 +00:00
Reed Kotler 287f0449a2 Implement carry for subtract/add for mips16
llvm-svn: 166755
2012-10-26 04:46:26 +00:00
Reed Kotler e47873ab89 implement large (>16 bit) constant loading.
llvm-svn: 166749
2012-10-26 03:09:34 +00:00
Reed Kotler 097556d6bd implement mips16 patterns for select nodes
llvm-svn: 166721
2012-10-25 21:33:30 +00:00
Reed Kotler 164bb37c7b implement setXX patterns
llvm-svn: 166459
2012-10-23 01:35:48 +00:00
Reed Kotler 6743924a32 Add conditional branch instructions and their patterns.
llvm-svn: 166134
2012-10-17 22:29:54 +00:00
Reed Kotler cf11c59e2f Div, Rem int/unsigned int
llvm-svn: 165783
2012-10-12 02:01:09 +00:00
Reed Kotler 0f2e44a1cb Reorder some parts of the td file to by in alphabetical order
llvm-svn: 165590
2012-10-10 01:58:16 +00:00
Reed Kotler 240322140e Patch for integer multiply, signed/unsigned, long/long long.
llvm-svn: 165322
2012-10-05 18:27:54 +00:00
Reed Kotler 210ebe93f3 1. Add load/store words from the stack
2. As part of this, added assembly format FEXT_RI16_SP_explicit_ins and
moved other lines for FEXT_RI16 formats to be in the right place in the code.
3. Added mayLoad and mayStore assignements for the load/store instructions added and for ones already there that did not have this assignment.
4. Another patch will deal with the problem of load/store byte/halfword to the stack. This is a particular Mips16 problem.

llvm-svn: 164811
2012-09-28 02:26:24 +00:00
Reed Kotler 7b10400709 blank line for test commit
llvm-svn: 164640
2012-09-25 22:34:20 +00:00
Akira Hatanaka cd04e2b8e2 Properly save and restore RA and Mips16 callee save registers S0,S1
Patch by Reed Kotler.

llvm-svn: 164349
2012-09-21 01:08:16 +00:00
Akira Hatanaka 3e7ba76157 Remove aligned/unaligned load/store fragments defined in MipsInstrInfo.td and
use load/store fragments defined in TargetSelectionDAG.td in place of them.
Unaligned loads/stores are either expanded or lowered to target-specific nodes,
so instruction selection should see only aligned load/store nodes.

No changes in functionality.

llvm-svn: 163960
2012-09-15 01:52:08 +00:00
Akira Hatanaka 0fbaec2246 mips16 fixes.
1. Add MoveR3216
2. Correct spelling for Move32R16

Patch by Reed Kotler.

llvm-svn: 163869
2012-09-14 03:21:56 +00:00
Akira Hatanaka 22bec282e9 1. Redo mips16 instructions to avoid multiple opcodes for same instruction.
Change these to patterns.
2. Add another 16 instructions.

Patch by Reed Kotler.

llvm-svn: 161272
2012-08-03 22:57:02 +00:00
Akira Hatanaka a66d676b20 Define ADJCALLSTACKDOWN/UP nodes. These nodes are emitted regardless of whether
or not it is in mips16 mode. Define MipsPseudo (mode-independant pseudo) and
PseudoSE (mips32/64 pseudo) classes.

llvm-svn: 161071
2012-07-31 19:13:07 +00:00
Akira Hatanaka 64626fc20f Fix call setup for PIC.
Patch by Reed Kotler.

llvm-svn: 160774
2012-07-26 02:24:43 +00:00
Akira Hatanaka 26e9ecb7a3 Add basic ability to setup call frame, and make procedure calls.
Hello world will compile and execute with this patch.

Patch by Reed Kotler.

llvm-svn: 160651
2012-07-23 23:45:54 +00:00
Akira Hatanaka b49c68a65d Revert accidental commit.
llvm-svn: 160598
2012-07-21 02:20:33 +00:00
Akira Hatanaka f73e362758 Add VK_Mips_HIGHER and VK_Mips_HIGHEST to MCSymbolRefExpr::VariantKind.
Test case will be added later when long branch patch is checked in.

llvm-svn: 160597
2012-07-21 02:15:19 +00:00
Akira Hatanaka f640f040d1 Clean up Mips16InstrFormats.td and Mips16InstrInfo.td.
Patch by Reed Kotler.

llvm-svn: 160403
2012-07-17 22:55:34 +00:00
Jakob Stoklund Olesen ed6c0408fa Remove variable_ops from call instructions in most targets.
Call instructions are no longer required to be variadic, and
variable_ops should only be used for instructions that encode a variable
number of arguments, like the ARM stm/ldm instructions.

llvm-svn: 160189
2012-07-13 20:44:29 +00:00
Akira Hatanaka efff7b763b Make register Mips::RA allocatable if not in mips16 mode.
llvm-svn: 159971
2012-07-10 00:19:06 +00:00
Akira Hatanaka 765c312314 1. fix null program output after some other changes
2. re-enable null.ll test
3. fix some minor style violations

Patch by Reed Kotler.

llvm-svn: 158935
2012-06-21 20:39:10 +00:00