Commit Graph

332 Commits

Author SHA1 Message Date
Evan Cheng 8cbbcb1f2f Encode VFP load / store instructions.
llvm-svn: 59084
2008-11-11 21:48:44 +00:00
Evan Cheng 38c9a14a88 Encode VFP conversion instructions.
llvm-svn: 59074
2008-11-11 19:40:26 +00:00
Evan Cheng ac2af2fdb2 Encode VFP arithmetic instructions.
llvm-svn: 59016
2008-11-11 02:11:05 +00:00
Evan Cheng 7095cd2af2 Jump table JIT support. Work in progress.
llvm-svn: 58836
2008-11-07 09:06:08 +00:00
Evan Cheng 98dc53e926 Encode misc arithmetic instructions.
llvm-svn: 58828
2008-11-07 01:41:35 +00:00
Evan Cheng 49d665218c Encode extend instructions; more clean up.
llvm-svn: 58818
2008-11-06 22:15:19 +00:00
Evan Cheng aa03cd3336 - Improve naming consistency: Branch -> BrFrm, BranchMisc -> BrMiscFrm.
- Consolidate instruction formats.
- Other clean up.

llvm-svn: 58808
2008-11-06 17:48:05 +00:00
Evan Cheng 47b546d75f Remove opcode from instruction TS flags; add MOVCC support; fix addrmode3 encoding bug.
llvm-svn: 58800
2008-11-06 08:47:38 +00:00
Evan Cheng 36ae40342f Handle smul<x><y>, smulw<y>, smla<x><y>, smlaw<y>.
llvm-svn: 58793
2008-11-06 03:35:07 +00:00
Evan Cheng 2686c8fb34 Fix encoding of multiple instructions with 3 src operands; also handle smmul, smmla, and smmls.
llvm-svn: 58789
2008-11-06 01:21:28 +00:00
Evan Cheng fd2adbfa28 Encode pic load / store instructions; fix some encoding bugs.
llvm-svn: 58780
2008-11-05 23:22:34 +00:00
Evan Cheng 81889d010c Restructure ARM code emitter to use instruction formats instead of addressing modes to determine how to encode instructions.
llvm-svn: 58764
2008-11-05 18:35:52 +00:00
Evan Cheng 453844c352 LDM_RET restores pc, do not set 's' bit which would restore CPSR from SPSR.
llvm-svn: 58707
2008-11-04 17:57:07 +00:00
Jim Grosbach 4d0549e3be Add binary encoding support for multiply instructions. Some blanks left to fill in, but the basics are there.
llvm-svn: 58626
2008-11-03 18:38:31 +00:00
Jim Grosbach b7c01f5f48 Update ARM Insn encoding to get endian-ness to match the documentation (31-0 left to right)
llvm-svn: 57524
2008-10-14 20:36:24 +00:00
Evan Cheng 7848cfcd77 Fix addrmode1 instruction encodings; fix bx_ret encoding.
llvm-svn: 56277
2008-09-17 07:53:38 +00:00
Evan Cheng 937569afe3 Specify instruction encoding using range list to avoid endianess issues.
llvm-svn: 56276
2008-09-17 07:16:21 +00:00
Evan Cheng 12134701ec Revert 56176. All those instruction formats are still needed.
llvm-svn: 56180
2008-09-13 01:35:33 +00:00
Evan Cheng c5c74f36fd Eliminate unnecessary instruction formats.
llvm-svn: 56176
2008-09-12 23:15:39 +00:00
Evan Cheng d1424c4eca Addrmode 1 S bit can be dynamically set. Look for CPSR def.
llvm-svn: 56172
2008-09-12 22:45:55 +00:00
Evan Cheng fa558788e7 Control flow instruction encodings.
llvm-svn: 55601
2008-09-01 08:25:56 +00:00
Evan Cheng c288cc0572 ldm / stm instruction encodings.
llvm-svn: 55599
2008-09-01 07:48:18 +00:00
Evan Cheng c37532b24a AXI2 and AXI3 instruction encodings.
llvm-svn: 55598
2008-09-01 07:34:13 +00:00
Evan Cheng a282723499 Reorganize instruction formats again; AXI1 encoding.
llvm-svn: 55597
2008-09-01 07:19:00 +00:00
Evan Cheng 169eccc24e addrmode3 instruction encodings.
llvm-svn: 55596
2008-09-01 07:00:14 +00:00
Evan Cheng 624844b4dd Reorganize some instruction format definitions. No functionality change.
llvm-svn: 55594
2008-09-01 01:51:14 +00:00
Evan Cheng cccca875b1 Rest of addrmode2 instruction encodings.
llvm-svn: 55593
2008-09-01 01:27:33 +00:00
Evan Cheng 01fd3f129a Addr2 word / byte load encodings.
llvm-svn: 55591
2008-08-31 19:02:21 +00:00
Evan Cheng 5b6c931e1f Addr1 instructions opcodes are encoded in bits 21-24; encode S bit.
llvm-svn: 55590
2008-08-31 18:32:16 +00:00
Evan Cheng c139c221dd addrmode1 (data processing) instruction encoding: bits 5-6 are 0, bits 7-10 encode the opcode.
llvm-svn: 55531
2008-08-29 07:40:52 +00:00
Evan Cheng ee98fa9db2 More refactoring.
llvm-svn: 55528
2008-08-29 06:41:12 +00:00
Evan Cheng 2d37f19ef2 Refactor ARM instruction format definitions into a separate file. No functionality changes.
llvm-svn: 55518
2008-08-28 23:39:26 +00:00