8bf01fc663
[fast-isel] Fallback to SelectionDAG isel if we require strict alignment for
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non-aligned i32 loads/stores.
rdar://12304911
llvm-svn: 164381
2012-09-21 16:58:35 +00:00
1a38004c1b
llvm/test/CodeGen/ARM/fast-isel.ll: Fix possible typos, s/@unaligned_i16_store/@unaligned_i16_load/g.
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I guess this had apparently passed in +Asserts possibly due to verborsity.
llvm-svn: 164350
2012-09-21 01:15:05 +00:00
8ff5a4aa79
Testcase does not need to be this strict.
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llvm-svn: 164347
2012-09-21 00:47:08 +00:00
1fb301aa41
Add newline.
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llvm-svn: 164346
2012-09-21 00:43:18 +00:00
2364f58326
[fast-isel] Fallback to SelectionDAG isel if we require strict alignment for
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non-halfword-aligned i16 loads/stores.
rdar://12304911
llvm-svn: 164345
2012-09-21 00:41:42 +00:00
aa9cb9df59
[fast-isel] Add support for selecting @llvm.trap().
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llvm-svn: 156646
2012-05-11 21:33:49 +00:00
6a63a74113
[fast-isel] Fold "urem x, pow2" -> "and x, pow2-1". This should fix the 271%
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execution-time regression for nsieve-bits on the ARMv7 -O0 -g nightly tester.
This may also improve compile-time on architectures that would otherwise
generate a libcall for urem (e.g., ARM) or fall back to the DAG selector.
rdar://10810716
llvm-svn: 153230
2012-03-22 00:21:17 +00:00
8cdce7e690
Use getRegForValue() to materialize the address of ARM globals.
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This enables basic local CSE, giving us 20% smaller code for
consumer-typeset in -O0 builds.
<rdar://problem/10658692>
llvm-svn: 147720
2012-01-07 04:07:22 +00:00
68f034ee1a
Use movw+movt in ARMFastISel::ARMMaterializeGV.
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This eliminates a lot of constant pool entries for -O0 builds of code
with many global variable accesses.
This speeds up -O0 codegen of consumer-typeset by 2x because the
constant island pass no longer has to look at thousands of constant pool
entries.
<rdar://problem/10629774>
llvm-svn: 147712
2012-01-07 01:47:05 +00:00
68132d8093
ARM target code clean up. Check for iOS, not Darwin where it makes sense.
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llvm-svn: 146981
2011-12-20 18:26:50 +00:00
4020ae75ea
Add newline at EOF.
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llvm-svn: 146538
2011-12-14 01:34:39 +00:00
563de603f7
[fast-isel] Unaligned loads of floats are not supported. Therefore, convert to a regular
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load and then move the result from a GPR to a FPR.
llvm-svn: 146502
2011-12-13 19:22:14 +00:00
c77830d21e
[arm-fast-isel] Doublewords only require word-alignment.
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rdar://10528060
llvm-svn: 145891
2011-12-06 01:44:17 +00:00
ec3b77e00d
[arm-fast-isel] Unaligned stores of floats require special care.
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rdar://10510150
llvm-svn: 145742
2011-12-03 02:21:57 +00:00
4e0dbee62b
ARM Darwin default relocation model is PIC.
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This matches clang, so default options in llc and friends are now closer to
clang's defaults.
llvm-svn: 140863
2011-09-30 17:41:35 +00:00
581da64241
Simplify printing of ARM shifted immediates.
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Print shifted immediate values directly rather than as a payload+shifter
value pair. This makes for more readable output assembly code, simplifies
the instruction printer, and is consistent with how Thumb immediates are
displayed.
llvm-svn: 134902
2011-07-11 16:48:36 +00:00
86585798af
Add ARM fast-isel support for materializing the address of a global in cases where the global uses an indirect symbol.
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rdar://9431157
llvm-svn: 132522
2011-06-03 01:13:19 +00:00
c70355195c
Rewrite fast-isel integer cast handling to handle more cases, and to be simpler and more consistent.
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The practical effects here are that x86-64 fast-isel can now handle trunc from i8 to i1, and ARM fast-isel can handle many more constructs involving integers narrower than 32 bits (including loads, stores, and many integer casts).
rdar://9437928 .
llvm-svn: 132099
2011-05-25 23:49:02 +00:00
4105ed1523
Make FastEmit_ri_ try a bit harder to succeed for supported operations; FastEmit_i can fail for non-Thumb2 ARM. Makes ARMSimplifyAddress work correctly, and reduces the number of fast-isel bailouts on non-Thumb ARM.
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llvm-svn: 130560
2011-04-29 23:34:52 +00:00
328bad02fa
Switch to ImmLeaf (which can be used by FastISel) for a few more common ARM/Thumb2 patterns.
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llvm-svn: 130552
2011-04-29 22:48:03 +00:00
8d46b47787
Add trunc->branch support, this won't help with clang's i8->i1 truncations
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for bools, but is a start.
llvm-svn: 130534
2011-04-29 20:02:39 +00:00
964943780b
Recommit this change and remove the failing part of the test - it didn't
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pass in the first place and was masked by earlier failures not warning
and aborting the block.
llvm-svn: 119184
2010-11-15 21:11:06 +00:00
a08ccc8cb9
This should be still failing, but is. Disable it with the
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forget-me-stick for now.
llvm-svn: 118950
2010-11-13 00:25:06 +00:00
7b92c2a9a0
Revert r116220 - thus turning arm fast isel back on by default.
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llvm-svn: 116762
2010-10-18 22:53:53 +00:00
e2a0b6841a
Found a bug turning this on by default. Disable again for now.
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llvm-svn: 116220
2010-10-11 20:26:21 +00:00
6002b3b3e1
Remove now non-existent option.
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llvm-svn: 116219
2010-10-11 20:21:21 +00:00
c237a849e3
Re-apply r113679, which was reverted in r113720, which added a paid of new instcombine transforms
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to expose greater opportunities for store narrowing in codegen. This patch fixes a potential
infinite loop in instcombine caused by one of the introduced transforms being overly aggressive.
llvm-svn: 113763
2010-09-13 17:59:27 +00:00
26abd3e0c2
Revert 113679, it was causing an infinite loop in a testcase that I've sent
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on to Owen.
llvm-svn: 113720
2010-09-12 06:09:23 +00:00
ca2ec95154
Remove ssp from this test.
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llvm-svn: 113392
2010-09-08 19:32:34 +00:00
6b1533a1a9
Add another basic test cribbed from the x86 fast-isel tests.
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llvm-svn: 112036
2010-08-25 07:57:29 +00:00
37d547aee6
Run this on thumb and arm.
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llvm-svn: 112035
2010-08-25 07:53:15 +00:00
e58c03698e
Make this testcase actually executed with fast-isel on arm.
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llvm-svn: 112033
2010-08-25 07:47:00 +00:00
84bdfd80df
Baby steps towards ARM fast-isel.
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llvm-svn: 109047
2010-07-21 22:26:11 +00:00
Chad Rosier