fa1b0fa77e
[mips][msa] Made the operand register sets optional for the 3RF_4RF format
...
Their default is to be the same as the result register set.
No functional change
llvm-svn: 190150
2013-09-06 12:44:13 +00:00
d719f5281c
[mips][msa] Made the operand register sets optional for the 3RF formats
...
Their default is to be the same as the result register set.
No functional change
llvm-svn: 190146
2013-09-06 12:32:57 +00:00
b2b7c0a044
[mips][msa] Made the operand register sets optional for the 3R_4R format
...
Their default is to be the same as the result register set.
No functional change
llvm-svn: 190145
2013-09-06 12:30:43 +00:00
2322f5d090
[mips][msa] Made the operand register sets optional for the 2RF format
...
Their default is to be the same as the result register set.
No functional change
llvm-svn: 190143
2013-09-06 12:28:13 +00:00
9148218cbe
[mips][msa] Made the operand register sets optional for the I8 format
...
Their default is to be the same as the result register set.
No functional change
llvm-svn: 190142
2013-09-06 12:25:47 +00:00
92c40a5796
[mips][msa] Made the operand register sets optional for the I5 and SI5 formats
...
Their default is to be the same as the result register set.
No functional change
llvm-svn: 190141
2013-09-06 12:23:19 +00:00
13d5e2f376
[mips][msa] Made the operand register sets optional for the BIT_[BHWD] formats
...
Their default is to be the same as the result register set.
No functional change
llvm-svn: 190140
2013-09-06 12:10:24 +00:00
63b97d5ae5
[mips][msa] Sorted MSA_BIT_[BHWD]_DESC_BASE into ascending order of element size
...
No functional change
llvm-svn: 190134
2013-09-06 11:01:38 +00:00
02a3007608
[mips][msa] Made the operand register sets optional for the 3R format
...
Their default is to be the same as the result register set.
No functional change
llvm-svn: 190133
2013-09-06 10:59:24 +00:00
db12ab7b7c
[mips][msa] Made the InstrItinClass argument optional since it is always NoItinerary at the moment.
...
No functional change
llvm-svn: 190131
2013-09-06 10:55:15 +00:00
ce09d07824
[mips][msa] Added bnz.df, bnz.v, bz.df, and bz.v
...
These intrinsics are legalized to V(ALL|ANY)_(NON)?ZERO nodes,
are matched as SN?Z_[BHWDV]_PSEUDO pseudo's, and emitted as
a branch/mov sequence to evaluate to 0 or 1.
Note: The resulting code is sub-optimal since it doesnt seem to be possible
to feed the result of an intrinsic directly into a brcond. At the moment
it uses (SETCC (VALL_ZERO $ws), 0, SETEQ) and similar which unnecessarily
evaluates the boolean twice.
llvm-svn: 189478
2013-08-28 12:14:50 +00:00
e6ed5b72f1
[mips][msa] Added load/store intrinsics.
...
llvm-svn: 189476
2013-08-28 12:04:29 +00:00
ba9c8505fb
[mips][msa] Added move.v
...
llvm-svn: 189471
2013-08-28 10:44:47 +00:00
f9aa1d1902
[mips][msa] Added cfcmsa, and ctcmsa
...
The MSA control registers have been added as reserved registers,
and are only used via ISD::Copy(To|From)Reg. The intrinsics are lowered
into these nodes.
llvm-svn: 189468
2013-08-28 10:26:24 +00:00
0dc0dd464b
[mips][msa] Added f[cs]af, f[cs]or, f[cs]ueq, f[cs]ul[et], f[cs]une, fsun, ftrunc_[su], hadd_[su], hsub_[su], sr[al]r, sr[al]ri
...
llvm-svn: 189467
2013-08-28 10:12:09 +00:00
70835f6025
[mips][msa] Added bitconverts for vector types for big and little-endian
...
llvm-svn: 189330
2013-08-27 09:40:30 +00:00
3c9a0ad444
[mips][msa] Split MSA128 regset into size-specific sets containing the same registers.
...
llvm-svn: 189095
2013-08-23 10:10:13 +00:00
4260527f5f
[mips][msa] Removed fcge, fcgt, fsge, fsgt
...
These instructions were present in a draft spec but were removed before
publication.
llvm-svn: 188782
2013-08-20 09:41:47 +00:00
f2a0f1d133
[mips][msa] Added insve
...
llvm-svn: 188777
2013-08-20 09:22:54 +00:00
869bdad93a
[mips][msa] Added and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.v
...
llvm-svn: 188767
2013-08-20 08:38:21 +00:00
6b32f892f2
Reverted test commit (r188556)
...
llvm-svn: 188557
2013-08-16 15:27:12 +00:00
7a2c9bc894
Test commit. Just a blank line
...
llvm-svn: 188556
2013-08-16 15:26:36 +00:00
d12e837f05
[Mips][msa] Added the simple builtins (madd_q to xori)
...
Includes:
madd_q, maddr_q, maddv, max_[asu], maxi_[su], min_[asu], mini_[su], mod_[su],
msub_q, msubr_q, msubv, mul_q, mulr_q, mulv, nloc, nlzc, nori, ori, pckev,
pckod, pcnt, sat_[su], shf, sld, sldi, sll, slli, splat, splati, sr[al],
sr[al]i, subs_[su], subss_u, subus_s, subv, subvi, vshf, xori
Patch by Daniel Sanders
llvm-svn: 188460
2013-08-15 14:22:07 +00:00
b95ee69163
[Mips][msa] Added the simple builtins (fadd to ftq)
...
Includes:
fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2,
fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin,
fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt,
fsne, fsqr, fsub, ftint_s, ftq
Patch by Daniel Sanders
llvm-svn: 188458
2013-08-15 13:45:36 +00:00
babdcc8c2c
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi)
...
Includes:
add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd],
bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti,
c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su],
dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve,
ldi
Patch by Daniel Sanders
llvm-svn: 188457
2013-08-15 12:24:57 +00:00
3a2c2d42b8
[Mips][msa] Added initial MSA support.
...
* msa SubtargetFeature
* registers
* ld.[bhwd], and st.[bhwd] instructions
Does not correctly prohibit use of both 32-bit FPU registers and MSA together.
Patch by Daniel Sanders
llvm-svn: 188313
2013-08-13 20:54:07 +00:00
Daniel Sanders